1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP ZCU106 4 * 5 * (C) Copyright 2016 - 2020, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9 10/dts-v1/; 11 12#include "zynqmp.dtsi" 13#include "zynqmp-clk-ccf.dtsi" 14#include <dt-bindings/input/input.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 17#include <dt-bindings/phy/phy.h> 18 19/ { 20 model = "ZynqMP ZCU106 RevA"; 21 compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; 22 23 aliases { 24 ethernet0 = &gem3; 25 gpio0 = &gpio; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 mmc0 = &sdhci1; 29 rtc0 = &rtc; 30 serial0 = &uart0; 31 serial1 = &uart1; 32 serial2 = &dcc; 33 spi0 = &qspi; 34 usb0 = &usb0; 35 }; 36 37 chosen { 38 bootargs = "earlycon"; 39 stdout-path = "serial0:115200n8"; 40 xlnx,eeprom = &eeprom; 41 }; 42 43 memory@0 { 44 device_type = "memory"; 45 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; 46 }; 47 48 gpio-keys { 49 compatible = "gpio-keys"; 50 autorepeat; 51 sw19 { 52 label = "sw19"; 53 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; 54 linux,code = <KEY_DOWN>; 55 wakeup-source; 56 autorepeat; 57 }; 58 }; 59 60 leds { 61 compatible = "gpio-leds"; 62 heartbeat-led { 63 label = "heartbeat"; 64 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; 65 linux,default-trigger = "heartbeat"; 66 }; 67 }; 68 69 ina226-u76 { 70 compatible = "iio-hwmon"; 71 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; 72 }; 73 ina226-u77 { 74 compatible = "iio-hwmon"; 75 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; 76 }; 77 ina226-u78 { 78 compatible = "iio-hwmon"; 79 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; 80 }; 81 ina226-u87 { 82 compatible = "iio-hwmon"; 83 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; 84 }; 85 ina226-u85 { 86 compatible = "iio-hwmon"; 87 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; 88 }; 89 ina226-u86 { 90 compatible = "iio-hwmon"; 91 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; 92 }; 93 ina226-u93 { 94 compatible = "iio-hwmon"; 95 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; 96 }; 97 ina226-u88 { 98 compatible = "iio-hwmon"; 99 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; 100 }; 101 ina226-u15 { 102 compatible = "iio-hwmon"; 103 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; 104 }; 105 ina226-u92 { 106 compatible = "iio-hwmon"; 107 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; 108 }; 109 ina226-u79 { 110 compatible = "iio-hwmon"; 111 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; 112 }; 113 ina226-u81 { 114 compatible = "iio-hwmon"; 115 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; 116 }; 117 ina226-u80 { 118 compatible = "iio-hwmon"; 119 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; 120 }; 121 ina226-u84 { 122 compatible = "iio-hwmon"; 123 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; 124 }; 125 ina226-u16 { 126 compatible = "iio-hwmon"; 127 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; 128 }; 129 ina226-u65 { 130 compatible = "iio-hwmon"; 131 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; 132 }; 133 ina226-u74 { 134 compatible = "iio-hwmon"; 135 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; 136 }; 137 ina226-u75 { 138 compatible = "iio-hwmon"; 139 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; 140 }; 141 142 /* 48MHz reference crystal */ 143 ref48: ref48M { 144 compatible = "fixed-clock"; 145 #clock-cells = <0>; 146 clock-frequency = <48000000>; 147 }; 148 149 refhdmi: refhdmi { 150 compatible = "fixed-clock"; 151 #clock-cells = <0>; 152 clock-frequency = <114285000>; 153 }; 154}; 155 156&can1 { 157 status = "okay"; 158 pinctrl-names = "default"; 159 pinctrl-0 = <&pinctrl_can1_default>; 160}; 161 162&dcc { 163 status = "okay"; 164}; 165 166&zynqmp_dpdma { 167 status = "okay"; 168}; 169 170&zynqmp_dpsub { 171 status = "okay"; 172 phy-names = "dp-phy0", "dp-phy1"; 173 phys = <&psgtr 1 PHY_TYPE_DP 0 3>, 174 <&psgtr 0 PHY_TYPE_DP 1 3>; 175}; 176 177/* fpd_dma clk 667MHz, lpd_dma 500MHz */ 178&fpd_dma_chan1 { 179 status = "okay"; 180}; 181 182&fpd_dma_chan2 { 183 status = "okay"; 184}; 185 186&fpd_dma_chan3 { 187 status = "okay"; 188}; 189 190&fpd_dma_chan4 { 191 status = "okay"; 192}; 193 194&fpd_dma_chan5 { 195 status = "okay"; 196}; 197 198&fpd_dma_chan6 { 199 status = "okay"; 200}; 201 202&fpd_dma_chan7 { 203 status = "okay"; 204}; 205 206&fpd_dma_chan8 { 207 status = "okay"; 208}; 209 210&gem3 { 211 status = "okay"; 212 phy-handle = <&phy0>; 213 phy-mode = "rgmii-id"; 214 pinctrl-names = "default"; 215 pinctrl-0 = <&pinctrl_gem3_default>; 216 phy0: ethernet-phy@c { 217 reg = <0xc>; 218 ti,rx-internal-delay = <0x8>; 219 ti,tx-internal-delay = <0xa>; 220 ti,fifo-depth = <0x1>; 221 ti,dp83867-rxctrl-strap-quirk; 222 }; 223}; 224 225&gpio { 226 status = "okay"; 227 pinctrl-names = "default"; 228 pinctrl-0 = <&pinctrl_gpio_default>; 229}; 230 231&gpu { 232 status = "okay"; 233}; 234 235&i2c0 { 236 status = "okay"; 237 clock-frequency = <400000>; 238 pinctrl-names = "default", "gpio"; 239 pinctrl-0 = <&pinctrl_i2c0_default>; 240 pinctrl-1 = <&pinctrl_i2c0_gpio>; 241 scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; 242 sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; 243 244 tca6416_u97: gpio@20 { 245 compatible = "ti,tca6416"; 246 reg = <0x20>; 247 gpio-controller; /* interrupt not connected */ 248 #gpio-cells = <2>; 249 /* 250 * IRQ not connected 251 * Lines: 252 * 0 - SFP_SI5328_INT_ALM 253 * 1 - HDMI_SI5328_INT_ALM 254 * 5 - IIC_MUX_RESET_B 255 * 6 - GEM3_EXP_RESET_B 256 * 10 - FMC_HPC0_PRSNT_M2C_B 257 * 11 - FMC_HPC1_PRSNT_M2C_B 258 * 2-4, 7, 12-17 - not connected 259 */ 260 }; 261 262 tca6416_u61: gpio@21 { 263 compatible = "ti,tca6416"; 264 reg = <0x21>; 265 gpio-controller; 266 #gpio-cells = <2>; 267 /* 268 * IRQ not connected 269 * Lines: 270 * 0 - VCCPSPLL_EN 271 * 1 - MGTRAVCC_EN 272 * 2 - MGTRAVTT_EN 273 * 3 - VCCPSDDRPLL_EN 274 * 4 - MIO26_PMU_INPUT_LS 275 * 5 - PL_PMBUS_ALERT 276 * 6 - PS_PMBUS_ALERT 277 * 7 - MAXIM_PMBUS_ALERT 278 * 10 - PL_DDR4_VTERM_EN 279 * 11 - PL_DDR4_VPP_2V5_EN 280 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON 281 * 13 - PS_DIMM_SUSPEND_EN 282 * 14 - PS_DDR4_VTERM_EN 283 * 15 - PS_DDR4_VPP_2V5_EN 284 * 16 - 17 - not connected 285 */ 286 }; 287 288 i2c-mux@75 { /* u60 */ 289 compatible = "nxp,pca9544"; 290 #address-cells = <1>; 291 #size-cells = <0>; 292 reg = <0x75>; 293 i2c@0 { 294 #address-cells = <1>; 295 #size-cells = <0>; 296 reg = <0>; 297 /* PS_PMBUS */ 298 u76: ina226@40 { /* u76 */ 299 compatible = "ti,ina226"; 300 #io-channel-cells = <1>; 301 label = "ina226-u76"; 302 reg = <0x40>; 303 shunt-resistor = <5000>; 304 }; 305 u77: ina226@41 { /* u77 */ 306 compatible = "ti,ina226"; 307 #io-channel-cells = <1>; 308 label = "ina226-u77"; 309 reg = <0x41>; 310 shunt-resistor = <5000>; 311 }; 312 u78: ina226@42 { /* u78 */ 313 compatible = "ti,ina226"; 314 #io-channel-cells = <1>; 315 label = "ina226-u78"; 316 reg = <0x42>; 317 shunt-resistor = <5000>; 318 }; 319 u87: ina226@43 { /* u87 */ 320 compatible = "ti,ina226"; 321 #io-channel-cells = <1>; 322 label = "ina226-u87"; 323 reg = <0x43>; 324 shunt-resistor = <5000>; 325 }; 326 u85: ina226@44 { /* u85 */ 327 compatible = "ti,ina226"; 328 #io-channel-cells = <1>; 329 label = "ina226-u85"; 330 reg = <0x44>; 331 shunt-resistor = <5000>; 332 }; 333 u86: ina226@45 { /* u86 */ 334 compatible = "ti,ina226"; 335 #io-channel-cells = <1>; 336 label = "ina226-u86"; 337 reg = <0x45>; 338 shunt-resistor = <5000>; 339 }; 340 u93: ina226@46 { /* u93 */ 341 compatible = "ti,ina226"; 342 #io-channel-cells = <1>; 343 label = "ina226-u93"; 344 reg = <0x46>; 345 shunt-resistor = <5000>; 346 }; 347 u88: ina226@47 { /* u88 */ 348 compatible = "ti,ina226"; 349 #io-channel-cells = <1>; 350 label = "ina226-u88"; 351 reg = <0x47>; 352 shunt-resistor = <5000>; 353 }; 354 u15: ina226@4a { /* u15 */ 355 compatible = "ti,ina226"; 356 #io-channel-cells = <1>; 357 label = "ina226-u15"; 358 reg = <0x4a>; 359 shunt-resistor = <5000>; 360 }; 361 u92: ina226@4b { /* u92 */ 362 compatible = "ti,ina226"; 363 #io-channel-cells = <1>; 364 label = "ina226-u92"; 365 reg = <0x4b>; 366 shunt-resistor = <5000>; 367 }; 368 }; 369 i2c@1 { 370 #address-cells = <1>; 371 #size-cells = <0>; 372 reg = <1>; 373 /* PL_PMBUS */ 374 u79: ina226@40 { /* u79 */ 375 compatible = "ti,ina226"; 376 #io-channel-cells = <1>; 377 label = "ina226-u79"; 378 reg = <0x40>; 379 shunt-resistor = <2000>; 380 }; 381 u81: ina226@41 { /* u81 */ 382 compatible = "ti,ina226"; 383 #io-channel-cells = <1>; 384 label = "ina226-u81"; 385 reg = <0x41>; 386 shunt-resistor = <5000>; 387 }; 388 u80: ina226@42 { /* u80 */ 389 compatible = "ti,ina226"; 390 #io-channel-cells = <1>; 391 label = "ina226-u80"; 392 reg = <0x42>; 393 shunt-resistor = <5000>; 394 }; 395 u84: ina226@43 { /* u84 */ 396 compatible = "ti,ina226"; 397 #io-channel-cells = <1>; 398 label = "ina226-u84"; 399 reg = <0x43>; 400 shunt-resistor = <5000>; 401 }; 402 u16: ina226@44 { /* u16 */ 403 compatible = "ti,ina226"; 404 #io-channel-cells = <1>; 405 label = "ina226-u16"; 406 reg = <0x44>; 407 shunt-resistor = <5000>; 408 }; 409 u65: ina226@45 { /* u65 */ 410 compatible = "ti,ina226"; 411 #io-channel-cells = <1>; 412 label = "ina226-u65"; 413 reg = <0x45>; 414 shunt-resistor = <5000>; 415 }; 416 u74: ina226@46 { /* u74 */ 417 compatible = "ti,ina226"; 418 #io-channel-cells = <1>; 419 label = "ina226-u74"; 420 reg = <0x46>; 421 shunt-resistor = <5000>; 422 }; 423 u75: ina226@47 { /* u75 */ 424 compatible = "ti,ina226"; 425 #io-channel-cells = <1>; 426 label = "ina226-u75"; 427 reg = <0x47>; 428 shunt-resistor = <5000>; 429 }; 430 }; 431 i2c@2 { 432 #address-cells = <1>; 433 #size-cells = <0>; 434 reg = <2>; 435 /* MAXIM_PMBUS - 00 */ 436 max15301@a { /* u46 */ 437 compatible = "maxim,max15301"; 438 reg = <0xa>; 439 }; 440 max15303@b { /* u4 */ 441 compatible = "maxim,max15303"; 442 reg = <0xb>; 443 }; 444 max15303@10 { /* u13 */ 445 compatible = "maxim,max15303"; 446 reg = <0x10>; 447 }; 448 max15301@13 { /* u47 */ 449 compatible = "maxim,max15301"; 450 reg = <0x13>; 451 }; 452 max15303@14 { /* u7 */ 453 compatible = "maxim,max15303"; 454 reg = <0x14>; 455 }; 456 max15303@15 { /* u6 */ 457 compatible = "maxim,max15303"; 458 reg = <0x15>; 459 }; 460 max15303@16 { /* u10 */ 461 compatible = "maxim,max15303"; 462 reg = <0x16>; 463 }; 464 max15303@17 { /* u9 */ 465 compatible = "maxim,max15303"; 466 reg = <0x17>; 467 }; 468 max15301@18 { /* u63 */ 469 compatible = "maxim,max15301"; 470 reg = <0x18>; 471 }; 472 max15303@1a { /* u49 */ 473 compatible = "maxim,max15303"; 474 reg = <0x1a>; 475 }; 476 max15303@1b { /* u8 */ 477 compatible = "maxim,max15303"; 478 reg = <0x1b>; 479 }; 480 max15303@1d { /* u18 */ 481 compatible = "maxim,max15303"; 482 reg = <0x1d>; 483 }; 484 485 max20751@72 { /* u95 */ 486 compatible = "maxim,max20751"; 487 reg = <0x72>; 488 }; 489 max20751@73 { /* u96 */ 490 compatible = "maxim,max20751"; 491 reg = <0x73>; 492 }; 493 }; 494 /* Bus 3 is not connected */ 495 }; 496}; 497 498&i2c1 { 499 status = "okay"; 500 clock-frequency = <400000>; 501 pinctrl-names = "default", "gpio"; 502 pinctrl-0 = <&pinctrl_i2c1_default>; 503 pinctrl-1 = <&pinctrl_i2c1_gpio>; 504 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; 505 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; 506 507 /* PL i2c via PCA9306 - u45 */ 508 i2c-mux@74 { /* u34 */ 509 compatible = "nxp,pca9548"; 510 #address-cells = <1>; 511 #size-cells = <0>; 512 reg = <0x74>; 513 i2c@0 { 514 #address-cells = <1>; 515 #size-cells = <0>; 516 reg = <0>; 517 /* 518 * IIC_EEPROM 1kB memory which uses 256B blocks 519 * where every block has different address. 520 * 0 - 256B address 0x54 521 * 256B - 512B address 0x55 522 * 512B - 768B address 0x56 523 * 768B - 1024B address 0x57 524 */ 525 eeprom: eeprom@54 { /* u23 */ 526 compatible = "atmel,24c08"; 527 reg = <0x54>; 528 }; 529 }; 530 i2c@1 { 531 #address-cells = <1>; 532 #size-cells = <0>; 533 reg = <1>; 534 si5341: clock-generator@36 { /* SI5341 - u69 */ 535 compatible = "silabs,si5341"; 536 reg = <0x36>; 537 #clock-cells = <2>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 clocks = <&ref48>; 541 clock-names = "xtal"; 542 clock-output-names = "si5341"; 543 544 si5341_0: out@0 { 545 /* refclk0 for PS-GT, used for DP */ 546 reg = <0>; 547 always-on; 548 }; 549 si5341_2: out@2 { 550 /* refclk2 for PS-GT, used for USB3 */ 551 reg = <2>; 552 always-on; 553 }; 554 si5341_3: out@3 { 555 /* refclk3 for PS-GT, used for SATA */ 556 reg = <3>; 557 always-on; 558 }; 559 si5341_6: out@6 { 560 /* refclk6 PL CLK125 */ 561 reg = <6>; 562 always-on; 563 }; 564 si5341_7: out@7 { 565 /* refclk7 PL CLK74 */ 566 reg = <7>; 567 always-on; 568 }; 569 si5341_9: out@9 { 570 /* refclk9 used for PS_REF_CLK 33.3 MHz */ 571 reg = <9>; 572 always-on; 573 }; 574 }; 575 576 }; 577 i2c@2 { 578 #address-cells = <1>; 579 #size-cells = <0>; 580 reg = <2>; 581 si570_1: clock-generator@5d { /* USER SI570 - u42 */ 582 #clock-cells = <0>; 583 compatible = "silabs,si570"; 584 reg = <0x5d>; 585 temperature-stability = <50>; 586 factory-fout = <300000000>; 587 clock-frequency = <300000000>; 588 clock-output-names = "si570_user"; 589 }; 590 }; 591 i2c@3 { 592 #address-cells = <1>; 593 #size-cells = <0>; 594 reg = <3>; 595 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ 596 #clock-cells = <0>; 597 compatible = "silabs,si570"; 598 reg = <0x5d>; 599 temperature-stability = <50>; /* copy from zc702 */ 600 factory-fout = <156250000>; 601 clock-frequency = <148500000>; 602 clock-output-names = "si570_mgt"; 603 }; 604 }; 605 i2c@4 { 606 #address-cells = <1>; 607 #size-cells = <0>; 608 reg = <4>; 609 si5328: clock-generator@69 {/* SI5328 - u20 */ 610 reg = <0x69>; 611 /* 612 * Chip has interrupt present connected to PL 613 * interrupt-parent = <&>; 614 * interrupts = <>; 615 */ 616 #address-cells = <1>; 617 #size-cells = <0>; 618 #clock-cells = <1>; 619 clocks = <&refhdmi>; 620 clock-names = "xtal"; 621 clock-output-names = "si5328"; 622 623 si5328_clk: clk0@0 { 624 reg = <0>; 625 clock-frequency = <27000000>; 626 }; 627 }; 628 }; 629 i2c@5 { 630 #address-cells = <1>; 631 #size-cells = <0>; 632 reg = <5>; /* FAN controller */ 633 temp@4c {/* lm96163 - u128 */ 634 compatible = "national,lm96163"; 635 reg = <0x4c>; 636 }; 637 }; 638 /* 6 - 7 unconnected */ 639 }; 640 641 i2c-mux@75 { 642 compatible = "nxp,pca9548"; /* u135 */ 643 #address-cells = <1>; 644 #size-cells = <0>; 645 reg = <0x75>; 646 647 i2c@0 { 648 #address-cells = <1>; 649 #size-cells = <0>; 650 reg = <0>; 651 /* HPC0_IIC */ 652 }; 653 i2c@1 { 654 #address-cells = <1>; 655 #size-cells = <0>; 656 reg = <1>; 657 /* HPC1_IIC */ 658 }; 659 i2c@2 { 660 #address-cells = <1>; 661 #size-cells = <0>; 662 reg = <2>; 663 /* SYSMON */ 664 }; 665 i2c@3 { 666 #address-cells = <1>; 667 #size-cells = <0>; 668 reg = <3>; 669 /* DDR4 SODIMM */ 670 }; 671 i2c@4 { 672 #address-cells = <1>; 673 #size-cells = <0>; 674 reg = <4>; 675 /* SEP 3 */ 676 }; 677 i2c@5 { 678 #address-cells = <1>; 679 #size-cells = <0>; 680 reg = <5>; 681 /* SEP 2 */ 682 }; 683 i2c@6 { 684 #address-cells = <1>; 685 #size-cells = <0>; 686 reg = <6>; 687 /* SEP 1 */ 688 }; 689 i2c@7 { 690 #address-cells = <1>; 691 #size-cells = <0>; 692 reg = <7>; 693 /* SEP 0 */ 694 }; 695 }; 696}; 697 698&pinctrl0 { 699 status = "okay"; 700 pinctrl_i2c0_default: i2c0-default { 701 mux { 702 groups = "i2c0_3_grp"; 703 function = "i2c0"; 704 }; 705 706 conf { 707 groups = "i2c0_3_grp"; 708 bias-pull-up; 709 slew-rate = <SLEW_RATE_SLOW>; 710 power-source = <IO_STANDARD_LVCMOS18>; 711 }; 712 }; 713 714 pinctrl_i2c0_gpio: i2c0-gpio { 715 mux { 716 groups = "gpio0_14_grp", "gpio0_15_grp"; 717 function = "gpio0"; 718 }; 719 720 conf { 721 groups = "gpio0_14_grp", "gpio0_15_grp"; 722 slew-rate = <SLEW_RATE_SLOW>; 723 power-source = <IO_STANDARD_LVCMOS18>; 724 }; 725 }; 726 727 pinctrl_i2c1_default: i2c1-default { 728 mux { 729 groups = "i2c1_4_grp"; 730 function = "i2c1"; 731 }; 732 733 conf { 734 groups = "i2c1_4_grp"; 735 bias-pull-up; 736 slew-rate = <SLEW_RATE_SLOW>; 737 power-source = <IO_STANDARD_LVCMOS18>; 738 }; 739 }; 740 741 pinctrl_i2c1_gpio: i2c1-gpio { 742 mux { 743 groups = "gpio0_16_grp", "gpio0_17_grp"; 744 function = "gpio0"; 745 }; 746 747 conf { 748 groups = "gpio0_16_grp", "gpio0_17_grp"; 749 slew-rate = <SLEW_RATE_SLOW>; 750 power-source = <IO_STANDARD_LVCMOS18>; 751 }; 752 }; 753 754 pinctrl_uart0_default: uart0-default { 755 mux { 756 groups = "uart0_4_grp"; 757 function = "uart0"; 758 }; 759 760 conf { 761 groups = "uart0_4_grp"; 762 slew-rate = <SLEW_RATE_SLOW>; 763 power-source = <IO_STANDARD_LVCMOS18>; 764 }; 765 766 conf-rx { 767 pins = "MIO18"; 768 bias-high-impedance; 769 }; 770 771 conf-tx { 772 pins = "MIO19"; 773 bias-disable; 774 }; 775 }; 776 777 pinctrl_uart1_default: uart1-default { 778 mux { 779 groups = "uart1_5_grp"; 780 function = "uart1"; 781 }; 782 783 conf { 784 groups = "uart1_5_grp"; 785 slew-rate = <SLEW_RATE_SLOW>; 786 power-source = <IO_STANDARD_LVCMOS18>; 787 }; 788 789 conf-rx { 790 pins = "MIO21"; 791 bias-high-impedance; 792 }; 793 794 conf-tx { 795 pins = "MIO20"; 796 bias-disable; 797 }; 798 }; 799 800 pinctrl_usb0_default: usb0-default { 801 mux { 802 groups = "usb0_0_grp"; 803 function = "usb0"; 804 }; 805 806 conf { 807 groups = "usb0_0_grp"; 808 slew-rate = <SLEW_RATE_SLOW>; 809 power-source = <IO_STANDARD_LVCMOS18>; 810 }; 811 812 conf-rx { 813 pins = "MIO52", "MIO53", "MIO55"; 814 bias-high-impedance; 815 }; 816 817 conf-tx { 818 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", 819 "MIO60", "MIO61", "MIO62", "MIO63"; 820 bias-disable; 821 }; 822 }; 823 824 pinctrl_gem3_default: gem3-default { 825 mux { 826 function = "ethernet3"; 827 groups = "ethernet3_0_grp"; 828 }; 829 830 conf { 831 groups = "ethernet3_0_grp"; 832 slew-rate = <SLEW_RATE_SLOW>; 833 power-source = <IO_STANDARD_LVCMOS18>; 834 }; 835 836 conf-rx { 837 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", 838 "MIO75"; 839 bias-high-impedance; 840 low-power-disable; 841 }; 842 843 conf-tx { 844 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", 845 "MIO69"; 846 bias-disable; 847 low-power-enable; 848 }; 849 850 mux-mdio { 851 function = "mdio3"; 852 groups = "mdio3_0_grp"; 853 }; 854 855 conf-mdio { 856 groups = "mdio3_0_grp"; 857 slew-rate = <SLEW_RATE_SLOW>; 858 power-source = <IO_STANDARD_LVCMOS18>; 859 bias-disable; 860 }; 861 }; 862 863 pinctrl_can1_default: can1-default { 864 mux { 865 function = "can1"; 866 groups = "can1_6_grp"; 867 }; 868 869 conf { 870 groups = "can1_6_grp"; 871 slew-rate = <SLEW_RATE_SLOW>; 872 power-source = <IO_STANDARD_LVCMOS18>; 873 }; 874 875 conf-rx { 876 pins = "MIO25"; 877 bias-high-impedance; 878 }; 879 880 conf-tx { 881 pins = "MIO24"; 882 bias-disable; 883 }; 884 }; 885 886 pinctrl_sdhci1_default: sdhci1-default { 887 mux { 888 groups = "sdio1_0_grp"; 889 function = "sdio1"; 890 }; 891 892 conf { 893 groups = "sdio1_0_grp"; 894 slew-rate = <SLEW_RATE_SLOW>; 895 power-source = <IO_STANDARD_LVCMOS18>; 896 bias-disable; 897 }; 898 899 mux-cd { 900 groups = "sdio1_cd_0_grp"; 901 function = "sdio1_cd"; 902 }; 903 904 conf-cd { 905 groups = "sdio1_cd_0_grp"; 906 bias-high-impedance; 907 bias-pull-up; 908 slew-rate = <SLEW_RATE_SLOW>; 909 power-source = <IO_STANDARD_LVCMOS18>; 910 }; 911 912 mux-wp { 913 groups = "sdio1_wp_0_grp"; 914 function = "sdio1_wp"; 915 }; 916 917 conf-wp { 918 groups = "sdio1_wp_0_grp"; 919 bias-high-impedance; 920 bias-pull-up; 921 slew-rate = <SLEW_RATE_SLOW>; 922 power-source = <IO_STANDARD_LVCMOS18>; 923 }; 924 }; 925 926 pinctrl_gpio_default: gpio-default { 927 mux { 928 function = "gpio0"; 929 groups = "gpio0_22_grp", "gpio0_23_grp"; 930 }; 931 932 conf { 933 groups = "gpio0_22_grp", "gpio0_23_grp"; 934 slew-rate = <SLEW_RATE_SLOW>; 935 power-source = <IO_STANDARD_LVCMOS18>; 936 }; 937 938 mux-msp { 939 function = "gpio0"; 940 groups = "gpio0_13_grp", "gpio0_38_grp"; 941 }; 942 943 conf-msp { 944 groups = "gpio0_13_grp", "gpio0_38_grp"; 945 slew-rate = <SLEW_RATE_SLOW>; 946 power-source = <IO_STANDARD_LVCMOS18>; 947 }; 948 949 conf-pull-up { 950 pins = "MIO22"; 951 bias-pull-up; 952 }; 953 954 conf-pull-none { 955 pins = "MIO13", "MIO23", "MIO38"; 956 bias-disable; 957 }; 958 }; 959}; 960 961&psgtr { 962 status = "okay"; 963 /* nc, sata, usb3, dp */ 964 clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; 965 clock-names = "ref1", "ref2", "ref3"; 966}; 967 968&qspi { 969 status = "okay"; 970 is-dual = <1>; 971 flash@0 { 972 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ 973 #address-cells = <1>; 974 #size-cells = <1>; 975 reg = <0x0>; 976 spi-tx-bus-width = <1>; 977 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ 978 spi-max-frequency = <108000000>; /* Based on DC1 spec */ 979 partition@0 { /* for testing purpose */ 980 label = "qspi-fsbl-uboot"; 981 reg = <0x0 0x100000>; 982 }; 983 partition@100000 { /* for testing purpose */ 984 label = "qspi-linux"; 985 reg = <0x100000 0x500000>; 986 }; 987 partition@600000 { /* for testing purpose */ 988 label = "qspi-device-tree"; 989 reg = <0x600000 0x20000>; 990 }; 991 partition@620000 { /* for testing purpose */ 992 label = "qspi-rootfs"; 993 reg = <0x620000 0x5E0000>; 994 }; 995 }; 996}; 997 998&rtc { 999 status = "okay"; 1000}; 1001 1002&sata { 1003 status = "okay"; 1004 /* SATA OOB timing settings */ 1005 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 1006 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 1007 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 1008 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 1009 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 1010 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 1011 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 1012 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 1013 phy-names = "sata-phy"; 1014 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; 1015}; 1016 1017/* SD1 with level shifter */ 1018&sdhci1 { 1019 status = "okay"; 1020 /* 1021 * This property should be removed for supporting UHS mode 1022 */ 1023 no-1-8-v; 1024 pinctrl-names = "default"; 1025 pinctrl-0 = <&pinctrl_sdhci1_default>; 1026 xlnx,mio-bank = <1>; 1027}; 1028 1029&uart0 { 1030 status = "okay"; 1031 pinctrl-names = "default"; 1032 pinctrl-0 = <&pinctrl_uart0_default>; 1033}; 1034 1035&uart1 { 1036 status = "okay"; 1037 pinctrl-names = "default"; 1038 pinctrl-0 = <&pinctrl_uart1_default>; 1039}; 1040 1041/* ULPI SMSC USB3320 */ 1042&usb0 { 1043 status = "okay"; 1044 pinctrl-names = "default"; 1045 pinctrl-0 = <&pinctrl_usb0_default>; 1046}; 1047 1048&dwc3_0 { 1049 status = "okay"; 1050 dr_mode = "host"; 1051 snps,usb3_lpm_capable; 1052 phy-names = "usb3-phy"; 1053 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; 1054}; 1055 1056&watchdog0 { 1057 status = "okay"; 1058}; 1059