1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
4  *
5  * Authors: Nick.Spence@freescale.com
6  *          Wilson.Lo@freescale.com
7  *          scottwood@freescale.com
8  */
9 
10 #include <common.h>
11 #include <init.h>
12 #include <mpc83xx.h>
13 #include <spd_sdram.h>
14 #include <asm/global_data.h>
15 #include <linux/delay.h>
16 
17 #include <asm/bitops.h>
18 #include <asm/io.h>
19 
20 #include <asm/processor.h>
21 
22 DECLARE_GLOBAL_DATA_PTR;
23 
24 #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
resume_from_sleep(void)25 static void resume_from_sleep(void)
26 {
27 	u32 magic = *(u32 *)0;
28 
29 	typedef void (*func_t)(void);
30 	func_t resume = *(func_t *)4;
31 
32 	if (magic == 0xf5153ae5)
33 		resume();
34 
35 	gd->flags &= ~GD_FLG_SILENT;
36 	puts("\nResume from sleep failed: bad magic word\n");
37 }
38 #endif
39 
40 /* Fixed sdram init -- doesn't use serial presence detect.
41  *
42  * This is useful for faster booting in configs where the RAM is unlikely
43  * to be changed, or for things like NAND booting where space is tight.
44  */
fixed_sdram(void)45 static long fixed_sdram(void)
46 {
47 	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
48 
49 #ifndef CONFIG_SYS_RAMBOOT
50 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
51 	u32 msize_log2 = __ilog2(msize);
52 
53 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
54 	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
55 	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
56 
57 	/*
58 	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
59 	 * or the DDR2 controller may fail to initialize correctly.
60 	 */
61 	__udelay(50000);
62 
63 #if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
64 #warning Chip select bounds is only configurable in 16MB increments
65 #endif
66 	im->ddr.csbnds[0].csbnds =
67 		((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
68 		(((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
69 			CSBNDS_EA);
70 	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
71 
72 	/* Currently we use only one CS, so disable the other bank. */
73 	im->ddr.cs_config[1] = 0;
74 
75 	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
76 	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
77 	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
78 	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
79 	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
80 
81 #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
82 	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
83 		im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI;
84 	else
85 #endif
86 		im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG;
87 
88 	im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2;
89 	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
90 	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2;
91 
92 	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
93 	sync();
94 
95 	/* enable DDR controller */
96 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
97 #endif
98 
99 	return msize;
100 }
101 
dram_init(void)102 int dram_init(void)
103 {
104 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
105 	volatile fsl_lbc_t *lbc = &im->im_lbc;
106 	u32 msize;
107 
108 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
109 		return -ENXIO;
110 
111 	/* DDR SDRAM - Main SODIMM */
112 	msize = fixed_sdram();
113 
114 	/* Local Bus setup lbcr and mrtpr */
115 	lbc->lbcr = (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF);
116 	/* LB refresh timer prescal, 266MHz/32 */
117 	lbc->mrtpr = 0x20000000;
118 	sync();
119 
120 #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
121 	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
122 		resume_from_sleep();
123 #endif
124 
125 	/* return total bus SDRAM size(bytes)  -- DDR */
126 	gd->ram_size = msize;
127 
128 	return 0;
129 }
130