1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Freescale i.MX28 APBH Register Definitions 4 * 5 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 6 * on behalf of DENX Software Engineering GmbH 7 * 8 * Based on code from LTIB: 9 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. 10 * Copyright 2020 NXP 11 */ 12 13 #ifndef __REGS_APBH_H__ 14 #define __REGS_APBH_H__ 15 16 #include <asm/mach-imx/regs-common.h> 17 18 #ifndef __ASSEMBLY__ 19 20 #if defined(CONFIG_MX23) 21 struct mxs_apbh_regs { 22 mxs_reg_32(hw_apbh_ctrl0) 23 mxs_reg_32(hw_apbh_ctrl1) 24 mxs_reg_32(hw_apbh_ctrl2) 25 mxs_reg_32(hw_apbh_channel_ctrl) 26 27 union { 28 struct { 29 mxs_reg_32(hw_apbh_ch_curcmdar) 30 mxs_reg_32(hw_apbh_ch_nxtcmdar) 31 mxs_reg_32(hw_apbh_ch_cmd) 32 mxs_reg_32(hw_apbh_ch_bar) 33 mxs_reg_32(hw_apbh_ch_sema) 34 mxs_reg_32(hw_apbh_ch_debug1) 35 mxs_reg_32(hw_apbh_ch_debug2) 36 } ch[8]; 37 struct { 38 mxs_reg_32(hw_apbh_ch0_curcmdar) 39 mxs_reg_32(hw_apbh_ch0_nxtcmdar) 40 mxs_reg_32(hw_apbh_ch0_cmd) 41 mxs_reg_32(hw_apbh_ch0_bar) 42 mxs_reg_32(hw_apbh_ch0_sema) 43 mxs_reg_32(hw_apbh_ch0_debug1) 44 mxs_reg_32(hw_apbh_ch0_debug2) 45 mxs_reg_32(hw_apbh_ch1_curcmdar) 46 mxs_reg_32(hw_apbh_ch1_nxtcmdar) 47 mxs_reg_32(hw_apbh_ch1_cmd) 48 mxs_reg_32(hw_apbh_ch1_bar) 49 mxs_reg_32(hw_apbh_ch1_sema) 50 mxs_reg_32(hw_apbh_ch1_debug1) 51 mxs_reg_32(hw_apbh_ch1_debug2) 52 mxs_reg_32(hw_apbh_ch2_curcmdar) 53 mxs_reg_32(hw_apbh_ch2_nxtcmdar) 54 mxs_reg_32(hw_apbh_ch2_cmd) 55 mxs_reg_32(hw_apbh_ch2_bar) 56 mxs_reg_32(hw_apbh_ch2_sema) 57 mxs_reg_32(hw_apbh_ch2_debug1) 58 mxs_reg_32(hw_apbh_ch2_debug2) 59 mxs_reg_32(hw_apbh_ch3_curcmdar) 60 mxs_reg_32(hw_apbh_ch3_nxtcmdar) 61 mxs_reg_32(hw_apbh_ch3_cmd) 62 mxs_reg_32(hw_apbh_ch3_bar) 63 mxs_reg_32(hw_apbh_ch3_sema) 64 mxs_reg_32(hw_apbh_ch3_debug1) 65 mxs_reg_32(hw_apbh_ch3_debug2) 66 mxs_reg_32(hw_apbh_ch4_curcmdar) 67 mxs_reg_32(hw_apbh_ch4_nxtcmdar) 68 mxs_reg_32(hw_apbh_ch4_cmd) 69 mxs_reg_32(hw_apbh_ch4_bar) 70 mxs_reg_32(hw_apbh_ch4_sema) 71 mxs_reg_32(hw_apbh_ch4_debug1) 72 mxs_reg_32(hw_apbh_ch4_debug2) 73 mxs_reg_32(hw_apbh_ch5_curcmdar) 74 mxs_reg_32(hw_apbh_ch5_nxtcmdar) 75 mxs_reg_32(hw_apbh_ch5_cmd) 76 mxs_reg_32(hw_apbh_ch5_bar) 77 mxs_reg_32(hw_apbh_ch5_sema) 78 mxs_reg_32(hw_apbh_ch5_debug1) 79 mxs_reg_32(hw_apbh_ch5_debug2) 80 mxs_reg_32(hw_apbh_ch6_curcmdar) 81 mxs_reg_32(hw_apbh_ch6_nxtcmdar) 82 mxs_reg_32(hw_apbh_ch6_cmd) 83 mxs_reg_32(hw_apbh_ch6_bar) 84 mxs_reg_32(hw_apbh_ch6_sema) 85 mxs_reg_32(hw_apbh_ch6_debug1) 86 mxs_reg_32(hw_apbh_ch6_debug2) 87 mxs_reg_32(hw_apbh_ch7_curcmdar) 88 mxs_reg_32(hw_apbh_ch7_nxtcmdar) 89 mxs_reg_32(hw_apbh_ch7_cmd) 90 mxs_reg_32(hw_apbh_ch7_bar) 91 mxs_reg_32(hw_apbh_ch7_sema) 92 mxs_reg_32(hw_apbh_ch7_debug1) 93 mxs_reg_32(hw_apbh_ch7_debug2) 94 }; 95 }; 96 mxs_reg_32(hw_apbh_version) 97 }; 98 99 #else 100 struct mxs_apbh_regs { 101 mxs_reg_32(hw_apbh_ctrl0) 102 mxs_reg_32(hw_apbh_ctrl1) 103 mxs_reg_32(hw_apbh_ctrl2) 104 mxs_reg_32(hw_apbh_channel_ctrl) 105 mxs_reg_32(hw_apbh_devsel) 106 mxs_reg_32(hw_apbh_dma_burst_size) 107 mxs_reg_32(hw_apbh_debug) 108 109 uint32_t reserved[36]; 110 111 union { 112 struct { 113 mxs_reg_32(hw_apbh_ch_curcmdar) 114 mxs_reg_32(hw_apbh_ch_nxtcmdar) 115 mxs_reg_32(hw_apbh_ch_cmd) 116 mxs_reg_32(hw_apbh_ch_bar) 117 mxs_reg_32(hw_apbh_ch_sema) 118 mxs_reg_32(hw_apbh_ch_debug1) 119 mxs_reg_32(hw_apbh_ch_debug2) 120 } ch[16]; 121 struct { 122 mxs_reg_32(hw_apbh_ch0_curcmdar) 123 mxs_reg_32(hw_apbh_ch0_nxtcmdar) 124 mxs_reg_32(hw_apbh_ch0_cmd) 125 mxs_reg_32(hw_apbh_ch0_bar) 126 mxs_reg_32(hw_apbh_ch0_sema) 127 mxs_reg_32(hw_apbh_ch0_debug1) 128 mxs_reg_32(hw_apbh_ch0_debug2) 129 mxs_reg_32(hw_apbh_ch1_curcmdar) 130 mxs_reg_32(hw_apbh_ch1_nxtcmdar) 131 mxs_reg_32(hw_apbh_ch1_cmd) 132 mxs_reg_32(hw_apbh_ch1_bar) 133 mxs_reg_32(hw_apbh_ch1_sema) 134 mxs_reg_32(hw_apbh_ch1_debug1) 135 mxs_reg_32(hw_apbh_ch1_debug2) 136 mxs_reg_32(hw_apbh_ch2_curcmdar) 137 mxs_reg_32(hw_apbh_ch2_nxtcmdar) 138 mxs_reg_32(hw_apbh_ch2_cmd) 139 mxs_reg_32(hw_apbh_ch2_bar) 140 mxs_reg_32(hw_apbh_ch2_sema) 141 mxs_reg_32(hw_apbh_ch2_debug1) 142 mxs_reg_32(hw_apbh_ch2_debug2) 143 mxs_reg_32(hw_apbh_ch3_curcmdar) 144 mxs_reg_32(hw_apbh_ch3_nxtcmdar) 145 mxs_reg_32(hw_apbh_ch3_cmd) 146 mxs_reg_32(hw_apbh_ch3_bar) 147 mxs_reg_32(hw_apbh_ch3_sema) 148 mxs_reg_32(hw_apbh_ch3_debug1) 149 mxs_reg_32(hw_apbh_ch3_debug2) 150 mxs_reg_32(hw_apbh_ch4_curcmdar) 151 mxs_reg_32(hw_apbh_ch4_nxtcmdar) 152 mxs_reg_32(hw_apbh_ch4_cmd) 153 mxs_reg_32(hw_apbh_ch4_bar) 154 mxs_reg_32(hw_apbh_ch4_sema) 155 mxs_reg_32(hw_apbh_ch4_debug1) 156 mxs_reg_32(hw_apbh_ch4_debug2) 157 mxs_reg_32(hw_apbh_ch5_curcmdar) 158 mxs_reg_32(hw_apbh_ch5_nxtcmdar) 159 mxs_reg_32(hw_apbh_ch5_cmd) 160 mxs_reg_32(hw_apbh_ch5_bar) 161 mxs_reg_32(hw_apbh_ch5_sema) 162 mxs_reg_32(hw_apbh_ch5_debug1) 163 mxs_reg_32(hw_apbh_ch5_debug2) 164 mxs_reg_32(hw_apbh_ch6_curcmdar) 165 mxs_reg_32(hw_apbh_ch6_nxtcmdar) 166 mxs_reg_32(hw_apbh_ch6_cmd) 167 mxs_reg_32(hw_apbh_ch6_bar) 168 mxs_reg_32(hw_apbh_ch6_sema) 169 mxs_reg_32(hw_apbh_ch6_debug1) 170 mxs_reg_32(hw_apbh_ch6_debug2) 171 mxs_reg_32(hw_apbh_ch7_curcmdar) 172 mxs_reg_32(hw_apbh_ch7_nxtcmdar) 173 mxs_reg_32(hw_apbh_ch7_cmd) 174 mxs_reg_32(hw_apbh_ch7_bar) 175 mxs_reg_32(hw_apbh_ch7_sema) 176 mxs_reg_32(hw_apbh_ch7_debug1) 177 mxs_reg_32(hw_apbh_ch7_debug2) 178 mxs_reg_32(hw_apbh_ch8_curcmdar) 179 mxs_reg_32(hw_apbh_ch8_nxtcmdar) 180 mxs_reg_32(hw_apbh_ch8_cmd) 181 mxs_reg_32(hw_apbh_ch8_bar) 182 mxs_reg_32(hw_apbh_ch8_sema) 183 mxs_reg_32(hw_apbh_ch8_debug1) 184 mxs_reg_32(hw_apbh_ch8_debug2) 185 mxs_reg_32(hw_apbh_ch9_curcmdar) 186 mxs_reg_32(hw_apbh_ch9_nxtcmdar) 187 mxs_reg_32(hw_apbh_ch9_cmd) 188 mxs_reg_32(hw_apbh_ch9_bar) 189 mxs_reg_32(hw_apbh_ch9_sema) 190 mxs_reg_32(hw_apbh_ch9_debug1) 191 mxs_reg_32(hw_apbh_ch9_debug2) 192 mxs_reg_32(hw_apbh_ch10_curcmdar) 193 mxs_reg_32(hw_apbh_ch10_nxtcmdar) 194 mxs_reg_32(hw_apbh_ch10_cmd) 195 mxs_reg_32(hw_apbh_ch10_bar) 196 mxs_reg_32(hw_apbh_ch10_sema) 197 mxs_reg_32(hw_apbh_ch10_debug1) 198 mxs_reg_32(hw_apbh_ch10_debug2) 199 mxs_reg_32(hw_apbh_ch11_curcmdar) 200 mxs_reg_32(hw_apbh_ch11_nxtcmdar) 201 mxs_reg_32(hw_apbh_ch11_cmd) 202 mxs_reg_32(hw_apbh_ch11_bar) 203 mxs_reg_32(hw_apbh_ch11_sema) 204 mxs_reg_32(hw_apbh_ch11_debug1) 205 mxs_reg_32(hw_apbh_ch11_debug2) 206 mxs_reg_32(hw_apbh_ch12_curcmdar) 207 mxs_reg_32(hw_apbh_ch12_nxtcmdar) 208 mxs_reg_32(hw_apbh_ch12_cmd) 209 mxs_reg_32(hw_apbh_ch12_bar) 210 mxs_reg_32(hw_apbh_ch12_sema) 211 mxs_reg_32(hw_apbh_ch12_debug1) 212 mxs_reg_32(hw_apbh_ch12_debug2) 213 mxs_reg_32(hw_apbh_ch13_curcmdar) 214 mxs_reg_32(hw_apbh_ch13_nxtcmdar) 215 mxs_reg_32(hw_apbh_ch13_cmd) 216 mxs_reg_32(hw_apbh_ch13_bar) 217 mxs_reg_32(hw_apbh_ch13_sema) 218 mxs_reg_32(hw_apbh_ch13_debug1) 219 mxs_reg_32(hw_apbh_ch13_debug2) 220 mxs_reg_32(hw_apbh_ch14_curcmdar) 221 mxs_reg_32(hw_apbh_ch14_nxtcmdar) 222 mxs_reg_32(hw_apbh_ch14_cmd) 223 mxs_reg_32(hw_apbh_ch14_bar) 224 mxs_reg_32(hw_apbh_ch14_sema) 225 mxs_reg_32(hw_apbh_ch14_debug1) 226 mxs_reg_32(hw_apbh_ch14_debug2) 227 mxs_reg_32(hw_apbh_ch15_curcmdar) 228 mxs_reg_32(hw_apbh_ch15_nxtcmdar) 229 mxs_reg_32(hw_apbh_ch15_cmd) 230 mxs_reg_32(hw_apbh_ch15_bar) 231 mxs_reg_32(hw_apbh_ch15_sema) 232 mxs_reg_32(hw_apbh_ch15_debug1) 233 mxs_reg_32(hw_apbh_ch15_debug2) 234 }; 235 }; 236 mxs_reg_32(hw_apbh_version) 237 }; 238 #endif 239 240 #endif 241 242 #define APBH_CTRL0_SFTRST (1 << 31) 243 #define APBH_CTRL0_CLKGATE (1 << 30) 244 #define APBH_CTRL0_AHB_BURST8_EN (1 << 29) 245 #define APBH_CTRL0_APB_BURST_EN (1 << 28) 246 #if defined(CONFIG_MX23) 247 #define APBH_CTRL0_RSVD0_MASK (0xf << 24) 248 #define APBH_CTRL0_RSVD0_OFFSET 24 249 #define APBH_CTRL0_RESET_CHANNEL_MASK (0xff << 16) 250 #define APBH_CTRL0_RESET_CHANNEL_OFFSET 16 251 #define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xff << 8) 252 #define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 8 253 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x02 254 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x04 255 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x10 256 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x20 257 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x40 258 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x80 259 #elif defined(CONFIG_MX28) 260 #define APBH_CTRL0_RSVD0_MASK (0xfff << 16) 261 #define APBH_CTRL0_RSVD0_OFFSET 16 262 #define APBH_CTRL0_CLKGATE_CHANNEL_MASK 0xffff 263 #define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0 264 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x0001 265 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x0002 266 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP2 0x0004 267 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP3 0x0008 268 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0010 269 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0020 270 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0040 271 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0080 272 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0100 273 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0200 274 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0400 275 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800 276 #define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000 277 #define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000 278 #elif (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)) 279 #define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0 280 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001 281 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002 282 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0004 283 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0008 284 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0010 285 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0020 286 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0040 287 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0080 288 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP 0x0100 289 #endif 290 291 #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN (1 << 31) 292 #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN (1 << 30) 293 #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN (1 << 29) 294 #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN (1 << 28) 295 #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN (1 << 27) 296 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN (1 << 26) 297 #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN (1 << 25) 298 #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN (1 << 24) 299 #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN (1 << 23) 300 #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN (1 << 22) 301 #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN (1 << 21) 302 #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN (1 << 20) 303 #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN (1 << 19) 304 #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN (1 << 18) 305 #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN (1 << 17) 306 #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN (1 << 16) 307 #define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET 16 308 #define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_MASK (0xffff << 16) 309 #define APBH_CTRL1_CH15_CMDCMPLT_IRQ (1 << 15) 310 #define APBH_CTRL1_CH14_CMDCMPLT_IRQ (1 << 14) 311 #define APBH_CTRL1_CH13_CMDCMPLT_IRQ (1 << 13) 312 #define APBH_CTRL1_CH12_CMDCMPLT_IRQ (1 << 12) 313 #define APBH_CTRL1_CH11_CMDCMPLT_IRQ (1 << 11) 314 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ (1 << 10) 315 #define APBH_CTRL1_CH9_CMDCMPLT_IRQ (1 << 9) 316 #define APBH_CTRL1_CH8_CMDCMPLT_IRQ (1 << 8) 317 #define APBH_CTRL1_CH7_CMDCMPLT_IRQ (1 << 7) 318 #define APBH_CTRL1_CH6_CMDCMPLT_IRQ (1 << 6) 319 #define APBH_CTRL1_CH5_CMDCMPLT_IRQ (1 << 5) 320 #define APBH_CTRL1_CH4_CMDCMPLT_IRQ (1 << 4) 321 #define APBH_CTRL1_CH3_CMDCMPLT_IRQ (1 << 3) 322 #define APBH_CTRL1_CH2_CMDCMPLT_IRQ (1 << 2) 323 #define APBH_CTRL1_CH1_CMDCMPLT_IRQ (1 << 1) 324 #define APBH_CTRL1_CH0_CMDCMPLT_IRQ (1 << 0) 325 326 #define APBH_CTRL2_CH15_ERROR_STATUS (1 << 31) 327 #define APBH_CTRL2_CH14_ERROR_STATUS (1 << 30) 328 #define APBH_CTRL2_CH13_ERROR_STATUS (1 << 29) 329 #define APBH_CTRL2_CH12_ERROR_STATUS (1 << 28) 330 #define APBH_CTRL2_CH11_ERROR_STATUS (1 << 27) 331 #define APBH_CTRL2_CH10_ERROR_STATUS (1 << 26) 332 #define APBH_CTRL2_CH9_ERROR_STATUS (1 << 25) 333 #define APBH_CTRL2_CH8_ERROR_STATUS (1 << 24) 334 #define APBH_CTRL2_CH7_ERROR_STATUS (1 << 23) 335 #define APBH_CTRL2_CH6_ERROR_STATUS (1 << 22) 336 #define APBH_CTRL2_CH5_ERROR_STATUS (1 << 21) 337 #define APBH_CTRL2_CH4_ERROR_STATUS (1 << 20) 338 #define APBH_CTRL2_CH3_ERROR_STATUS (1 << 19) 339 #define APBH_CTRL2_CH2_ERROR_STATUS (1 << 18) 340 #define APBH_CTRL2_CH1_ERROR_STATUS (1 << 17) 341 #define APBH_CTRL2_CH0_ERROR_STATUS (1 << 16) 342 #define APBH_CTRL2_CH15_ERROR_IRQ (1 << 15) 343 #define APBH_CTRL2_CH14_ERROR_IRQ (1 << 14) 344 #define APBH_CTRL2_CH13_ERROR_IRQ (1 << 13) 345 #define APBH_CTRL2_CH12_ERROR_IRQ (1 << 12) 346 #define APBH_CTRL2_CH11_ERROR_IRQ (1 << 11) 347 #define APBH_CTRL2_CH10_ERROR_IRQ (1 << 10) 348 #define APBH_CTRL2_CH9_ERROR_IRQ (1 << 9) 349 #define APBH_CTRL2_CH8_ERROR_IRQ (1 << 8) 350 #define APBH_CTRL2_CH7_ERROR_IRQ (1 << 7) 351 #define APBH_CTRL2_CH6_ERROR_IRQ (1 << 6) 352 #define APBH_CTRL2_CH5_ERROR_IRQ (1 << 5) 353 #define APBH_CTRL2_CH4_ERROR_IRQ (1 << 4) 354 #define APBH_CTRL2_CH3_ERROR_IRQ (1 << 3) 355 #define APBH_CTRL2_CH2_ERROR_IRQ (1 << 2) 356 #define APBH_CTRL2_CH1_ERROR_IRQ (1 << 1) 357 #define APBH_CTRL2_CH0_ERROR_IRQ (1 << 0) 358 359 #if defined(CONFIG_MX28) 360 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xffff << 16) 361 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0 (0x0001 << 16) 362 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP1 (0x0002 << 16) 363 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP2 (0x0004 << 16) 364 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP3 (0x0008 << 16) 365 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND0 (0x0010 << 16) 366 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND1 (0x0020 << 16) 367 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND2 (0x0040 << 16) 368 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND3 (0x0080 << 16) 369 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND4 (0x0100 << 16) 370 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND5 (0x0200 << 16) 371 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND6 (0x0400 << 16) 372 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND7 (0x0800 << 16) 373 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_HSADC (0x1000 << 16) 374 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_LCDIF (0x2000 << 16) 375 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK 0xffff 376 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET 0 377 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP0 0x0001 378 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP1 0x0002 379 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP2 0x0004 380 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP3 0x0008 381 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND0 0x0010 382 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND1 0x0020 383 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND2 0x0040 384 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND3 0x0080 385 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND4 0x0100 386 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND5 0x0200 387 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND6 0x0400 388 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND7 0x0800 389 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_HSADC 0x1000 390 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000 391 #endif 392 393 /* Not on i.MX23 */ 394 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16 395 396 #if defined(CONFIG_MX23) 397 #define APBH_DEVSEL_CH7_MASK (0xf << 28) 398 #define APBH_DEVSEL_CH7_OFFSET 28 399 #define APBH_DEVSEL_CH6_MASK (0xf << 24) 400 #define APBH_DEVSEL_CH6_OFFSET 24 401 #define APBH_DEVSEL_CH5_MASK (0xf << 20) 402 #define APBH_DEVSEL_CH5_OFFSET 20 403 #define APBH_DEVSEL_CH4_MASK (0xf << 16) 404 #define APBH_DEVSEL_CH4_OFFSET 16 405 #define APBH_DEVSEL_CH3_MASK (0xf << 12) 406 #define APBH_DEVSEL_CH3_OFFSET 12 407 #define APBH_DEVSEL_CH2_MASK (0xf << 8) 408 #define APBH_DEVSEL_CH2_OFFSET 8 409 #define APBH_DEVSEL_CH1_MASK (0xf << 4) 410 #define APBH_DEVSEL_CH1_OFFSET 4 411 #define APBH_DEVSEL_CH0_MASK (0xf << 0) 412 #define APBH_DEVSEL_CH0_OFFSET 0 413 #elif defined(CONFIG_MX28) 414 #define APBH_DEVSEL_CH15_MASK (0x3 << 30) 415 #define APBH_DEVSEL_CH15_OFFSET 30 416 #define APBH_DEVSEL_CH14_MASK (0x3 << 28) 417 #define APBH_DEVSEL_CH14_OFFSET 28 418 #define APBH_DEVSEL_CH13_MASK (0x3 << 26) 419 #define APBH_DEVSEL_CH13_OFFSET 26 420 #define APBH_DEVSEL_CH12_MASK (0x3 << 24) 421 #define APBH_DEVSEL_CH12_OFFSET 24 422 #define APBH_DEVSEL_CH11_MASK (0x3 << 22) 423 #define APBH_DEVSEL_CH11_OFFSET 22 424 #define APBH_DEVSEL_CH10_MASK (0x3 << 20) 425 #define APBH_DEVSEL_CH10_OFFSET 20 426 #define APBH_DEVSEL_CH9_MASK (0x3 << 18) 427 #define APBH_DEVSEL_CH9_OFFSET 18 428 #define APBH_DEVSEL_CH8_MASK (0x3 << 16) 429 #define APBH_DEVSEL_CH8_OFFSET 16 430 #define APBH_DEVSEL_CH7_MASK (0x3 << 14) 431 #define APBH_DEVSEL_CH7_OFFSET 14 432 #define APBH_DEVSEL_CH6_MASK (0x3 << 12) 433 #define APBH_DEVSEL_CH6_OFFSET 12 434 #define APBH_DEVSEL_CH5_MASK (0x3 << 10) 435 #define APBH_DEVSEL_CH5_OFFSET 10 436 #define APBH_DEVSEL_CH4_MASK (0x3 << 8) 437 #define APBH_DEVSEL_CH4_OFFSET 8 438 #define APBH_DEVSEL_CH3_MASK (0x3 << 6) 439 #define APBH_DEVSEL_CH3_OFFSET 6 440 #define APBH_DEVSEL_CH2_MASK (0x3 << 4) 441 #define APBH_DEVSEL_CH2_OFFSET 4 442 #define APBH_DEVSEL_CH1_MASK (0x3 << 2) 443 #define APBH_DEVSEL_CH1_OFFSET 2 444 #define APBH_DEVSEL_CH0_MASK (0x3 << 0) 445 #define APBH_DEVSEL_CH0_OFFSET 0 446 #endif 447 448 #if defined(CONFIG_MX28) 449 #define APBH_DMA_BURST_SIZE_CH15_MASK (0x3 << 30) 450 #define APBH_DMA_BURST_SIZE_CH15_OFFSET 30 451 #define APBH_DMA_BURST_SIZE_CH14_MASK (0x3 << 28) 452 #define APBH_DMA_BURST_SIZE_CH14_OFFSET 28 453 #define APBH_DMA_BURST_SIZE_CH13_MASK (0x3 << 26) 454 #define APBH_DMA_BURST_SIZE_CH13_OFFSET 26 455 #define APBH_DMA_BURST_SIZE_CH12_MASK (0x3 << 24) 456 #define APBH_DMA_BURST_SIZE_CH12_OFFSET 24 457 #define APBH_DMA_BURST_SIZE_CH11_MASK (0x3 << 22) 458 #define APBH_DMA_BURST_SIZE_CH11_OFFSET 22 459 #define APBH_DMA_BURST_SIZE_CH10_MASK (0x3 << 20) 460 #define APBH_DMA_BURST_SIZE_CH10_OFFSET 20 461 #define APBH_DMA_BURST_SIZE_CH9_MASK (0x3 << 18) 462 #define APBH_DMA_BURST_SIZE_CH9_OFFSET 18 463 #define APBH_DMA_BURST_SIZE_CH8_MASK (0x3 << 16) 464 #define APBH_DMA_BURST_SIZE_CH8_OFFSET 16 465 #define APBH_DMA_BURST_SIZE_CH8_BURST0 (0x0 << 16) 466 #define APBH_DMA_BURST_SIZE_CH8_BURST4 (0x1 << 16) 467 #define APBH_DMA_BURST_SIZE_CH8_BURST8 (0x2 << 16) 468 #define APBH_DMA_BURST_SIZE_CH7_MASK (0x3 << 14) 469 #define APBH_DMA_BURST_SIZE_CH7_OFFSET 14 470 #define APBH_DMA_BURST_SIZE_CH6_MASK (0x3 << 12) 471 #define APBH_DMA_BURST_SIZE_CH6_OFFSET 12 472 #define APBH_DMA_BURST_SIZE_CH5_MASK (0x3 << 10) 473 #define APBH_DMA_BURST_SIZE_CH5_OFFSET 10 474 #define APBH_DMA_BURST_SIZE_CH4_MASK (0x3 << 8) 475 #define APBH_DMA_BURST_SIZE_CH4_OFFSET 8 476 #define APBH_DMA_BURST_SIZE_CH3_MASK (0x3 << 6) 477 #define APBH_DMA_BURST_SIZE_CH3_OFFSET 6 478 #define APBH_DMA_BURST_SIZE_CH3_BURST0 (0x0 << 6) 479 #define APBH_DMA_BURST_SIZE_CH3_BURST4 (0x1 << 6) 480 #define APBH_DMA_BURST_SIZE_CH3_BURST8 (0x2 << 6) 481 482 #define APBH_DMA_BURST_SIZE_CH2_MASK (0x3 << 4) 483 #define APBH_DMA_BURST_SIZE_CH2_OFFSET 4 484 #define APBH_DMA_BURST_SIZE_CH2_BURST0 (0x0 << 4) 485 #define APBH_DMA_BURST_SIZE_CH2_BURST4 (0x1 << 4) 486 #define APBH_DMA_BURST_SIZE_CH2_BURST8 (0x2 << 4) 487 #define APBH_DMA_BURST_SIZE_CH1_MASK (0x3 << 2) 488 #define APBH_DMA_BURST_SIZE_CH1_OFFSET 2 489 #define APBH_DMA_BURST_SIZE_CH1_BURST0 (0x0 << 2) 490 #define APBH_DMA_BURST_SIZE_CH1_BURST4 (0x1 << 2) 491 #define APBH_DMA_BURST_SIZE_CH1_BURST8 (0x2 << 2) 492 493 #define APBH_DMA_BURST_SIZE_CH0_MASK 0x3 494 #define APBH_DMA_BURST_SIZE_CH0_OFFSET 0 495 #define APBH_DMA_BURST_SIZE_CH0_BURST0 0x0 496 #define APBH_DMA_BURST_SIZE_CH0_BURST4 0x1 497 #define APBH_DMA_BURST_SIZE_CH0_BURST8 0x2 498 499 #define APBH_DEBUG_GPMI_ONE_FIFO (1 << 0) 500 #endif 501 502 #define APBH_CHn_CURCMDAR_CMD_ADDR_MASK 0xffffffff 503 #define APBH_CHn_CURCMDAR_CMD_ADDR_OFFSET 0 504 505 #define APBH_CHn_NXTCMDAR_CMD_ADDR_MASK 0xffffffff 506 #define APBH_CHn_NXTCMDAR_CMD_ADDR_OFFSET 0 507 508 #define APBH_CHn_CMD_XFER_COUNT_MASK (0xffff << 16) 509 #define APBH_CHn_CMD_XFER_COUNT_OFFSET 16 510 #define APBH_CHn_CMD_CMDWORDS_MASK (0xf << 12) 511 #define APBH_CHn_CMD_CMDWORDS_OFFSET 12 512 #define APBH_CHn_CMD_HALTONTERMINATE (1 << 8) 513 #define APBH_CHn_CMD_WAIT4ENDCMD (1 << 7) 514 #define APBH_CHn_CMD_SEMAPHORE (1 << 6) 515 #define APBH_CHn_CMD_NANDWAIT4READY (1 << 5) 516 #define APBH_CHn_CMD_NANDLOCK (1 << 4) 517 #define APBH_CHn_CMD_IRQONCMPLT (1 << 3) 518 #define APBH_CHn_CMD_CHAIN (1 << 2) 519 #define APBH_CHn_CMD_COMMAND_MASK 0x3 520 #define APBH_CHn_CMD_COMMAND_OFFSET 0 521 #define APBH_CHn_CMD_COMMAND_NO_DMA_XFER 0x0 522 #define APBH_CHn_CMD_COMMAND_DMA_WRITE 0x1 523 #define APBH_CHn_CMD_COMMAND_DMA_READ 0x2 524 #define APBH_CHn_CMD_COMMAND_DMA_SENSE 0x3 525 526 #define APBH_CHn_BAR_ADDRESS_MASK 0xffffffff 527 #define APBH_CHn_BAR_ADDRESS_OFFSET 0 528 529 #define APBH_CHn_SEMA_RSVD2_MASK (0xff << 24) 530 #define APBH_CHn_SEMA_RSVD2_OFFSET 24 531 #define APBH_CHn_SEMA_PHORE_MASK (0xff << 16) 532 #define APBH_CHn_SEMA_PHORE_OFFSET 16 533 #define APBH_CHn_SEMA_RSVD1_MASK (0xff << 8) 534 #define APBH_CHn_SEMA_RSVD1_OFFSET 8 535 #define APBH_CHn_SEMA_INCREMENT_SEMA_MASK (0xff << 0) 536 #define APBH_CHn_SEMA_INCREMENT_SEMA_OFFSET 0 537 538 #define APBH_CHn_DEBUG1_REQ (1 << 31) 539 #define APBH_CHn_DEBUG1_BURST (1 << 30) 540 #define APBH_CHn_DEBUG1_KICK (1 << 29) 541 #define APBH_CHn_DEBUG1_END (1 << 28) 542 #define APBH_CHn_DEBUG1_SENSE (1 << 27) 543 #define APBH_CHn_DEBUG1_READY (1 << 26) 544 #define APBH_CHn_DEBUG1_LOCK (1 << 25) 545 #define APBH_CHn_DEBUG1_NEXTCMDADDRVALID (1 << 24) 546 #define APBH_CHn_DEBUG1_RD_FIFO_EMPTY (1 << 23) 547 #define APBH_CHn_DEBUG1_RD_FIFO_FULL (1 << 22) 548 #define APBH_CHn_DEBUG1_WR_FIFO_EMPTY (1 << 21) 549 #define APBH_CHn_DEBUG1_WR_FIFO_FULL (1 << 20) 550 #define APBH_CHn_DEBUG1_RSVD1_MASK (0x7fff << 5) 551 #define APBH_CHn_DEBUG1_RSVD1_OFFSET 5 552 #define APBH_CHn_DEBUG1_STATEMACHINE_MASK 0x1f 553 #define APBH_CHn_DEBUG1_STATEMACHINE_OFFSET 0 554 #define APBH_CHn_DEBUG1_STATEMACHINE_IDLE 0x00 555 #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD1 0x01 556 #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD3 0x02 557 #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD2 0x03 558 #define APBH_CHn_DEBUG1_STATEMACHINE_XFER_DECODE 0x04 559 #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_WAIT 0x05 560 #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD4 0x06 561 #define APBH_CHn_DEBUG1_STATEMACHINE_PIO_REQ 0x07 562 #define APBH_CHn_DEBUG1_STATEMACHINE_READ_FLUSH 0x08 563 #define APBH_CHn_DEBUG1_STATEMACHINE_READ_WAIT 0x09 564 #define APBH_CHn_DEBUG1_STATEMACHINE_WRITE 0x0c 565 #define APBH_CHn_DEBUG1_STATEMACHINE_READ_REQ 0x0d 566 #define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_CHAIN 0x0e 567 #define APBH_CHn_DEBUG1_STATEMACHINE_XFER_COMPLETE 0x0f 568 #define APBH_CHn_DEBUG1_STATEMACHINE_TERMINATE 0x14 569 #define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_END 0x15 570 #define APBH_CHn_DEBUG1_STATEMACHINE_WRITE_WAIT 0x1c 571 #define APBH_CHn_DEBUG1_STATEMACHINE_HALT_AFTER_TERM 0x1d 572 #define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_WAIT 0x1e 573 #define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_READY 0x1f 574 575 #define APBH_CHn_DEBUG2_APB_BYTES_MASK (0xffff << 16) 576 #define APBH_CHn_DEBUG2_APB_BYTES_OFFSET 16 577 #define APBH_CHn_DEBUG2_AHB_BYTES_MASK 0xffff 578 #define APBH_CHn_DEBUG2_AHB_BYTES_OFFSET 0 579 580 #define APBH_VERSION_MAJOR_MASK (0xff << 24) 581 #define APBH_VERSION_MAJOR_OFFSET 24 582 #define APBH_VERSION_MINOR_MASK (0xff << 16) 583 #define APBH_VERSION_MINOR_OFFSET 16 584 #define APBH_VERSION_STEP_MASK 0xffff 585 #define APBH_VERSION_STEP_OFFSET 0 586 587 #endif /* __REGS_APBH_H__ */ 588