1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2012,2015 Stephen Warren 4 */ 5 6 #ifndef _BCM2835_MBOX_H 7 #define _BCM2835_MBOX_H 8 9 #include <linux/compiler.h> 10 #include <asm/arch/base.h> 11 12 /* 13 * The BCM2835 SoC contains (at least) two CPUs; the VideoCore (a/k/a "GPU") 14 * and the ARM CPU. The ARM CPU is often thought of as the main CPU. 15 * However, the VideoCore actually controls the initial SoC boot, and hides 16 * much of the hardware behind a protocol. This protocol is transported 17 * using the SoC's mailbox hardware module. 18 * 19 * The mailbox hardware supports passing 32-bit values back and forth. 20 * Presumably by software convention of the firmware, the bottom 4 bits of the 21 * value are used to indicate a logical channel, and the upper 28 bits are the 22 * actual payload. Various channels exist using these simple raw messages. See 23 * https://github.com/raspberrypi/firmware/wiki/Mailboxes for a list. As an 24 * example, the messages on the power management channel are a bitmask of 25 * devices whose power should be enabled. 26 * 27 * The property mailbox channel passes messages that contain the (16-byte 28 * aligned) ARM physical address of a memory buffer. This buffer is passed to 29 * the VC for processing, is modified in-place by the VC, and the address then 30 * passed back to the ARM CPU as the response mailbox message to indicate 31 * request completion. The buffers have a generic and extensible format; each 32 * buffer contains a standard header, a list of "tags", and a terminating zero 33 * entry. Each tag contains an ID indicating its type, and length fields for 34 * generic parsing. With some limitations, an arbitrary set of tags may be 35 * combined together into a single message buffer. This file defines structs 36 * representing the header and many individual tag layouts and IDs. 37 */ 38 39 /* Raw mailbox HW */ 40 41 #define BCM2835_MBOX_PHYSADDR ({ BUG_ON(!rpi_bcm283x_base); \ 42 rpi_bcm283x_base + 0x0000b880; }) 43 44 struct bcm2835_mbox_regs { 45 u32 read; 46 u32 rsvd0[5]; 47 u32 mail0_status; 48 u32 mail0_config; 49 u32 write; 50 u32 rsvd1[5]; 51 u32 mail1_status; 52 u32 mail1_config; 53 }; 54 55 #define BCM2835_MBOX_STATUS_WR_FULL 0x80000000 56 #define BCM2835_MBOX_STATUS_RD_EMPTY 0x40000000 57 58 /* Lower 4-bits are channel ID */ 59 #define BCM2835_CHAN_MASK 0xf 60 #define BCM2835_MBOX_PACK(chan, data) (((data) & (~BCM2835_CHAN_MASK)) | \ 61 (chan & BCM2835_CHAN_MASK)) 62 #define BCM2835_MBOX_UNPACK_CHAN(val) ((val) & BCM2835_CHAN_MASK) 63 #define BCM2835_MBOX_UNPACK_DATA(val) ((val) & (~BCM2835_CHAN_MASK)) 64 65 /* Property mailbox buffer structures */ 66 67 #define BCM2835_MBOX_PROP_CHAN 8 68 69 /* All message buffers must start with this header */ 70 struct bcm2835_mbox_hdr { 71 u32 buf_size; 72 u32 code; 73 }; 74 75 #define BCM2835_MBOX_REQ_CODE 0 76 #define BCM2835_MBOX_RESP_CODE_SUCCESS 0x80000000 77 78 #define BCM2835_MBOX_INIT_HDR(_m_) { \ 79 memset((_m_), 0, sizeof(*(_m_))); \ 80 (_m_)->hdr.buf_size = sizeof(*(_m_)); \ 81 (_m_)->hdr.code = 0; \ 82 (_m_)->end_tag = 0; \ 83 } 84 85 /* 86 * A message buffer contains a list of tags. Each tag must also start with 87 * a standardized header. 88 */ 89 struct bcm2835_mbox_tag_hdr { 90 u32 tag; 91 u32 val_buf_size; 92 u32 val_len; 93 }; 94 95 #define BCM2835_MBOX_INIT_TAG(_t_, _id_) { \ 96 (_t_)->tag_hdr.tag = BCM2835_MBOX_TAG_##_id_; \ 97 (_t_)->tag_hdr.val_buf_size = sizeof((_t_)->body); \ 98 (_t_)->tag_hdr.val_len = sizeof((_t_)->body.req); \ 99 } 100 101 #define BCM2835_MBOX_INIT_TAG_NO_REQ(_t_, _id_) { \ 102 (_t_)->tag_hdr.tag = BCM2835_MBOX_TAG_##_id_; \ 103 (_t_)->tag_hdr.val_buf_size = sizeof((_t_)->body); \ 104 (_t_)->tag_hdr.val_len = 0; \ 105 } 106 107 /* When responding, the VC sets this bit in val_len to indicate a response */ 108 #define BCM2835_MBOX_TAG_VAL_LEN_RESPONSE 0x80000000 109 110 /* 111 * Below we define the ID and struct for many possible tags. This header only 112 * defines individual tag structs, not entire message structs, since in 113 * general an arbitrary set of tags may be combined into a single message. 114 * Clients of the mbox API are expected to define their own overall message 115 * structures by combining the header, a set of tags, and a terminating 116 * entry. For example, 117 * 118 * struct msg { 119 * struct bcm2835_mbox_hdr hdr; 120 * struct bcm2835_mbox_tag_get_arm_mem get_arm_mem; 121 * ... perhaps other tags here ... 122 * u32 end_tag; 123 * }; 124 */ 125 126 #define BCM2835_MBOX_TAG_GET_BOARD_REV 0x00010002 127 128 struct bcm2835_mbox_tag_get_board_rev { 129 struct bcm2835_mbox_tag_hdr tag_hdr; 130 union { 131 struct { 132 } req; 133 struct { 134 u32 rev; 135 } resp; 136 } body; 137 }; 138 139 #define BCM2835_MBOX_TAG_GET_MAC_ADDRESS 0x00010003 140 141 struct bcm2835_mbox_tag_get_mac_address { 142 struct bcm2835_mbox_tag_hdr tag_hdr; 143 union { 144 struct { 145 } req; 146 struct { 147 u8 mac[6]; 148 u8 pad[2]; 149 } resp; 150 } body; 151 }; 152 153 #define BCM2835_MBOX_TAG_GET_BOARD_SERIAL 0x00010004 154 155 struct bcm2835_mbox_tag_get_board_serial { 156 struct bcm2835_mbox_tag_hdr tag_hdr; 157 union { 158 struct __packed { 159 u64 serial; 160 } resp; 161 } body; 162 }; 163 164 #define BCM2835_MBOX_TAG_GET_ARM_MEMORY 0x00010005 165 166 struct bcm2835_mbox_tag_get_arm_mem { 167 struct bcm2835_mbox_tag_hdr tag_hdr; 168 union { 169 struct { 170 } req; 171 struct { 172 u32 mem_base; 173 u32 mem_size; 174 } resp; 175 } body; 176 }; 177 178 #define BCM2835_MBOX_POWER_DEVID_SDHCI 0 179 #define BCM2835_MBOX_POWER_DEVID_UART0 1 180 #define BCM2835_MBOX_POWER_DEVID_UART1 2 181 #define BCM2835_MBOX_POWER_DEVID_USB_HCD 3 182 #define BCM2835_MBOX_POWER_DEVID_I2C0 4 183 #define BCM2835_MBOX_POWER_DEVID_I2C1 5 184 #define BCM2835_MBOX_POWER_DEVID_I2C2 6 185 #define BCM2835_MBOX_POWER_DEVID_SPI 7 186 #define BCM2835_MBOX_POWER_DEVID_CCP2TX 8 187 188 #define BCM2835_MBOX_POWER_STATE_RESP_ON (1 << 0) 189 /* Device doesn't exist */ 190 #define BCM2835_MBOX_POWER_STATE_RESP_NODEV (1 << 1) 191 192 #define BCM2835_MBOX_TAG_GET_POWER_STATE 0x00020001 193 194 struct bcm2835_mbox_tag_get_power_state { 195 struct bcm2835_mbox_tag_hdr tag_hdr; 196 union { 197 struct { 198 u32 device_id; 199 } req; 200 struct { 201 u32 device_id; 202 u32 state; 203 } resp; 204 } body; 205 }; 206 207 #define BCM2835_MBOX_TAG_SET_POWER_STATE 0x00028001 208 209 #define BCM2835_MBOX_SET_POWER_STATE_REQ_ON (1 << 0) 210 #define BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT (1 << 1) 211 212 struct bcm2835_mbox_tag_set_power_state { 213 struct bcm2835_mbox_tag_hdr tag_hdr; 214 union { 215 struct { 216 u32 device_id; 217 u32 state; 218 } req; 219 struct { 220 u32 device_id; 221 u32 state; 222 } resp; 223 } body; 224 }; 225 226 #define BCM2835_MBOX_TAG_GET_CLOCK_RATE 0x00030002 227 228 #define BCM2835_MBOX_CLOCK_ID_EMMC 1 229 #define BCM2835_MBOX_CLOCK_ID_UART 2 230 #define BCM2835_MBOX_CLOCK_ID_ARM 3 231 #define BCM2835_MBOX_CLOCK_ID_CORE 4 232 #define BCM2835_MBOX_CLOCK_ID_V3D 5 233 #define BCM2835_MBOX_CLOCK_ID_H264 6 234 #define BCM2835_MBOX_CLOCK_ID_ISP 7 235 #define BCM2835_MBOX_CLOCK_ID_SDRAM 8 236 #define BCM2835_MBOX_CLOCK_ID_PIXEL 9 237 #define BCM2835_MBOX_CLOCK_ID_PWM 10 238 #define BCM2835_MBOX_CLOCK_ID_EMMC2 12 239 240 struct bcm2835_mbox_tag_get_clock_rate { 241 struct bcm2835_mbox_tag_hdr tag_hdr; 242 union { 243 struct { 244 u32 clock_id; 245 } req; 246 struct { 247 u32 clock_id; 248 u32 rate_hz; 249 } resp; 250 } body; 251 }; 252 253 #define BCM2835_MBOX_TAG_ALLOCATE_BUFFER 0x00040001 254 255 struct bcm2835_mbox_tag_allocate_buffer { 256 struct bcm2835_mbox_tag_hdr tag_hdr; 257 union { 258 struct { 259 u32 alignment; 260 } req; 261 struct { 262 u32 fb_address; 263 u32 fb_size; 264 } resp; 265 } body; 266 }; 267 268 #define BCM2835_MBOX_TAG_RELEASE_BUFFER 0x00048001 269 270 struct bcm2835_mbox_tag_release_buffer { 271 struct bcm2835_mbox_tag_hdr tag_hdr; 272 union { 273 struct { 274 } req; 275 struct { 276 } resp; 277 } body; 278 }; 279 280 #define BCM2835_MBOX_TAG_BLANK_SCREEN 0x00040002 281 282 struct bcm2835_mbox_tag_blank_screen { 283 struct bcm2835_mbox_tag_hdr tag_hdr; 284 union { 285 struct { 286 /* bit 0 means on, other bots reserved */ 287 u32 state; 288 } req; 289 struct { 290 u32 state; 291 } resp; 292 } body; 293 }; 294 295 /* Physical means output signal */ 296 #define BCM2835_MBOX_TAG_GET_PHYSICAL_W_H 0x00040003 297 #define BCM2835_MBOX_TAG_TEST_PHYSICAL_W_H 0x00044003 298 #define BCM2835_MBOX_TAG_SET_PHYSICAL_W_H 0x00048003 299 300 struct bcm2835_mbox_tag_physical_w_h { 301 struct bcm2835_mbox_tag_hdr tag_hdr; 302 union { 303 /* req not used for get */ 304 struct { 305 u32 width; 306 u32 height; 307 } req; 308 struct { 309 u32 width; 310 u32 height; 311 } resp; 312 } body; 313 }; 314 315 /* Virtual means display buffer */ 316 #define BCM2835_MBOX_TAG_GET_VIRTUAL_W_H 0x00040004 317 #define BCM2835_MBOX_TAG_TEST_VIRTUAL_W_H 0x00044004 318 #define BCM2835_MBOX_TAG_SET_VIRTUAL_W_H 0x00048004 319 320 struct bcm2835_mbox_tag_virtual_w_h { 321 struct bcm2835_mbox_tag_hdr tag_hdr; 322 union { 323 /* req not used for get */ 324 struct { 325 u32 width; 326 u32 height; 327 } req; 328 struct { 329 u32 width; 330 u32 height; 331 } resp; 332 } body; 333 }; 334 335 #define BCM2835_MBOX_TAG_GET_DEPTH 0x00040005 336 #define BCM2835_MBOX_TAG_TEST_DEPTH 0x00044005 337 #define BCM2835_MBOX_TAG_SET_DEPTH 0x00048005 338 339 struct bcm2835_mbox_tag_depth { 340 struct bcm2835_mbox_tag_hdr tag_hdr; 341 union { 342 /* req not used for get */ 343 struct { 344 u32 bpp; 345 } req; 346 struct { 347 u32 bpp; 348 } resp; 349 } body; 350 }; 351 352 #define BCM2835_MBOX_TAG_GET_PIXEL_ORDER 0x00040006 353 #define BCM2835_MBOX_TAG_TEST_PIXEL_ORDER 0x00044006 354 #define BCM2835_MBOX_TAG_SET_PIXEL_ORDER 0x00048006 355 356 #define BCM2835_MBOX_PIXEL_ORDER_BGR 0 357 #define BCM2835_MBOX_PIXEL_ORDER_RGB 1 358 359 struct bcm2835_mbox_tag_pixel_order { 360 struct bcm2835_mbox_tag_hdr tag_hdr; 361 union { 362 /* req not used for get */ 363 struct { 364 u32 order; 365 } req; 366 struct { 367 u32 order; 368 } resp; 369 } body; 370 }; 371 372 #define BCM2835_MBOX_TAG_GET_ALPHA_MODE 0x00040007 373 #define BCM2835_MBOX_TAG_TEST_ALPHA_MODE 0x00044007 374 #define BCM2835_MBOX_TAG_SET_ALPHA_MODE 0x00048007 375 376 #define BCM2835_MBOX_ALPHA_MODE_0_OPAQUE 0 377 #define BCM2835_MBOX_ALPHA_MODE_0_TRANSPARENT 1 378 #define BCM2835_MBOX_ALPHA_MODE_IGNORED 2 379 380 struct bcm2835_mbox_tag_alpha_mode { 381 struct bcm2835_mbox_tag_hdr tag_hdr; 382 union { 383 /* req not used for get */ 384 struct { 385 u32 alpha; 386 } req; 387 struct { 388 u32 alpha; 389 } resp; 390 } body; 391 }; 392 393 #define BCM2835_MBOX_TAG_GET_PITCH 0x00040008 394 395 struct bcm2835_mbox_tag_pitch { 396 struct bcm2835_mbox_tag_hdr tag_hdr; 397 union { 398 struct { 399 } req; 400 struct { 401 u32 pitch; 402 } resp; 403 } body; 404 }; 405 406 /* Offset of display window within buffer */ 407 #define BCM2835_MBOX_TAG_GET_VIRTUAL_OFFSET 0x00040009 408 #define BCM2835_MBOX_TAG_TEST_VIRTUAL_OFFSET 0x00044009 409 #define BCM2835_MBOX_TAG_SET_VIRTUAL_OFFSET 0x00048009 410 411 struct bcm2835_mbox_tag_virtual_offset { 412 struct bcm2835_mbox_tag_hdr tag_hdr; 413 union { 414 /* req not used for get */ 415 struct { 416 u32 x; 417 u32 y; 418 } req; 419 struct { 420 u32 x; 421 u32 y; 422 } resp; 423 } body; 424 }; 425 426 #define BCM2835_MBOX_TAG_GET_OVERSCAN 0x0004000a 427 #define BCM2835_MBOX_TAG_TEST_OVERSCAN 0x0004400a 428 #define BCM2835_MBOX_TAG_SET_OVERSCAN 0x0004800a 429 430 struct bcm2835_mbox_tag_overscan { 431 struct bcm2835_mbox_tag_hdr tag_hdr; 432 union { 433 /* req not used for get */ 434 struct { 435 u32 top; 436 u32 bottom; 437 u32 left; 438 u32 right; 439 } req; 440 struct { 441 u32 top; 442 u32 bottom; 443 u32 left; 444 u32 right; 445 } resp; 446 } body; 447 }; 448 449 #define BCM2835_MBOX_TAG_GET_PALETTE 0x0004000b 450 451 struct bcm2835_mbox_tag_get_palette { 452 struct bcm2835_mbox_tag_hdr tag_hdr; 453 union { 454 struct { 455 } req; 456 struct { 457 u32 data[1024]; 458 } resp; 459 } body; 460 }; 461 462 #define BCM2835_MBOX_TAG_TEST_PALETTE 0x0004400b 463 464 struct bcm2835_mbox_tag_test_palette { 465 struct bcm2835_mbox_tag_hdr tag_hdr; 466 union { 467 struct { 468 u32 offset; 469 u32 num_entries; 470 u32 data[256]; 471 } req; 472 struct { 473 u32 is_invalid; 474 } resp; 475 } body; 476 }; 477 478 #define BCM2835_MBOX_TAG_SET_PALETTE 0x0004800b 479 480 struct bcm2835_mbox_tag_set_palette { 481 struct bcm2835_mbox_tag_hdr tag_hdr; 482 union { 483 struct { 484 u32 offset; 485 u32 num_entries; 486 u32 data[256]; 487 } req; 488 struct { 489 u32 is_invalid; 490 } resp; 491 } body; 492 }; 493 494 #define BCM2835_MBOX_TAG_NOTIFY_XHCI_RESET 0x00030058 495 496 struct bcm2835_mbox_tag_pci_dev_addr { 497 struct bcm2835_mbox_tag_hdr tag_hdr; 498 union { 499 struct { 500 u32 dev_addr; 501 } req; 502 struct { 503 } resp; 504 } body; 505 }; 506 507 /* 508 * Pass a raw u32 message to the VC, and receive a raw u32 back. 509 * 510 * Returns 0 for success, any other value for error. 511 */ 512 int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv); 513 514 /* 515 * Pass a complete property-style buffer to the VC, and wait until it has 516 * been processed. 517 * 518 * This function expects a pointer to the mbox_hdr structure in an attempt 519 * to ensure some degree of type safety. However, some number of tags and 520 * a termination value are expected to immediately follow the header in 521 * memory, as required by the property protocol. 522 * 523 * Each struct bcm2835_mbox_hdr passed must be allocated with 524 * ALLOC_CACHE_ALIGN_BUFFER(x, y, z) to ensure proper cache flush/invalidate. 525 * 526 * Returns 0 for success, any other value for error. 527 */ 528 int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer); 529 530 #endif 531