1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <asm-offsets.h>
8 #include <mpc83xx.h>
9 #include <ioports.h>
10 #include <asm/global_data.h>
11 #include <asm/io.h>
12 #include <asm/processor.h>
13 #include <fsl_qe.h>
14 #ifdef CONFIG_USB_EHCI_FSL
15 #include <usb/ehci-ci.h>
16 #endif
17 #include <linux/delay.h>
18 #ifdef CONFIG_QE
19 #include <fsl_qe.h>
20 #endif
21
22 #include "lblaw/lblaw.h"
23 #include "elbc/elbc.h"
24 #include "sysio/sysio.h"
25 #include "arbiter/arbiter.h"
26 #include "initreg/initreg.h"
27
28 DECLARE_GLOBAL_DATA_PTR;
29
30 #ifdef CONFIG_QE
31 extern qe_iop_conf_t qe_iop_conf_tab[];
32 extern void qe_config_iopin(u8 port, u8 pin, int dir,
33 int open_drain, int assign);
34
35 #if !defined(CONFIG_PINCTRL)
config_qe_ioports(void)36 static void config_qe_ioports(void)
37 {
38 u8 port, pin;
39 int dir, open_drain, assign;
40 int i;
41
42 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
43 port = qe_iop_conf_tab[i].port;
44 pin = qe_iop_conf_tab[i].pin;
45 dir = qe_iop_conf_tab[i].dir;
46 open_drain = qe_iop_conf_tab[i].open_drain;
47 assign = qe_iop_conf_tab[i].assign;
48 qe_config_iopin(port, pin, dir, open_drain, assign);
49 }
50 }
51 #endif
52 #endif
53
54 /*
55 * Breathe some life into the CPU...
56 *
57 * Set up the memory map,
58 * initialize a bunch of registers,
59 * initialize the UPM's
60 */
cpu_init_f(volatile immap_t * im)61 void cpu_init_f (volatile immap_t * im)
62 {
63 __be32 sccr_mask =
64 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
65 SCCR_ENCCM |
66 #endif
67 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
68 SCCR_PCICM |
69 #endif
70 #ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */
71 SCCR_PCIEXP1CM |
72 #endif
73 #ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */
74 SCCR_PCIEXP2CM |
75 #endif
76 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
77 SCCR_TSECCM |
78 #endif
79 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
80 SCCR_TSEC1CM |
81 #endif
82 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
83 SCCR_TSEC2CM |
84 #endif
85 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
86 SCCR_TSEC1ON |
87 #endif
88 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
89 SCCR_TSEC2ON |
90 #endif
91 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
92 SCCR_USBMPHCM |
93 #endif
94 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
95 SCCR_USBDRCM |
96 #endif
97 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
98 SCCR_SATACM |
99 #endif
100 0;
101 __be32 sccr_val =
102 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
103 (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
104 #endif
105 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
106 (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
107 #endif
108 #ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */
109 (CONFIG_SYS_SCCR_PCIEXP1CM << SCCR_PCIEXP1CM_SHIFT) |
110 #endif
111 #ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */
112 (CONFIG_SYS_SCCR_PCIEXP2CM << SCCR_PCIEXP2CM_SHIFT) |
113 #endif
114 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
115 (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
116 #endif
117 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
118 (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
119 #endif
120 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
121 (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
122 #endif
123 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
124 (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
125 #endif
126 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
127 (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
128 #endif
129 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
130 (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
131 #endif
132 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
133 (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
134 #endif
135 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
136 (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
137 #endif
138 0;
139
140 /* Pointer is writable since we allocated a register for it */
141 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
142
143 /* global data region was cleared in start.S */
144
145 /* system performance tweaking */
146 clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
147
148 clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
149
150 clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
151
152 /* RSR - Reset Status Register - clear all status (4.6.1.3) */
153 gd->arch.reset_status = __raw_readl(&im->reset.rsr);
154 __raw_writel(~(RSR_RES), &im->reset.rsr);
155
156 /* AER - Arbiter Event Register - store status */
157 gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
158 gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
159
160 /*
161 * RMR - Reset Mode Register
162 * contains checkstop reset enable (4.6.1.4)
163 */
164 __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
165
166 /* LCRR - Clock Ratio Register (10.3.1.16)
167 * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
168 */
169 clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val);
170 __raw_readl(&im->im_lbc.lcrr);
171 isync();
172
173 /* Enable Time Base & Decrementer ( so we will have udelay() )*/
174 setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
175
176 /* System General Purpose Register */
177 #ifdef CONFIG_SYS_SICRH
178 #if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313)
179 /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
180 __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
181 &im->sysconf.sicrh);
182 #else
183 __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
184 #endif
185 #endif
186 #ifdef CONFIG_SYS_SICRL
187 __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
188 #endif
189 #ifdef CONFIG_SYS_GPR1
190 __raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1);
191 #endif
192 #ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
193 __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
194 #endif
195 #ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
196 __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
197 #endif
198
199 #if !defined(CONFIG_PINCTRL)
200 #ifdef CONFIG_QE
201 /* Config QE ioports */
202 config_qe_ioports();
203 #endif
204 #endif
205
206 /* Set up preliminary BR/OR regs */
207 init_early_memctl_regs();
208
209 /* Local Access window setup */
210 #if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
211 im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
212 im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
213 #else
214 #error CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
215 #endif
216
217 #if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
218 im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
219 im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
220 #endif
221 #if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
222 im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
223 im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
224 #endif
225 #if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
226 im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
227 im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
228 #endif
229 #if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
230 im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
231 im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
232 #endif
233 #if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
234 im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
235 im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
236 #endif
237 #if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
238 im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
239 im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
240 #endif
241 #if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
242 im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
243 im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
244 #endif
245 #ifdef CONFIG_SYS_GPIO1_PRELIM
246 im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT;
247 im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR;
248 #endif
249 #ifdef CONFIG_SYS_GPIO2_PRELIM
250 im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
251 im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
252 #endif
253 #if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X)
254 uint32_t temp;
255 struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
256
257 /* Configure interface. */
258 setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
259
260 /* Wait for clock to stabilize */
261 do {
262 temp = __raw_readl(&ehci->control);
263 udelay(1000);
264 } while (!(temp & PHY_CLK_VALID));
265 #endif
266 }
267
cpu_init_r(void)268 int cpu_init_r (void)
269 {
270 #ifdef CONFIG_QE
271 uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
272
273 qe_init(qe_base);
274 qe_reset();
275 #endif
276 return 0;
277 }
278
279 /*
280 * Print out the bus arbiter event
281 */
282 #if defined(CONFIG_DISPLAY_AER_FULL)
print_83xx_arb_event(int force)283 static int print_83xx_arb_event(int force)
284 {
285 static char* event[] = {
286 "Address Time Out",
287 "Data Time Out",
288 "Address Only Transfer Type",
289 "External Control Word Transfer Type",
290 "Reserved Transfer Type",
291 "Transfer Error",
292 "reserved",
293 "reserved"
294 };
295 static char* master[] = {
296 "e300 Core Data Transaction",
297 "reserved",
298 "e300 Core Instruction Fetch",
299 "reserved",
300 "TSEC1",
301 "TSEC2",
302 "USB MPH",
303 "USB DR",
304 "Encryption Core",
305 "I2C Boot Sequencer",
306 "JTAG",
307 "reserved",
308 "eSDHC",
309 "PCI1",
310 "PCI2",
311 "DMA",
312 "QUICC Engine 00",
313 "QUICC Engine 01",
314 "QUICC Engine 10",
315 "QUICC Engine 11",
316 "reserved",
317 "reserved",
318 "reserved",
319 "reserved",
320 "SATA1",
321 "SATA2",
322 "SATA3",
323 "SATA4",
324 "reserved",
325 "PCI Express 1",
326 "PCI Express 2",
327 "TDM-DMAC"
328 };
329 static char *transfer[] = {
330 "Address-only, Clean Block",
331 "Address-only, lwarx reservation set",
332 "Single-beat or Burst write",
333 "reserved",
334 "Address-only, Flush Block",
335 "reserved",
336 "Burst write",
337 "reserved",
338 "Address-only, sync",
339 "Address-only, tlbsync",
340 "Single-beat or Burst read",
341 "Single-beat or Burst read",
342 "Address-only, Kill Block",
343 "Address-only, icbi",
344 "Burst read",
345 "reserved",
346 "Address-only, eieio",
347 "reserved",
348 "Single-beat write",
349 "reserved",
350 "ecowx - Illegal single-beat write",
351 "reserved",
352 "reserved",
353 "reserved",
354 "Address-only, TLB Invalidate",
355 "reserved",
356 "Single-beat or Burst read",
357 "reserved",
358 "eciwx - Illegal single-beat read",
359 "reserved",
360 "Burst read",
361 "reserved"
362 };
363
364 int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT)
365 >> AEATR_EVENT_SHIFT;
366 int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID)
367 >> AEATR_MSTR_ID_SHIFT;
368 int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST)
369 >> AEATR_TBST_SHIFT;
370 int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE)
371 >> AEATR_TSIZE_SHIFT;
372 int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE)
373 >> AEATR_TTYPE_SHIFT;
374
375 if (!force && !gd->arch.arbiter_event_address)
376 return 0;
377
378 puts("Arbiter Event Status:\n");
379 printf(" Event Address: 0x%08lX\n",
380 gd->arch.arbiter_event_address);
381 printf(" Event Type: 0x%1x = %s\n", etype, event[etype]);
382 printf(" Master ID: 0x%02x = %s\n", mstr_id, master[mstr_id]);
383 printf(" Transfer Size: 0x%1x = %d bytes\n", (tbst<<3) | tsize,
384 tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
385 printf(" Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
386
387 return gd->arch.arbiter_event_address;
388 }
389
390 #elif defined(CONFIG_DISPLAY_AER_BRIEF)
391
print_83xx_arb_event(int force)392 static int print_83xx_arb_event(int force)
393 {
394 if (!force && !gd->arch.arbiter_event_address)
395 return 0;
396
397 printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
398 gd->arch.arbiter_event_attributes,
399 gd->arch.arbiter_event_address);
400
401 return gd->arch.arbiter_event_address;
402 }
403 #endif /* CONFIG_DISPLAY_AER_xxxx */
404
405 #ifndef CONFIG_CPU_MPC83XX
406 /*
407 * Figure out the cause of the reset
408 */
prt_83xx_rsr(void)409 int prt_83xx_rsr(void)
410 {
411 static struct {
412 ulong mask;
413 char *desc;
414 } bits[] = {
415 {
416 RSR_SWSR, "Software Soft"}, {
417 RSR_SWHR, "Software Hard"}, {
418 RSR_JSRS, "JTAG Soft"}, {
419 RSR_CSHR, "Check Stop"}, {
420 RSR_SWRS, "Software Watchdog"}, {
421 RSR_BMRS, "Bus Monitor"}, {
422 RSR_SRS, "External/Internal Soft"}, {
423 RSR_HRS, "External/Internal Hard"}
424 };
425 static int n = ARRAY_SIZE(bits);
426 ulong rsr = gd->arch.reset_status;
427 int i;
428 char *sep;
429
430 puts("Reset Status:");
431
432 sep = " ";
433 for (i = 0; i < n; i++)
434 if (rsr & bits[i].mask) {
435 printf("%s%s", sep, bits[i].desc);
436 sep = ", ";
437 }
438 puts("\n");
439
440 #if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
441 print_83xx_arb_event(rsr & RSR_BMRS);
442 #endif
443 puts("\n");
444
445 return 0;
446 }
447 #endif
448