1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Renesas RCar Gen3 RPC QSPI driver
4 *
5 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
6 */
7
8 #include <common.h>
9 #include <asm/global_data.h>
10 #include <asm/io.h>
11 #include <clk.h>
12 #include <dm.h>
13 #include <dm/of_access.h>
14 #include <dt-structs.h>
15 #include <errno.h>
16 #include <linux/bitops.h>
17 #include <linux/bug.h>
18 #include <linux/errno.h>
19 #include <spi.h>
20 #include <wait_bit.h>
21
22 #define RPC_CMNCR 0x0000 /* R/W */
23 #define RPC_CMNCR_MD BIT(31)
24 #define RPC_CMNCR_SFDE BIT(24)
25 #define RPC_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
26 #define RPC_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
27 #define RPC_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
28 #define RPC_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
29 #define RPC_CMNCR_MOIIO_HIZ (RPC_CMNCR_MOIIO0(3) | RPC_CMNCR_MOIIO1(3) | \
30 RPC_CMNCR_MOIIO2(3) | RPC_CMNCR_MOIIO3(3))
31 #define RPC_CMNCR_IO3FV(val) (((val) & 0x3) << 14)
32 #define RPC_CMNCR_IO2FV(val) (((val) & 0x3) << 12)
33 #define RPC_CMNCR_IO0FV(val) (((val) & 0x3) << 8)
34 #define RPC_CMNCR_IOFV_HIZ (RPC_CMNCR_IO0FV(3) | RPC_CMNCR_IO2FV(3) | \
35 RPC_CMNCR_IO3FV(3))
36 #define RPC_CMNCR_CPHAT BIT(6)
37 #define RPC_CMNCR_CPHAR BIT(5)
38 #define RPC_CMNCR_SSLP BIT(4)
39 #define RPC_CMNCR_CPOL BIT(3)
40 #define RPC_CMNCR_BSZ(val) (((val) & 0x3) << 0)
41
42 #define RPC_SSLDR 0x0004 /* R/W */
43 #define RPC_SSLDR_SPNDL(d) (((d) & 0x7) << 16)
44 #define RPC_SSLDR_SLNDL(d) (((d) & 0x7) << 8)
45 #define RPC_SSLDR_SCKDL(d) (((d) & 0x7) << 0)
46
47 #define RPC_DRCR 0x000C /* R/W */
48 #define RPC_DRCR_SSLN BIT(24)
49 #define RPC_DRCR_RBURST(v) (((v) & 0x1F) << 16)
50 #define RPC_DRCR_RCF BIT(9)
51 #define RPC_DRCR_RBE BIT(8)
52 #define RPC_DRCR_SSLE BIT(0)
53
54 #define RPC_DRCMR 0x0010 /* R/W */
55 #define RPC_DRCMR_CMD(c) (((c) & 0xFF) << 16)
56 #define RPC_DRCMR_OCMD(c) (((c) & 0xFF) << 0)
57
58 #define RPC_DREAR 0x0014 /* R/W */
59 #define RPC_DREAR_EAV(v) (((v) & 0xFF) << 16)
60 #define RPC_DREAR_EAC(v) (((v) & 0x7) << 0)
61
62 #define RPC_DROPR 0x0018 /* R/W */
63 #define RPC_DROPR_OPD3(o) (((o) & 0xFF) << 24)
64 #define RPC_DROPR_OPD2(o) (((o) & 0xFF) << 16)
65 #define RPC_DROPR_OPD1(o) (((o) & 0xFF) << 8)
66 #define RPC_DROPR_OPD0(o) (((o) & 0xFF) << 0)
67
68 #define RPC_DRENR 0x001C /* R/W */
69 #define RPC_DRENR_CDB(o) (u32)((((o) & 0x3) << 30))
70 #define RPC_DRENR_OCDB(o) (((o) & 0x3) << 28)
71 #define RPC_DRENR_ADB(o) (((o) & 0x3) << 24)
72 #define RPC_DRENR_OPDB(o) (((o) & 0x3) << 20)
73 #define RPC_DRENR_SPIDB(o) (((o) & 0x3) << 16)
74 #define RPC_DRENR_DME BIT(15)
75 #define RPC_DRENR_CDE BIT(14)
76 #define RPC_DRENR_OCDE BIT(12)
77 #define RPC_DRENR_ADE(v) (((v) & 0xF) << 8)
78 #define RPC_DRENR_OPDE(v) (((v) & 0xF) << 4)
79
80 #define RPC_SMCR 0x0020 /* R/W */
81 #define RPC_SMCR_SSLKP BIT(8)
82 #define RPC_SMCR_SPIRE BIT(2)
83 #define RPC_SMCR_SPIWE BIT(1)
84 #define RPC_SMCR_SPIE BIT(0)
85
86 #define RPC_SMCMR 0x0024 /* R/W */
87 #define RPC_SMCMR_CMD(c) (((c) & 0xFF) << 16)
88 #define RPC_SMCMR_OCMD(c) (((c) & 0xFF) << 0)
89
90 #define RPC_SMADR 0x0028 /* R/W */
91 #define RPC_SMOPR 0x002C /* R/W */
92 #define RPC_SMOPR_OPD0(o) (((o) & 0xFF) << 0)
93 #define RPC_SMOPR_OPD1(o) (((o) & 0xFF) << 8)
94 #define RPC_SMOPR_OPD2(o) (((o) & 0xFF) << 16)
95 #define RPC_SMOPR_OPD3(o) (((o) & 0xFF) << 24)
96
97 #define RPC_SMENR 0x0030 /* R/W */
98 #define RPC_SMENR_CDB(o) (((o) & 0x3) << 30)
99 #define RPC_SMENR_OCDB(o) (((o) & 0x3) << 28)
100 #define RPC_SMENR_ADB(o) (((o) & 0x3) << 24)
101 #define RPC_SMENR_OPDB(o) (((o) & 0x3) << 20)
102 #define RPC_SMENR_SPIDB(o) (((o) & 0x3) << 16)
103 #define RPC_SMENR_DME BIT(15)
104 #define RPC_SMENR_CDE BIT(14)
105 #define RPC_SMENR_OCDE BIT(12)
106 #define RPC_SMENR_ADE(v) (((v) & 0xF) << 8)
107 #define RPC_SMENR_OPDE(v) (((v) & 0xF) << 4)
108 #define RPC_SMENR_SPIDE(v) (((v) & 0xF) << 0)
109
110 #define RPC_SMRDR0 0x0038 /* R */
111 #define RPC_SMRDR1 0x003C /* R */
112 #define RPC_SMWDR0 0x0040 /* R/W */
113 #define RPC_SMWDR1 0x0044 /* R/W */
114 #define RPC_CMNSR 0x0048 /* R */
115 #define RPC_CMNSR_SSLF BIT(1)
116 #define RPC_CMNSR_TEND BIT(0)
117
118 #define RPC_DRDMCR 0x0058 /* R/W */
119 #define RPC_DRDMCR_DMCYC(v) (((v) & 0xF) << 0)
120
121 #define RPC_DRDRENR 0x005C /* R/W */
122 #define RPC_DRDRENR_HYPE (0x5 << 12)
123 #define RPC_DRDRENR_ADDRE BIT(8)
124 #define RPC_DRDRENR_OPDRE BIT(4)
125 #define RPC_DRDRENR_DRDRE BIT(0)
126
127 #define RPC_SMDMCR 0x0060 /* R/W */
128 #define RPC_SMDMCR_DMCYC(v) (((v) & 0xF) << 0)
129
130 #define RPC_SMDRENR 0x0064 /* R/W */
131 #define RPC_SMDRENR_HYPE (0x5 << 12)
132 #define RPC_SMDRENR_ADDRE BIT(8)
133 #define RPC_SMDRENR_OPDRE BIT(4)
134 #define RPC_SMDRENR_SPIDRE BIT(0)
135
136 #define RPC_PHYCNT 0x007C /* R/W */
137 #define RPC_PHYCNT_CAL BIT(31)
138 #define PRC_PHYCNT_OCTA_AA BIT(22)
139 #define PRC_PHYCNT_OCTA_SA BIT(23)
140 #define PRC_PHYCNT_EXDS BIT(21)
141 #define RPC_PHYCNT_OCT BIT(20)
142 #define RPC_PHYCNT_STRTIM(v) (((v) & 0x7) << 15)
143 #define RPC_PHYCNT_WBUF2 BIT(4)
144 #define RPC_PHYCNT_WBUF BIT(2)
145 #define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0)
146
147 #define RPC_PHYINT 0x0088 /* R/W */
148 #define RPC_PHYINT_RSTEN BIT(18)
149 #define RPC_PHYINT_WPEN BIT(17)
150 #define RPC_PHYINT_INTEN BIT(16)
151 #define RPC_PHYINT_RST BIT(2)
152 #define RPC_PHYINT_WP BIT(1)
153 #define RPC_PHYINT_INT BIT(0)
154
155 #define RPC_WBUF 0x8000 /* R/W size=4/8/16/32/64Bytes */
156 #define RPC_WBUF_SIZE 0x100
157
158 DECLARE_GLOBAL_DATA_PTR;
159
160 struct rpc_spi_plat {
161 fdt_addr_t regs;
162 fdt_addr_t extr;
163 s32 freq; /* Default clock freq, -1 for none */
164 };
165
166 struct rpc_spi_priv {
167 fdt_addr_t regs;
168 fdt_addr_t extr;
169 struct clk clk;
170
171 u8 cmdcopy[8];
172 u32 cmdlen;
173 bool cmdstarted;
174 };
175
rpc_spi_wait_sslf(struct udevice * dev)176 static int rpc_spi_wait_sslf(struct udevice *dev)
177 {
178 struct rpc_spi_priv *priv = dev_get_priv(dev->parent);
179
180 return wait_for_bit_le32((void *)priv->regs + RPC_CMNSR, RPC_CMNSR_SSLF,
181 false, 1000, false);
182 }
183
rpc_spi_wait_tend(struct udevice * dev)184 static int rpc_spi_wait_tend(struct udevice *dev)
185 {
186 struct rpc_spi_priv *priv = dev_get_priv(dev->parent);
187
188 return wait_for_bit_le32((void *)priv->regs + RPC_CMNSR, RPC_CMNSR_TEND,
189 true, 1000, false);
190 }
191
rpc_spi_flush_read_cache(struct udevice * dev)192 static void rpc_spi_flush_read_cache(struct udevice *dev)
193 {
194 struct udevice *bus = dev->parent;
195 struct rpc_spi_priv *priv = dev_get_priv(bus);
196
197 /* Flush read cache */
198 writel(RPC_DRCR_SSLN | RPC_DRCR_RBURST(0x1f) |
199 RPC_DRCR_RCF | RPC_DRCR_RBE | RPC_DRCR_SSLE,
200 priv->regs + RPC_DRCR);
201 readl(priv->regs + RPC_DRCR);
202
203 }
204
rpc_spi_claim_bus(struct udevice * dev,bool manual)205 static int rpc_spi_claim_bus(struct udevice *dev, bool manual)
206 {
207 struct udevice *bus = dev->parent;
208 struct rpc_spi_priv *priv = dev_get_priv(bus);
209
210 /*
211 * NOTE: The 0x260 are undocumented bits, but they must be set.
212 * NOTE: On H3 ES1.x (not supported in mainline U-Boot), the
213 * RPC_PHYCNT_STRTIM shall be 0, while on newer parts, the
214 * RPC_PHYCNT_STRTIM shall be 6.
215 */
216 writel(RPC_PHYCNT_CAL | RPC_PHYCNT_STRTIM(6) | 0x260,
217 priv->regs + RPC_PHYCNT);
218 writel((manual ? RPC_CMNCR_MD : 0) | RPC_CMNCR_SFDE |
219 RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ | RPC_CMNCR_BSZ(0),
220 priv->regs + RPC_CMNCR);
221
222 writel(RPC_SSLDR_SPNDL(7) | RPC_SSLDR_SLNDL(7) |
223 RPC_SSLDR_SCKDL(7), priv->regs + RPC_SSLDR);
224
225 rpc_spi_flush_read_cache(dev);
226
227 return 0;
228 }
229
rpc_spi_release_bus(struct udevice * dev)230 static int rpc_spi_release_bus(struct udevice *dev)
231 {
232 struct udevice *bus = dev->parent;
233 struct rpc_spi_priv *priv = dev_get_priv(bus);
234
235 /* NOTE: The 0x260 are undocumented bits, but they must be set. */
236 writel(RPC_PHYCNT_STRTIM(6) | 0x260, priv->regs + RPC_PHYCNT);
237
238 rpc_spi_flush_read_cache(dev);
239
240 return 0;
241 }
242
rpc_spi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)243 static int rpc_spi_xfer(struct udevice *dev, unsigned int bitlen,
244 const void *dout, void *din, unsigned long flags)
245 {
246 struct udevice *bus = dev->parent;
247 struct rpc_spi_priv *priv = dev_get_priv(bus);
248 u32 wlen = dout ? (bitlen / 8) : 0;
249 u32 rlen = din ? (bitlen / 8) : 0;
250 u32 wloop = DIV_ROUND_UP(wlen, 4);
251 u32 smenr, smcr, offset;
252 int ret = 0;
253
254 if (!priv->cmdstarted) {
255 if (!wlen || rlen)
256 BUG();
257
258 memcpy(priv->cmdcopy, dout, wlen);
259 priv->cmdlen = wlen;
260
261 /* Command transfer start */
262 priv->cmdstarted = true;
263 if (!(flags & SPI_XFER_END))
264 return 0;
265 }
266
267 offset = (priv->cmdcopy[1] << 16) | (priv->cmdcopy[2] << 8) |
268 (priv->cmdcopy[3] << 0);
269
270 smenr = 0;
271
272 if (wlen || (!rlen && !wlen) || flags == SPI_XFER_ONCE) {
273 if (wlen && flags == SPI_XFER_END)
274 smenr = RPC_SMENR_SPIDE(0xf);
275
276 rpc_spi_claim_bus(dev, true);
277
278 writel(0, priv->regs + RPC_SMCR);
279
280 if (priv->cmdlen >= 1) { /* Command(1) */
281 writel(RPC_SMCMR_CMD(priv->cmdcopy[0]),
282 priv->regs + RPC_SMCMR);
283 smenr |= RPC_SMENR_CDE;
284 } else {
285 writel(0, priv->regs + RPC_SMCMR);
286 }
287
288 if (priv->cmdlen >= 4) { /* Address(3) */
289 writel(offset, priv->regs + RPC_SMADR);
290 smenr |= RPC_SMENR_ADE(7);
291 } else {
292 writel(0, priv->regs + RPC_SMADR);
293 }
294
295 if (priv->cmdlen >= 5) { /* Dummy(n) */
296 writel(8 * (priv->cmdlen - 4) - 1,
297 priv->regs + RPC_SMDMCR);
298 smenr |= RPC_SMENR_DME;
299 } else {
300 writel(0, priv->regs + RPC_SMDMCR);
301 }
302
303 writel(0, priv->regs + RPC_SMOPR);
304
305 writel(0, priv->regs + RPC_SMDRENR);
306
307 if (wlen && flags == SPI_XFER_END) {
308 u32 *datout = (u32 *)dout;
309
310 while (wloop--) {
311 smcr = RPC_SMCR_SPIWE | RPC_SMCR_SPIE;
312 if (wloop >= 1)
313 smcr |= RPC_SMCR_SSLKP;
314 writel(smenr, priv->regs + RPC_SMENR);
315 writel(*datout, priv->regs + RPC_SMWDR0);
316 writel(smcr, priv->regs + RPC_SMCR);
317 ret = rpc_spi_wait_tend(dev);
318 if (ret)
319 goto err;
320 datout++;
321 smenr = RPC_SMENR_SPIDE(0xf);
322 }
323
324 ret = rpc_spi_wait_sslf(dev);
325
326 } else {
327 writel(smenr, priv->regs + RPC_SMENR);
328 writel(RPC_SMCR_SPIE, priv->regs + RPC_SMCR);
329 ret = rpc_spi_wait_tend(dev);
330 }
331 } else { /* Read data only, using DRx ext access */
332 rpc_spi_claim_bus(dev, false);
333
334 if (priv->cmdlen >= 1) { /* Command(1) */
335 writel(RPC_DRCMR_CMD(priv->cmdcopy[0]),
336 priv->regs + RPC_DRCMR);
337 smenr |= RPC_DRENR_CDE;
338 } else {
339 writel(0, priv->regs + RPC_DRCMR);
340 }
341
342 if (priv->cmdlen >= 4) /* Address(3) */
343 smenr |= RPC_DRENR_ADE(7);
344
345 if (priv->cmdlen >= 5) { /* Dummy(n) */
346 writel(8 * (priv->cmdlen - 4) - 1,
347 priv->regs + RPC_DRDMCR);
348 smenr |= RPC_DRENR_DME;
349 } else {
350 writel(0, priv->regs + RPC_DRDMCR);
351 }
352
353 writel(0, priv->regs + RPC_DROPR);
354
355 writel(smenr, priv->regs + RPC_DRENR);
356
357 if (rlen)
358 memcpy_fromio(din, (void *)(priv->extr + offset), rlen);
359 else
360 readl(priv->extr); /* Dummy read */
361 }
362
363 err:
364 priv->cmdstarted = false;
365
366 rpc_spi_release_bus(dev);
367
368 return ret;
369 }
370
rpc_spi_set_speed(struct udevice * bus,uint speed)371 static int rpc_spi_set_speed(struct udevice *bus, uint speed)
372 {
373 /* This is a SPI NOR controller, do nothing. */
374 return 0;
375 }
376
rpc_spi_set_mode(struct udevice * bus,uint mode)377 static int rpc_spi_set_mode(struct udevice *bus, uint mode)
378 {
379 /* This is a SPI NOR controller, do nothing. */
380 return 0;
381 }
382
rpc_spi_bind(struct udevice * parent)383 static int rpc_spi_bind(struct udevice *parent)
384 {
385 const void *fdt = gd->fdt_blob;
386 ofnode node;
387 int ret, off;
388
389 /*
390 * Check if there are any SPI NOR child nodes, if so, bind as
391 * this controller will be operated in SPI mode.
392 */
393 dev_for_each_subnode(node, parent) {
394 off = ofnode_to_offset(node);
395
396 ret = fdt_node_check_compatible(fdt, off, "spi-flash");
397 if (!ret)
398 return 0;
399
400 ret = fdt_node_check_compatible(fdt, off, "jedec,spi-nor");
401 if (!ret)
402 return 0;
403 }
404
405 return -ENODEV;
406 }
407
rpc_spi_probe(struct udevice * dev)408 static int rpc_spi_probe(struct udevice *dev)
409 {
410 struct rpc_spi_plat *plat = dev_get_plat(dev);
411 struct rpc_spi_priv *priv = dev_get_priv(dev);
412
413 priv->regs = plat->regs;
414 priv->extr = plat->extr;
415 #if CONFIG_IS_ENABLED(CLK)
416 clk_enable(&priv->clk);
417 #endif
418 return 0;
419 }
420
rpc_spi_of_to_plat(struct udevice * bus)421 static int rpc_spi_of_to_plat(struct udevice *bus)
422 {
423 struct rpc_spi_plat *plat = dev_get_plat(bus);
424
425 plat->regs = dev_read_addr_index(bus, 0);
426 plat->extr = dev_read_addr_index(bus, 1);
427
428 #if CONFIG_IS_ENABLED(CLK)
429 struct rpc_spi_priv *priv = dev_get_priv(bus);
430 int ret;
431
432 ret = clk_get_by_index(bus, 0, &priv->clk);
433 if (ret < 0) {
434 printf("%s: Could not get clock for %s: %d\n",
435 __func__, bus->name, ret);
436 return ret;
437 }
438 #endif
439
440 plat->freq = dev_read_u32_default(bus, "spi-max-freq", 50000000);
441
442 return 0;
443 }
444
445 static const struct dm_spi_ops rpc_spi_ops = {
446 .xfer = rpc_spi_xfer,
447 .set_speed = rpc_spi_set_speed,
448 .set_mode = rpc_spi_set_mode,
449 };
450
451 static const struct udevice_id rpc_spi_ids[] = {
452 { .compatible = "renesas,rpc-r7s72100" },
453 { .compatible = "renesas,rpc-r8a7795" },
454 { .compatible = "renesas,rpc-r8a7796" },
455 { .compatible = "renesas,rpc-r8a77965" },
456 { .compatible = "renesas,rpc-r8a77970" },
457 { .compatible = "renesas,rpc-r8a77995" },
458 { .compatible = "renesas,rcar-gen3-rpc" },
459 { }
460 };
461
462 U_BOOT_DRIVER(rpc_spi) = {
463 .name = "rpc_spi",
464 .id = UCLASS_SPI,
465 .of_match = rpc_spi_ids,
466 .ops = &rpc_spi_ops,
467 .of_to_plat = rpc_spi_of_to_plat,
468 .plat_auto = sizeof(struct rpc_spi_plat),
469 .priv_auto = sizeof(struct rpc_spi_priv),
470 .bind = rpc_spi_bind,
471 .probe = rpc_spi_probe,
472 };
473