1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2 /*
3 * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
4 *
5 * Driver for STMicroelectronics Serial peripheral interface (SPI)
6 */
7
8 #define LOG_CATEGORY UCLASS_SPI
9
10 #include <common.h>
11 #include <clk.h>
12 #include <dm.h>
13 #include <errno.h>
14 #include <log.h>
15 #include <malloc.h>
16 #include <reset.h>
17 #include <spi.h>
18 #include <dm/device_compat.h>
19 #include <linux/bitops.h>
20 #include <linux/delay.h>
21
22 #include <asm/io.h>
23 #include <asm/gpio.h>
24 #include <linux/bitfield.h>
25 #include <linux/iopoll.h>
26
27 /* STM32 SPI registers */
28 #define STM32_SPI_CR1 0x00
29 #define STM32_SPI_CR2 0x04
30 #define STM32_SPI_CFG1 0x08
31 #define STM32_SPI_CFG2 0x0C
32 #define STM32_SPI_SR 0x14
33 #define STM32_SPI_IFCR 0x18
34 #define STM32_SPI_TXDR 0x20
35 #define STM32_SPI_RXDR 0x30
36 #define STM32_SPI_I2SCFGR 0x50
37
38 /* STM32_SPI_CR1 bit fields */
39 #define SPI_CR1_SPE BIT(0)
40 #define SPI_CR1_MASRX BIT(8)
41 #define SPI_CR1_CSTART BIT(9)
42 #define SPI_CR1_CSUSP BIT(10)
43 #define SPI_CR1_HDDIR BIT(11)
44 #define SPI_CR1_SSI BIT(12)
45
46 /* STM32_SPI_CR2 bit fields */
47 #define SPI_CR2_TSIZE GENMASK(15, 0)
48
49 /* STM32_SPI_CFG1 bit fields */
50 #define SPI_CFG1_DSIZE GENMASK(4, 0)
51 #define SPI_CFG1_DSIZE_MIN 3
52 #define SPI_CFG1_FTHLV_SHIFT 5
53 #define SPI_CFG1_FTHLV GENMASK(8, 5)
54 #define SPI_CFG1_MBR_SHIFT 28
55 #define SPI_CFG1_MBR GENMASK(30, 28)
56 #define SPI_CFG1_MBR_MIN 0
57 #define SPI_CFG1_MBR_MAX FIELD_GET(SPI_CFG1_MBR, SPI_CFG1_MBR)
58
59 /* STM32_SPI_CFG2 bit fields */
60 #define SPI_CFG2_COMM_SHIFT 17
61 #define SPI_CFG2_COMM GENMASK(18, 17)
62 #define SPI_CFG2_MASTER BIT(22)
63 #define SPI_CFG2_LSBFRST BIT(23)
64 #define SPI_CFG2_CPHA BIT(24)
65 #define SPI_CFG2_CPOL BIT(25)
66 #define SPI_CFG2_SSM BIT(26)
67 #define SPI_CFG2_AFCNTR BIT(31)
68
69 /* STM32_SPI_SR bit fields */
70 #define SPI_SR_RXP BIT(0)
71 #define SPI_SR_TXP BIT(1)
72 #define SPI_SR_EOT BIT(3)
73 #define SPI_SR_TXTF BIT(4)
74 #define SPI_SR_OVR BIT(6)
75 #define SPI_SR_SUSP BIT(11)
76 #define SPI_SR_RXPLVL_SHIFT 13
77 #define SPI_SR_RXPLVL GENMASK(14, 13)
78 #define SPI_SR_RXWNE BIT(15)
79
80 /* STM32_SPI_IFCR bit fields */
81 #define SPI_IFCR_ALL GENMASK(11, 3)
82
83 /* STM32_SPI_I2SCFGR bit fields */
84 #define SPI_I2SCFGR_I2SMOD BIT(0)
85
86 #define MAX_CS_COUNT 4
87
88 /* SPI Master Baud Rate min/max divisor */
89 #define STM32_MBR_DIV_MIN (2 << SPI_CFG1_MBR_MIN)
90 #define STM32_MBR_DIV_MAX (2 << SPI_CFG1_MBR_MAX)
91
92 #define STM32_SPI_TIMEOUT_US 100000
93
94 /* SPI Communication mode */
95 #define SPI_FULL_DUPLEX 0
96 #define SPI_SIMPLEX_TX 1
97 #define SPI_SIMPLEX_RX 2
98 #define SPI_HALF_DUPLEX 3
99
100 struct stm32_spi_priv {
101 void __iomem *base;
102 struct clk clk;
103 struct reset_ctl rst_ctl;
104 struct gpio_desc cs_gpios[MAX_CS_COUNT];
105 ulong bus_clk_rate;
106 unsigned int fifo_size;
107 unsigned int cur_bpw;
108 unsigned int cur_hz;
109 unsigned int cur_xferlen; /* current transfer length in bytes */
110 unsigned int tx_len; /* number of data to be written in bytes */
111 unsigned int rx_len; /* number of data to be read in bytes */
112 const void *tx_buf; /* data to be written, or NULL */
113 void *rx_buf; /* data to be read, or NULL */
114 u32 cur_mode;
115 bool cs_high;
116 };
117
stm32_spi_write_txfifo(struct stm32_spi_priv * priv)118 static void stm32_spi_write_txfifo(struct stm32_spi_priv *priv)
119 {
120 while ((priv->tx_len > 0) &&
121 (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)) {
122 u32 offs = priv->cur_xferlen - priv->tx_len;
123
124 if (priv->tx_len >= sizeof(u32) &&
125 IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u32))) {
126 const u32 *tx_buf32 = (const u32 *)(priv->tx_buf + offs);
127
128 writel(*tx_buf32, priv->base + STM32_SPI_TXDR);
129 priv->tx_len -= sizeof(u32);
130 } else if (priv->tx_len >= sizeof(u16) &&
131 IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u16))) {
132 const u16 *tx_buf16 = (const u16 *)(priv->tx_buf + offs);
133
134 writew(*tx_buf16, priv->base + STM32_SPI_TXDR);
135 priv->tx_len -= sizeof(u16);
136 } else {
137 const u8 *tx_buf8 = (const u8 *)(priv->tx_buf + offs);
138
139 writeb(*tx_buf8, priv->base + STM32_SPI_TXDR);
140 priv->tx_len -= sizeof(u8);
141 }
142 }
143
144 log_debug("%d bytes left\n", priv->tx_len);
145 }
146
stm32_spi_read_rxfifo(struct stm32_spi_priv * priv)147 static void stm32_spi_read_rxfifo(struct stm32_spi_priv *priv)
148 {
149 u32 sr = readl(priv->base + STM32_SPI_SR);
150 u32 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
151
152 while ((priv->rx_len > 0) &&
153 ((sr & SPI_SR_RXP) ||
154 ((sr & SPI_SR_EOT) && ((sr & SPI_SR_RXWNE) || (rxplvl > 0))))) {
155 u32 offs = priv->cur_xferlen - priv->rx_len;
156
157 if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u32)) &&
158 (priv->rx_len >= sizeof(u32) || (sr & SPI_SR_RXWNE))) {
159 u32 *rx_buf32 = (u32 *)(priv->rx_buf + offs);
160
161 *rx_buf32 = readl(priv->base + STM32_SPI_RXDR);
162 priv->rx_len -= sizeof(u32);
163 } else if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u16)) &&
164 (priv->rx_len >= sizeof(u16) ||
165 (!(sr & SPI_SR_RXWNE) &&
166 (rxplvl >= 2 || priv->cur_bpw > 8)))) {
167 u16 *rx_buf16 = (u16 *)(priv->rx_buf + offs);
168
169 *rx_buf16 = readw(priv->base + STM32_SPI_RXDR);
170 priv->rx_len -= sizeof(u16);
171 } else {
172 u8 *rx_buf8 = (u8 *)(priv->rx_buf + offs);
173
174 *rx_buf8 = readb(priv->base + STM32_SPI_RXDR);
175 priv->rx_len -= sizeof(u8);
176 }
177
178 sr = readl(priv->base + STM32_SPI_SR);
179 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
180 }
181
182 log_debug("%d bytes left\n", priv->rx_len);
183 }
184
stm32_spi_enable(struct stm32_spi_priv * priv)185 static int stm32_spi_enable(struct stm32_spi_priv *priv)
186 {
187 log_debug("\n");
188
189 /* Enable the SPI hardware */
190 setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
191
192 return 0;
193 }
194
stm32_spi_disable(struct stm32_spi_priv * priv)195 static int stm32_spi_disable(struct stm32_spi_priv *priv)
196 {
197 log_debug("\n");
198
199 /* Disable the SPI hardware */
200 clrbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
201
202 return 0;
203 }
204
stm32_spi_claim_bus(struct udevice * slave)205 static int stm32_spi_claim_bus(struct udevice *slave)
206 {
207 struct udevice *bus = dev_get_parent(slave);
208 struct stm32_spi_priv *priv = dev_get_priv(bus);
209
210 dev_dbg(slave, "\n");
211
212 /* Enable the SPI hardware */
213 return stm32_spi_enable(priv);
214 }
215
stm32_spi_release_bus(struct udevice * slave)216 static int stm32_spi_release_bus(struct udevice *slave)
217 {
218 struct udevice *bus = dev_get_parent(slave);
219 struct stm32_spi_priv *priv = dev_get_priv(bus);
220
221 dev_dbg(slave, "\n");
222
223 /* Disable the SPI hardware */
224 return stm32_spi_disable(priv);
225 }
226
stm32_spi_stopxfer(struct udevice * dev)227 static void stm32_spi_stopxfer(struct udevice *dev)
228 {
229 struct stm32_spi_priv *priv = dev_get_priv(dev);
230 u32 cr1, sr;
231 int ret;
232
233 dev_dbg(dev, "\n");
234
235 cr1 = readl(priv->base + STM32_SPI_CR1);
236
237 if (!(cr1 & SPI_CR1_SPE))
238 return;
239
240 /* Wait on EOT or suspend the flow */
241 ret = readl_poll_timeout(priv->base + STM32_SPI_SR, sr,
242 !(sr & SPI_SR_EOT), 100000);
243 if (ret < 0) {
244 if (cr1 & SPI_CR1_CSTART) {
245 writel(cr1 | SPI_CR1_CSUSP, priv->base + STM32_SPI_CR1);
246 if (readl_poll_timeout(priv->base + STM32_SPI_SR,
247 sr, !(sr & SPI_SR_SUSP),
248 100000) < 0)
249 dev_err(dev, "Suspend request timeout\n");
250 }
251 }
252
253 /* clear status flags */
254 setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL);
255 }
256
stm32_spi_set_cs(struct udevice * dev,unsigned int cs,bool enable)257 static int stm32_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable)
258 {
259 struct stm32_spi_priv *priv = dev_get_priv(dev);
260
261 dev_dbg(dev, "cs=%d enable=%d\n", cs, enable);
262
263 if (cs >= MAX_CS_COUNT)
264 return -ENODEV;
265
266 if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
267 return -EINVAL;
268
269 if (priv->cs_high)
270 enable = !enable;
271
272 return dm_gpio_set_value(&priv->cs_gpios[cs], enable ? 1 : 0);
273 }
274
stm32_spi_set_mode(struct udevice * bus,uint mode)275 static int stm32_spi_set_mode(struct udevice *bus, uint mode)
276 {
277 struct stm32_spi_priv *priv = dev_get_priv(bus);
278 u32 cfg2_clrb = 0, cfg2_setb = 0;
279
280 dev_dbg(bus, "mode=%d\n", mode);
281
282 if (mode & SPI_CPOL)
283 cfg2_setb |= SPI_CFG2_CPOL;
284 else
285 cfg2_clrb |= SPI_CFG2_CPOL;
286
287 if (mode & SPI_CPHA)
288 cfg2_setb |= SPI_CFG2_CPHA;
289 else
290 cfg2_clrb |= SPI_CFG2_CPHA;
291
292 if (mode & SPI_LSB_FIRST)
293 cfg2_setb |= SPI_CFG2_LSBFRST;
294 else
295 cfg2_clrb |= SPI_CFG2_LSBFRST;
296
297 if (cfg2_clrb || cfg2_setb)
298 clrsetbits_le32(priv->base + STM32_SPI_CFG2,
299 cfg2_clrb, cfg2_setb);
300
301 if (mode & SPI_CS_HIGH)
302 priv->cs_high = true;
303 else
304 priv->cs_high = false;
305 return 0;
306 }
307
stm32_spi_set_fthlv(struct udevice * dev,u32 xfer_len)308 static int stm32_spi_set_fthlv(struct udevice *dev, u32 xfer_len)
309 {
310 struct stm32_spi_priv *priv = dev_get_priv(dev);
311 u32 fthlv, half_fifo;
312
313 /* data packet should not exceed 1/2 of fifo space */
314 half_fifo = (priv->fifo_size / 2);
315
316 /* data_packet should not exceed transfer length */
317 fthlv = (half_fifo > xfer_len) ? xfer_len : half_fifo;
318
319 /* align packet size with data registers access */
320 fthlv -= (fthlv % 4);
321
322 if (!fthlv)
323 fthlv = 1;
324 clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_FTHLV,
325 (fthlv - 1) << SPI_CFG1_FTHLV_SHIFT);
326
327 return 0;
328 }
329
stm32_spi_set_speed(struct udevice * bus,uint hz)330 static int stm32_spi_set_speed(struct udevice *bus, uint hz)
331 {
332 struct stm32_spi_priv *priv = dev_get_priv(bus);
333 u32 mbrdiv;
334 long div;
335
336 dev_dbg(bus, "hz=%d\n", hz);
337
338 if (priv->cur_hz == hz)
339 return 0;
340
341 div = DIV_ROUND_UP(priv->bus_clk_rate, hz);
342
343 if (div < STM32_MBR_DIV_MIN ||
344 div > STM32_MBR_DIV_MAX)
345 return -EINVAL;
346
347 /* Determine the first power of 2 greater than or equal to div */
348 if (div & (div - 1))
349 mbrdiv = fls(div);
350 else
351 mbrdiv = fls(div) - 1;
352
353 if (!mbrdiv)
354 return -EINVAL;
355
356 clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_MBR,
357 (mbrdiv - 1) << SPI_CFG1_MBR_SHIFT);
358
359 priv->cur_hz = hz;
360
361 return 0;
362 }
363
stm32_spi_xfer(struct udevice * slave,unsigned int bitlen,const void * dout,void * din,unsigned long flags)364 static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen,
365 const void *dout, void *din, unsigned long flags)
366 {
367 struct udevice *bus = dev_get_parent(slave);
368 struct dm_spi_slave_plat *slave_plat;
369 struct stm32_spi_priv *priv = dev_get_priv(bus);
370 u32 sr;
371 u32 ifcr = 0;
372 u32 xferlen;
373 u32 mode;
374 int xfer_status = 0;
375
376 xferlen = bitlen / 8;
377
378 if (xferlen <= SPI_CR2_TSIZE)
379 writel(xferlen, priv->base + STM32_SPI_CR2);
380 else
381 return -EMSGSIZE;
382
383 priv->tx_buf = dout;
384 priv->rx_buf = din;
385 priv->tx_len = priv->tx_buf ? bitlen / 8 : 0;
386 priv->rx_len = priv->rx_buf ? bitlen / 8 : 0;
387
388 mode = SPI_FULL_DUPLEX;
389 if (!priv->tx_buf)
390 mode = SPI_SIMPLEX_RX;
391 else if (!priv->rx_buf)
392 mode = SPI_SIMPLEX_TX;
393
394 if (priv->cur_xferlen != xferlen || priv->cur_mode != mode) {
395 priv->cur_mode = mode;
396 priv->cur_xferlen = xferlen;
397
398 /* Disable the SPI hardware to unlock CFG1/CFG2 registers */
399 stm32_spi_disable(priv);
400
401 clrsetbits_le32(priv->base + STM32_SPI_CFG2, SPI_CFG2_COMM,
402 mode << SPI_CFG2_COMM_SHIFT);
403
404 stm32_spi_set_fthlv(bus, xferlen);
405
406 /* Enable the SPI hardware */
407 stm32_spi_enable(priv);
408 }
409
410 dev_dbg(bus, "priv->tx_len=%d priv->rx_len=%d\n",
411 priv->tx_len, priv->rx_len);
412
413 slave_plat = dev_get_parent_plat(slave);
414 if (flags & SPI_XFER_BEGIN)
415 stm32_spi_set_cs(bus, slave_plat->cs, false);
416
417 /* Be sure to have data in fifo before starting data transfer */
418 if (priv->tx_buf)
419 stm32_spi_write_txfifo(priv);
420
421 setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_CSTART);
422
423 while (1) {
424 sr = readl(priv->base + STM32_SPI_SR);
425
426 if (sr & SPI_SR_OVR) {
427 dev_err(bus, "Overrun: RX data lost\n");
428 xfer_status = -EIO;
429 break;
430 }
431
432 if (sr & SPI_SR_SUSP) {
433 dev_warn(bus, "System too slow is limiting data throughput\n");
434
435 if (priv->rx_buf && priv->rx_len > 0)
436 stm32_spi_read_rxfifo(priv);
437
438 ifcr |= SPI_SR_SUSP;
439 }
440
441 if (sr & SPI_SR_TXTF)
442 ifcr |= SPI_SR_TXTF;
443
444 if (sr & SPI_SR_TXP)
445 if (priv->tx_buf && priv->tx_len > 0)
446 stm32_spi_write_txfifo(priv);
447
448 if (sr & SPI_SR_RXP)
449 if (priv->rx_buf && priv->rx_len > 0)
450 stm32_spi_read_rxfifo(priv);
451
452 if (sr & SPI_SR_EOT) {
453 if (priv->rx_buf && priv->rx_len > 0)
454 stm32_spi_read_rxfifo(priv);
455 break;
456 }
457
458 writel(ifcr, priv->base + STM32_SPI_IFCR);
459 }
460
461 /* clear status flags */
462 setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL);
463 stm32_spi_stopxfer(bus);
464
465 if (flags & SPI_XFER_END)
466 stm32_spi_set_cs(bus, slave_plat->cs, true);
467
468 return xfer_status;
469 }
470
stm32_spi_get_fifo_size(struct udevice * dev)471 static int stm32_spi_get_fifo_size(struct udevice *dev)
472 {
473 struct stm32_spi_priv *priv = dev_get_priv(dev);
474 u32 count = 0;
475
476 stm32_spi_enable(priv);
477
478 while (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)
479 writeb(++count, priv->base + STM32_SPI_TXDR);
480
481 stm32_spi_disable(priv);
482
483 dev_dbg(dev, "%d x 8-bit fifo size\n", count);
484
485 return count;
486 }
487
stm32_spi_probe(struct udevice * dev)488 static int stm32_spi_probe(struct udevice *dev)
489 {
490 struct stm32_spi_priv *priv = dev_get_priv(dev);
491 unsigned long clk_rate;
492 int ret;
493 unsigned int i;
494
495 priv->base = dev_remap_addr(dev);
496 if (!priv->base)
497 return -EINVAL;
498
499 /* enable clock */
500 ret = clk_get_by_index(dev, 0, &priv->clk);
501 if (ret < 0)
502 return ret;
503
504 ret = clk_enable(&priv->clk);
505 if (ret < 0)
506 return ret;
507
508 clk_rate = clk_get_rate(&priv->clk);
509 if (!clk_rate) {
510 ret = -EINVAL;
511 goto clk_err;
512 }
513
514 priv->bus_clk_rate = clk_rate;
515
516 /* perform reset */
517 ret = reset_get_by_index(dev, 0, &priv->rst_ctl);
518 if (ret < 0)
519 goto clk_err;
520
521 reset_assert(&priv->rst_ctl);
522 udelay(2);
523 reset_deassert(&priv->rst_ctl);
524
525 ret = gpio_request_list_by_name(dev, "cs-gpios", priv->cs_gpios,
526 ARRAY_SIZE(priv->cs_gpios), 0);
527 if (ret < 0) {
528 dev_err(dev, "Can't get cs gpios: %d", ret);
529 goto reset_err;
530 }
531
532 priv->fifo_size = stm32_spi_get_fifo_size(dev);
533
534 priv->cur_mode = SPI_FULL_DUPLEX;
535 priv->cur_xferlen = 0;
536 priv->cur_bpw = SPI_DEFAULT_WORDLEN;
537 clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_DSIZE,
538 priv->cur_bpw - 1);
539
540 for (i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) {
541 if (!dm_gpio_is_valid(&priv->cs_gpios[i]))
542 continue;
543
544 dm_gpio_set_dir_flags(&priv->cs_gpios[i],
545 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
546 }
547
548 /* Ensure I2SMOD bit is kept cleared */
549 clrbits_le32(priv->base + STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD);
550
551 /*
552 * - SS input value high
553 * - transmitter half duplex direction
554 * - automatic communication suspend when RX-Fifo is full
555 */
556 setbits_le32(priv->base + STM32_SPI_CR1,
557 SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX);
558
559 /*
560 * - Set the master mode (default Motorola mode)
561 * - Consider 1 master/n slaves configuration and
562 * SS input value is determined by the SSI bit
563 * - keep control of all associated GPIOs
564 */
565 setbits_le32(priv->base + STM32_SPI_CFG2,
566 SPI_CFG2_MASTER | SPI_CFG2_SSM | SPI_CFG2_AFCNTR);
567
568 return 0;
569
570 reset_err:
571 reset_free(&priv->rst_ctl);
572
573 clk_err:
574 clk_disable(&priv->clk);
575 clk_free(&priv->clk);
576
577 return ret;
578 };
579
stm32_spi_remove(struct udevice * dev)580 static int stm32_spi_remove(struct udevice *dev)
581 {
582 struct stm32_spi_priv *priv = dev_get_priv(dev);
583 int ret;
584
585 stm32_spi_stopxfer(dev);
586 stm32_spi_disable(priv);
587
588 ret = reset_assert(&priv->rst_ctl);
589 if (ret < 0)
590 return ret;
591
592 reset_free(&priv->rst_ctl);
593
594 ret = clk_disable(&priv->clk);
595 if (ret < 0)
596 return ret;
597
598 clk_free(&priv->clk);
599
600 return ret;
601 };
602
603 static const struct dm_spi_ops stm32_spi_ops = {
604 .claim_bus = stm32_spi_claim_bus,
605 .release_bus = stm32_spi_release_bus,
606 .set_mode = stm32_spi_set_mode,
607 .set_speed = stm32_spi_set_speed,
608 .xfer = stm32_spi_xfer,
609 };
610
611 static const struct udevice_id stm32_spi_ids[] = {
612 { .compatible = "st,stm32h7-spi", },
613 { }
614 };
615
616 U_BOOT_DRIVER(stm32_spi) = {
617 .name = "stm32_spi",
618 .id = UCLASS_SPI,
619 .of_match = stm32_spi_ids,
620 .ops = &stm32_spi_ops,
621 .priv_auto = sizeof(struct stm32_spi_priv),
622 .probe = stm32_spi_probe,
623 .remove = stm32_spi_remove,
624 };
625