1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2020 Cortina-Access
4 *
5 * GPIO Driver for Cortina Access CAxxxx Line of SoCs
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <log.h>
11 #include <asm/io.h>
12 #include <asm/gpio.h>
13 #include <linux/bitops.h>
14 #include <linux/compat.h>
15 #include <linux/compiler.h>
16
17 /* GPIO Register Map */
18 #define CORTINA_GPIO_CFG 0x00
19 #define CORTINA_GPIO_OUT 0x04
20 #define CORTINA_GPIO_IN 0x08
21 #define CORTINA_GPIO_LVL 0x0C
22 #define CORTINA_GPIO_EDGE 0x10
23 #define CORTINA_GPIO_BOTHEDGE 0x14
24 #define CORTINA_GPIO_IE 0x18
25 #define CORTINA_GPIO_INT 0x1C
26 #define CORTINA_GPIO_STAT 0x20
27
28 struct cortina_gpio_bank {
29 void __iomem *base;
30 };
31
32 #ifdef CONFIG_DM_GPIO
ca_gpio_direction_input(struct udevice * dev,unsigned int offset)33 static int ca_gpio_direction_input(struct udevice *dev, unsigned int offset)
34 {
35 struct cortina_gpio_bank *priv = dev_get_priv(dev);
36
37 setbits_32(priv->base, BIT(offset));
38 return 0;
39 }
40
41 static int
ca_gpio_direction_output(struct udevice * dev,unsigned int offset,int value)42 ca_gpio_direction_output(struct udevice *dev, unsigned int offset, int value)
43 {
44 struct cortina_gpio_bank *priv = dev_get_priv(dev);
45
46 clrbits_32(priv->base, BIT(offset));
47 return 0;
48 }
49
ca_gpio_get_value(struct udevice * dev,unsigned int offset)50 static int ca_gpio_get_value(struct udevice *dev, unsigned int offset)
51 {
52 struct cortina_gpio_bank *priv = dev_get_priv(dev);
53
54 return readl(priv->base + CORTINA_GPIO_IN) & BIT(offset);
55 }
56
ca_gpio_set_value(struct udevice * dev,unsigned int offset,int value)57 static int ca_gpio_set_value(struct udevice *dev, unsigned int offset,
58 int value)
59 {
60 struct cortina_gpio_bank *priv = dev_get_priv(dev);
61
62 setbits_32(priv->base + CORTINA_GPIO_OUT, BIT(offset));
63 return 0;
64 }
65
ca_gpio_get_function(struct udevice * dev,unsigned int offset)66 static int ca_gpio_get_function(struct udevice *dev, unsigned int offset)
67 {
68 struct cortina_gpio_bank *priv = dev_get_priv(dev);
69
70 if (readl(priv->base) & BIT(offset))
71 return GPIOF_INPUT;
72 else
73 return GPIOF_OUTPUT;
74 }
75
76 static const struct dm_gpio_ops gpio_cortina_ops = {
77 .direction_input = ca_gpio_direction_input,
78 .direction_output = ca_gpio_direction_output,
79 .get_value = ca_gpio_get_value,
80 .set_value = ca_gpio_set_value,
81 .get_function = ca_gpio_get_function,
82 };
83
ca_gpio_probe(struct udevice * dev)84 static int ca_gpio_probe(struct udevice *dev)
85 {
86 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
87 struct cortina_gpio_bank *priv = dev_get_priv(dev);
88
89 priv->base = dev_remap_addr_index(dev, 0);
90 if (!priv->base)
91 return -EINVAL;
92
93 uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios", 32);
94 uc_priv->bank_name = dev->name;
95
96 debug("Done Cortina GPIO init\n");
97 return 0;
98 }
99
100 static const struct udevice_id ca_gpio_ids[] = {
101 {.compatible = "cortina,ca-gpio"},
102 {}
103 };
104
105 U_BOOT_DRIVER(cortina_gpio) = {
106 .name = "cortina-gpio",
107 .id = UCLASS_GPIO,
108 .ops = &gpio_cortina_ops,
109 .probe = ca_gpio_probe,
110 .priv_auto = sizeof(struct cortina_gpio_bank),
111 .of_match = ca_gpio_ids,
112 };
113 #endif /* CONFIG_DM_GPIO */
114