1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2012 The Chromium OS Authors.
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <errno.h>
9 #include <fdtdec.h>
10 #include <log.h>
11 #include <pch.h>
12 #include <pci.h>
13 #include <syscon.h>
14 #include <asm/cpu.h>
15 #include <asm/global_data.h>
16 #include <asm/gpio.h>
17 #include <asm/io.h>
18 #include <asm/pci.h>
19 #include <asm/arch/gpio.h>
20 #include <dt-bindings/gpio/x86-gpio.h>
21
22 DECLARE_GLOBAL_DATA_PTR;
23
24 /**
25 * struct broadwell_bank_priv - Private driver data
26 *
27 * @regs: Pointer to GPIO registers
28 * @bank: Bank number for this bank (0, 1 or 2)
29 * @offset: GPIO offset for this bank (0, 32 or 64)
30 */
31 struct broadwell_bank_priv {
32 struct pch_lp_gpio_regs *regs;
33 int bank;
34 int offset;
35 };
36
broadwell_gpio_request(struct udevice * dev,unsigned offset,const char * label)37 static int broadwell_gpio_request(struct udevice *dev, unsigned offset,
38 const char *label)
39 {
40 struct broadwell_bank_priv *priv = dev_get_priv(dev);
41 struct pch_lp_gpio_regs *regs = priv->regs;
42 u32 val;
43
44 /*
45 * Make sure that the GPIO pin we want isn't already in use for some
46 * built-in hardware function. We have to check this for every
47 * requested pin.
48 */
49 debug("%s: request bank %d offset %d: ", __func__, priv->bank, offset);
50 val = inl(®s->own[priv->bank]);
51 if (!(val & (1UL << offset))) {
52 debug("gpio is reserved for internal use\n");
53 return -EPERM;
54 }
55 debug("ok\n");
56
57 return 0;
58 }
59
broadwell_gpio_direction_input(struct udevice * dev,unsigned offset)60 static int broadwell_gpio_direction_input(struct udevice *dev, unsigned offset)
61 {
62 struct broadwell_bank_priv *priv = dev_get_priv(dev);
63 struct pch_lp_gpio_regs *regs = priv->regs;
64
65 setio_32(®s->config[priv->offset + offset], CONFA_DIR_INPUT);
66
67 return 0;
68 }
69
broadwell_gpio_get_value(struct udevice * dev,unsigned offset)70 static int broadwell_gpio_get_value(struct udevice *dev, unsigned offset)
71 {
72 struct broadwell_bank_priv *priv = dev_get_priv(dev);
73 struct pch_lp_gpio_regs *regs = priv->regs;
74
75 return inl(®s->config[priv->offset + offset]) & CONFA_LEVEL_HIGH ?
76 1 : 0;
77 }
78
broadwell_gpio_set_value(struct udevice * dev,unsigned offset,int value)79 static int broadwell_gpio_set_value(struct udevice *dev, unsigned offset,
80 int value)
81 {
82 struct broadwell_bank_priv *priv = dev_get_priv(dev);
83 struct pch_lp_gpio_regs *regs = priv->regs;
84
85 debug("%s: dev=%s, offset=%d, value=%d\n", __func__, dev->name, offset,
86 value);
87 clrsetio_32(®s->config[priv->offset + offset], CONFA_OUTPUT_HIGH,
88 value ? CONFA_OUTPUT_HIGH : 0);
89
90 return 0;
91 }
92
broadwell_gpio_direction_output(struct udevice * dev,unsigned offset,int value)93 static int broadwell_gpio_direction_output(struct udevice *dev, unsigned offset,
94 int value)
95 {
96 struct broadwell_bank_priv *priv = dev_get_priv(dev);
97 struct pch_lp_gpio_regs *regs = priv->regs;
98
99 broadwell_gpio_set_value(dev, offset, value);
100 clrio_32(®s->config[priv->offset + offset], CONFA_DIR_INPUT);
101
102 return 0;
103 }
104
broadwell_gpio_get_function(struct udevice * dev,unsigned offset)105 static int broadwell_gpio_get_function(struct udevice *dev, unsigned offset)
106 {
107 struct broadwell_bank_priv *priv = dev_get_priv(dev);
108 struct pch_lp_gpio_regs *regs = priv->regs;
109 u32 mask = 1UL << offset;
110
111 if (!(inl(®s->own[priv->bank]) & mask))
112 return GPIOF_FUNC;
113 if (inl(®s->config[priv->offset + offset]) & CONFA_DIR_INPUT)
114 return GPIOF_INPUT;
115 else
116 return GPIOF_OUTPUT;
117 }
118
broadwell_gpio_probe(struct udevice * dev)119 static int broadwell_gpio_probe(struct udevice *dev)
120 {
121 struct broadwell_bank_plat *plat = dev_get_plat(dev);
122 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
123 struct broadwell_bank_priv *priv = dev_get_priv(dev);
124 struct udevice *pinctrl;
125 int ret;
126
127 /* Set up pin control if available */
128 ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl);
129 debug("%s, pinctrl=%p, ret=%d\n", __func__, pinctrl, ret);
130
131 uc_priv->gpio_count = GPIO_PER_BANK;
132 uc_priv->bank_name = plat->bank_name;
133
134 priv->regs = (struct pch_lp_gpio_regs *)(uintptr_t)plat->base_addr;
135 priv->bank = plat->bank;
136 priv->offset = priv->bank * 32;
137 debug("%s: probe done, regs %p, bank %d\n", __func__, priv->regs,
138 priv->bank);
139
140 return 0;
141 }
142
broadwell_gpio_of_to_plat(struct udevice * dev)143 static int broadwell_gpio_of_to_plat(struct udevice *dev)
144 {
145 struct broadwell_bank_plat *plat = dev_get_plat(dev);
146 u32 gpiobase;
147 int bank;
148 int ret;
149
150 ret = pch_get_gpio_base(dev->parent, &gpiobase);
151 if (ret)
152 return ret;
153
154 bank = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1);
155 if (bank == -1) {
156 debug("%s: Invalid bank number %d\n", __func__, bank);
157 return -EINVAL;
158 }
159 plat->bank = bank;
160 plat->base_addr = gpiobase;
161 plat->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
162 "bank-name", NULL);
163
164 return 0;
165 }
166
167 static const struct dm_gpio_ops gpio_broadwell_ops = {
168 .request = broadwell_gpio_request,
169 .direction_input = broadwell_gpio_direction_input,
170 .direction_output = broadwell_gpio_direction_output,
171 .get_value = broadwell_gpio_get_value,
172 .set_value = broadwell_gpio_set_value,
173 .get_function = broadwell_gpio_get_function,
174 };
175
176 static const struct udevice_id intel_broadwell_gpio_ids[] = {
177 { .compatible = "intel,broadwell-gpio" },
178 { }
179 };
180
181 U_BOOT_DRIVER(gpio_broadwell) = {
182 .name = "gpio_broadwell",
183 .id = UCLASS_GPIO,
184 .of_match = intel_broadwell_gpio_ids,
185 .ops = &gpio_broadwell_ops,
186 .of_to_plat = broadwell_gpio_of_to_plat,
187 .probe = broadwell_gpio_probe,
188 .priv_auto = sizeof(struct broadwell_bank_priv),
189 .plat_auto = sizeof(struct broadwell_bank_plat),
190 };
191