1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2015 Google, Inc 4 * Copyright 2014 Rockchip Inc. 5 */ 6 7 #ifndef _ASM_ARCH_EDP_H 8 #define _ASM_ARCH_EDP_H 9 10 struct rk3288_edp { 11 u8 res0[0x10]; 12 u32 dp_tx_version; 13 u8 res1[0x4]; 14 u32 func_en_1; 15 u32 func_en_2; 16 u32 video_ctl_1; 17 u32 video_ctl_2; 18 u32 video_ctl_3; 19 u32 video_ctl_4; 20 u8 res2[0xc]; 21 u32 video_ctl_8; 22 u8 res3[0x4]; 23 u32 video_ctl_10; 24 u32 total_line_l; 25 u32 total_line_h; 26 u32 active_line_l; 27 u32 active_line_h; 28 u32 v_f_porch; 29 u32 vsync; 30 u32 v_b_porch; 31 u32 total_pixel_l; 32 u32 total_pixel_h; 33 u32 active_pixel_l; 34 u32 active_pixel_h; 35 u32 h_f_porch_l; 36 u32 h_f_porch_h; 37 u32 hsync_l; 38 u32 hysnc_h; 39 u32 h_b_porch_l; 40 u32 h_b_porch_h; 41 u32 vid_status; 42 u32 total_line_sta_l; 43 u32 total_line_sta_h; 44 u32 active_line_sta_l; 45 u32 active_line_sta_h; 46 u32 v_f_porch_sta; 47 u32 vsync_sta; 48 u32 v_b_porch_sta; 49 u32 total_pixel_sta_l; 50 u32 total_pixel_sta_h; 51 u32 active_pixel_sta_l; 52 u32 active_pixel_sta_h; 53 u32 h_f_porch_sta_l; 54 u32 h_f_porch_sta_h; 55 u32 hsync_sta_l; 56 u32 hsync_sta_h; 57 u32 h_b_porch_sta_l; 58 u32 h_b_porch__sta_h; 59 u8 res4[0x28]; 60 u32 pll_reg_1; 61 u8 res5[4]; 62 u32 ssc_reg; 63 u8 res6[0xc]; 64 u32 tx_common; 65 u32 tx_common2; 66 u8 res7[0x4]; 67 u32 dp_aux; 68 u32 dp_bias; 69 u32 dp_test; 70 u32 dp_pd; 71 u32 dp_reserv1; 72 u32 dp_reserv2; 73 u8 res8[0x224]; 74 u32 lane_map; 75 u8 res9[0x14]; 76 u32 analog_ctl_2; 77 u8 res10[0x48]; 78 u32 int_state; 79 u32 common_int_sta_1; 80 u32 common_int_sta_2; 81 u32 common_int_sta_3; 82 u32 common_int_sta_4; 83 u32 spdif_biphase_int_sta; 84 u8 res11[0x4]; 85 u32 dp_int_sta; 86 u32 common_int_mask_1; 87 u32 common_int_mask_2; 88 u32 common_int_mask_3; 89 u32 common_int_mask_4; 90 u8 res12[0x08]; 91 u32 int_sta_mask; 92 u32 int_ctl; 93 u8 res13[0x200]; 94 u32 sys_ctl_1; 95 u32 sys_ctl_2; 96 u32 sys_ctl_3; 97 u32 sys_ctl_4; 98 u32 dp_vid_ctl; 99 u8 res14[0x4]; 100 u32 dp_aud_ctl; 101 u8 res15[0x24]; 102 u32 pkt_send_ctl; 103 u8 res16[0x4]; 104 u32 dp_hdcp_ctl; 105 u8 res17[0x34]; 106 u32 link_bw_set; 107 u32 lane_count_set; 108 u32 dp_training_ptn_set; 109 u32 ln_link_trn_ctl[4]; 110 u8 res18[0x4]; 111 u32 dp_hw_link_training; 112 u8 res19[0x1c]; 113 u32 dp_debug_ctl; 114 u32 hpd_deglitch_l; 115 u32 hpd_deglitch_h; 116 u8 res20[0x14]; 117 u32 dp_link_debug_ctl; 118 u8 res21[0x1c]; 119 u32 m_vid_0; 120 u32 m_vid_1; 121 u32 m_vid_2; 122 u32 n_vid_0; 123 u32 n_vid_1; 124 u32 n_vid_2; 125 u32 m_vid_mon; 126 u8 res22[0x14]; 127 u32 dp_video_fifo_thrd; 128 u8 res23[0x8]; 129 u32 dp_audio_margin; 130 u8 res24[0x20]; 131 u32 dp_m_cal_ctl; 132 u32 m_vid_gen_filter_th; 133 u8 res25[0x10]; 134 u32 m_aud_gen_filter_th; 135 u8 res26[0x4]; 136 u32 aux_ch_sta; 137 u32 aux_err_num; 138 u32 aux_ch_defer_dtl; 139 u32 aux_rx_comm; 140 u32 buf_data_ctl; 141 u32 aux_ch_ctl_1; 142 u32 aux_addr_7_0; 143 u32 aux_addr_15_8; 144 u32 aux_addr_19_16; 145 u32 aux_ch_ctl_2; 146 u8 res27[0x18]; 147 u32 buf_data[16]; 148 u32 soc_general_ctl; 149 u8 res29[0x1e0]; 150 u32 pll_reg_2; 151 u32 pll_reg_3; 152 u32 pll_reg_4; 153 u8 res30[0x10]; 154 u32 pll_reg_5; 155 }; 156 check_member(rk3288_edp, pll_reg_5, 0xa00); 157 158 /* func_en_1 */ 159 #define VID_CAP_FUNC_EN_N (0x1 << 6) 160 #define VID_FIFO_FUNC_EN_N (0x1 << 5) 161 #define AUD_FIFO_FUNC_EN_N (0x1 << 4) 162 #define AUD_FUNC_EN_N (0x1 << 3) 163 #define HDCP_FUNC_EN_N (0x1 << 2) 164 #define SW_FUNC_EN_N (0x1 << 0) 165 166 /* func_en_2 */ 167 #define SSC_FUNC_EN_N (0x1 << 7) 168 #define AUX_FUNC_EN_N (0x1 << 2) 169 #define SERDES_FIFO_FUNC_EN_N (0x1 << 1) 170 #define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) 171 172 /* video_ctl_1 */ 173 #define VIDEO_EN (0x1 << 7) 174 #define VIDEO_MUTE (0x1 << 6) 175 176 /* video_ctl_2 */ 177 #define IN_D_RANGE_MASK (0x1 << 7) 178 #define IN_D_RANGE_SHIFT (7) 179 #define IN_D_RANGE_CEA (0x1 << 7) 180 #define IN_D_RANGE_VESA (0x0 << 7) 181 #define IN_BPC_MASK (0x7 << 4) 182 #define IN_BPC_SHIFT (4) 183 #define IN_BPC_12_BITS (0x3 << 4) 184 #define IN_BPC_10_BITS (0x2 << 4) 185 #define IN_BPC_8_BITS (0x1 << 4) 186 #define IN_BPC_6_BITS (0x0 << 4) 187 #define IN_COLOR_F_MASK (0x3 << 0) 188 #define IN_COLOR_F_SHIFT (0) 189 #define IN_COLOR_F_YCBCR444 (0x2 << 0) 190 #define IN_COLOR_F_YCBCR422 (0x1 << 0) 191 #define IN_COLOR_F_RGB (0x0 << 0) 192 193 /* video_ctl_3 */ 194 #define IN_YC_COEFFI_MASK (0x1 << 7) 195 #define IN_YC_COEFFI_SHIFT (7) 196 #define IN_YC_COEFFI_ITU709 (0x1 << 7) 197 #define IN_YC_COEFFI_ITU601 (0x0 << 7) 198 #define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4) 199 #define VID_CHK_UPDATE_TYPE_SHIFT (4) 200 #define VID_CHK_UPDATE_TYPE_1 (0x1 << 4) 201 #define VID_CHK_UPDATE_TYPE_0 (0x0 << 4) 202 203 /* video_ctl_4 */ 204 #define BIST_EN (0x1 << 3) 205 #define BIST_WH_64 (0x1 << 2) 206 #define BIST_WH_32 (0x0 << 2) 207 #define BIST_TYPE_COLR_BAR (0x0 << 0) 208 #define BIST_TYPE_GRAY_BAR (0x1 << 0) 209 #define BIST_TYPE_MOBILE_BAR (0x2 << 0) 210 211 /* video_ctl_8 */ 212 #define VID_HRES_TH(x) (((x) & 0xf) << 4) 213 #define VID_VRES_TH(x) (((x) & 0xf) << 0) 214 215 /* video_ctl_10 */ 216 #define F_SEL (0x1 << 4) 217 #define INTERACE_SCAN_CFG (0x1 << 2) 218 #define INTERACD_SCAN_CFG_OFFSET 2 219 #define VSYNC_POLARITY_CFG (0x1 << 1) 220 #define VSYNC_POLARITY_CFG_OFFSET 1 221 #define HSYNC_POLARITY_CFG (0x1 << 0) 222 #define HSYNC_POLARITY_CFG_OFFSET 0 223 224 /* dp_pd */ 225 #define PD_INC_BG (0x1 << 7) 226 #define PD_EXP_BG (0x1 << 6) 227 #define PD_AUX (0x1 << 5) 228 #define PD_PLL (0x1 << 4) 229 #define PD_CH3 (0x1 << 3) 230 #define PD_CH2 (0x1 << 2) 231 #define PD_CH1 (0x1 << 1) 232 #define PD_CH0 (0x1 << 0) 233 234 /* pll_reg_1 */ 235 #define REF_CLK_24M (0x1 << 0) 236 #define REF_CLK_27M (0x0 << 0) 237 #define REF_CLK_MASK (0x1 << 0) 238 239 /* line_map */ 240 #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) 241 #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6) 242 #define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6) 243 #define LANE3_MAP_LOGIC_LANE_3 (0x3 << 6) 244 #define LANE2_MAP_LOGIC_LANE_0 (0x0 << 4) 245 #define LANE2_MAP_LOGIC_LANE_1 (0x1 << 4) 246 #define LANE2_MAP_LOGIC_LANE_2 (0x2 << 4) 247 #define LANE2_MAP_LOGIC_LANE_3 (0x3 << 4) 248 #define LANE1_MAP_LOGIC_LANE_0 (0x0 << 2) 249 #define LANE1_MAP_LOGIC_LANE_1 (0x1 << 2) 250 #define LANE1_MAP_LOGIC_LANE_2 (0x2 << 2) 251 #define LANE1_MAP_LOGIC_LANE_3 (0x3 << 2) 252 #define LANE0_MAP_LOGIC_LANE_0 (0x0 << 0) 253 #define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0) 254 #define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0) 255 #define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0) 256 257 /* analog_ctl_2 */ 258 #define SEL_24M (0x1 << 3) 259 260 /* common_int_sta_1 */ 261 #define VSYNC_DET (0x1 << 7) 262 #define PLL_LOCK_CHG (0x1 << 6) 263 #define SPDIF_ERR (0x1 << 5) 264 #define SPDIF_UNSTBL (0x1 << 4) 265 #define VID_FORMAT_CHG (0x1 << 3) 266 #define AUD_CLK_CHG (0x1 << 2) 267 #define VID_CLK_CHG (0x1 << 1) 268 #define SW_INT (0x1 << 0) 269 270 /* common_int_sta_2 */ 271 #define ENC_EN_CHG (0x1 << 6) 272 #define HW_BKSV_RDY (0x1 << 3) 273 #define HW_SHA_DONE (0x1 << 2) 274 #define HW_AUTH_STATE_CHG (0x1 << 1) 275 #define HW_AUTH_DONE (0x1 << 0) 276 277 /* common_int_sta_3 */ 278 #define AFIFO_UNDER (0x1 << 7) 279 #define AFIFO_OVER (0x1 << 6) 280 #define R0_CHK_FLAG (0x1 << 5) 281 282 /* common_int_sta_4 */ 283 #define PSR_ACTIVE (0x1 << 7) 284 #define PSR_INACTIVE (0x1 << 6) 285 #define SPDIF_BI_PHASE_ERR (0x1 << 5) 286 #define HOTPLUG_CHG (0x1 << 2) 287 #define HPD_LOST (0x1 << 1) 288 #define PLUG (0x1 << 0) 289 290 /* dp_int_sta */ 291 #define INT_HPD (0x1 << 6) 292 #define HW_LT_DONE (0x1 << 5) 293 #define SINK_LOST (0x1 << 3) 294 #define LINK_LOST (0x1 << 2) 295 #define RPLY_RECEIV (0x1 << 1) 296 #define AUX_ERR (0x1 << 0) 297 298 /* int_ctl */ 299 #define SOFT_INT_CTRL (0x1 << 2) 300 #define INT_POL1 (0x1 << 1) 301 #define INT_POL0 (0x1 << 0) 302 #define INT_POL (INT_POL0 | INT_POL1) 303 304 /* sys_ctl_1 */ 305 #define DET_STA (0x1 << 2) 306 #define FORCE_DET (0x1 << 1) 307 #define DET_CTRL (0x1 << 0) 308 309 /* sys_ctl_2 */ 310 #define CHA_CRI(x) (((x) & 0xf) << 4) 311 #define CHA_STA (0x1 << 2) 312 #define FORCE_CHA (0x1 << 1) 313 #define CHA_CTRL (0x1 << 0) 314 315 /* sys_ctl_3 */ 316 #define HPD_STATUS (0x1 << 6) 317 #define F_HPD (0x1 << 5) 318 #define HPD_CTRL (0x1 << 4) 319 #define HDCP_RDY (0x1 << 3) 320 #define STRM_VALID (0x1 << 2) 321 #define F_VALID (0x1 << 1) 322 #define VALID_CTRL (0x1 << 0) 323 324 /* sys_ctl_4 */ 325 #define FIX_M_AUD (0x1 << 4) 326 #define ENHANCED (0x1 << 3) 327 #define FIX_M_VID (0x1 << 2) 328 #define M_VID_UPDATE_CTRL (0x3 << 0) 329 330 /* pll_reg_2 */ 331 #define LDO_OUTPUT_V_SEL_145 (2 << 6) 332 #define KVCO_DEFALUT (1 << 4) 333 #define CHG_PUMP_CUR_SEL_5US (1 << 2) 334 #define V2L_CUR_SEL_1MA (1 << 0) 335 336 /* pll_reg_3 */ 337 #define LOCK_DET_CNT_SEL_256 (2 << 5) 338 #define LOOP_FILTER_RESET (0 << 4) 339 #define PALL_SSC_RESET (0 << 3) 340 #define LOCK_DET_BYPASS (0 << 2) 341 #define PLL_LOCK_DET_MODE (0 << 1) 342 #define PLL_LOCK_DET_FORCE (0 << 0) 343 344 /* pll_reg_5 */ 345 #define REGULATOR_V_SEL_950MV (2 << 4) 346 #define STANDBY_CUR_SEL (0 << 3) 347 #define CHG_PUMP_INOUT_CTRL_1200MV (1 << 1) 348 #define CHG_PUMP_INPUT_CTRL_OP (0 << 0) 349 350 /* ssc_reg */ 351 #define SSC_OFFSET (0 << 6) 352 #define SSC_MODE (1 << 4) 353 #define SSC_DEPTH (9 << 0) 354 355 /* tx_common */ 356 #define TX_SWING_PRE_EMP_MODE (1 << 7) 357 #define PRE_DRIVER_PW_CTRL1 (0 << 5) 358 #define LP_MODE_CLK_REGULATOR (0 << 4) 359 #define RESISTOR_MSB_CTRL (0 << 3) 360 #define RESISTOR_CTRL (7 << 0) 361 362 /* dp_aux */ 363 #define DP_AUX_COMMON_MODE (0 << 4) 364 #define DP_AUX_EN (0 << 3) 365 #define AUX_TERM_50OHM (3 << 0) 366 367 /* dp_bias */ 368 #define DP_BG_OUT_SEL (4 << 4) 369 #define DP_DB_CUR_CTRL (0 << 3) 370 #define DP_BG_SEL (1 << 2) 371 #define DP_RESISTOR_TUNE_BG (2 << 0) 372 373 /* dp_reserv2 */ 374 #define CH1_CH3_SWING_EMP_CTRL (5 << 4) 375 #define CH0_CH2_SWING_EMP_CTRL (5 << 0) 376 377 /* dp_training_ptn_set */ 378 #define SCRAMBLING_DISABLE (0x1 << 5) 379 #define SCRAMBLING_ENABLE (0x0 << 5) 380 #define LINK_QUAL_PATTERN_SET_MASK (0x7 << 2) 381 #define LINK_QUAL_PATTERN_SET_HBR2 (0x5 << 2) 382 #define LINK_QUAL_PATTERN_SET_80BIT (0x4 << 2) 383 #define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2) 384 #define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2) 385 #define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2) 386 #define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0) 387 #define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0) 388 #define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0) 389 #define SW_TRAINING_PATTERN_SET_DISABLE (0x0 << 0) 390 391 /* dp_hw_link_training_ctl */ 392 #define HW_LT_ERR_CODE_MASK 0x70 393 #define HW_LT_ERR_CODE_SHIFT 4 394 #define HW_LT_EN (0x1 << 0) 395 396 /* dp_debug_ctl */ 397 #define PLL_LOCK (0x1 << 4) 398 #define F_PLL_LOCK (0x1 << 3) 399 #define PLL_LOCK_CTRL (0x1 << 2) 400 #define POLL_EN (0x1 << 1) 401 #define PN_INV (0x1 << 0) 402 403 /* aux_ch_sta */ 404 #define AUX_BUSY (0x1 << 4) 405 #define AUX_STATUS_MASK (0xf << 0) 406 407 /* aux_ch_defer_ctl */ 408 #define DEFER_CTRL_EN (0x1 << 7) 409 #define DEFER_COUNT(x) (((x) & 0x7f) << 0) 410 411 /* aux_rx_comm */ 412 #define AUX_RX_COMM_I2C_DEFER (0x2 << 2) 413 #define AUX_RX_COMM_AUX_DEFER (0x2 << 0) 414 415 /* buffer_data_ctl */ 416 #define BUF_CLR (0x1 << 7) 417 #define BUF_HAVE_DATA (0x1 << 4) 418 #define BUF_DATA_COUNT(x) (((x) & 0xf) << 0) 419 420 /* aux_ch_ctl_1 */ 421 #define AUX_LENGTH(x) (((x - 1) & 0xf) << 4) 422 #define AUX_TX_COMM_MASK (0xf << 0) 423 #define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3) 424 #define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3) 425 #define AUX_TX_COMM_MOT (0x1 << 2) 426 #define AUX_TX_COMM_WRITE (0x0 << 0) 427 #define AUX_TX_COMM_READ (0x1 << 0) 428 429 /* aux_ch_ctl_2 */ 430 #define PD_AUX_IDLE (0x1 << 3) 431 #define ADDR_ONLY (0x1 << 1) 432 #define AUX_EN (0x1 << 0) 433 434 /* tx_sw_reset */ 435 #define RST_DP_TX (0x1 << 0) 436 437 /* analog_ctl_1 */ 438 #define TX_TERMINAL_CTRL_50_OHM (0x1 << 4) 439 440 /* analog_ctl_3 */ 441 #define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) 442 #define VCO_BIT_600_MICRO (0x5 << 0) 443 444 /* pll_filter_ctl_1 */ 445 #define PD_RING_OSC (0x1 << 6) 446 #define AUX_TERMINAL_CTRL_37_5_OHM (0x0 << 4) 447 #define AUX_TERMINAL_CTRL_45_OHM (0x1 << 4) 448 #define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4) 449 #define AUX_TERMINAL_CTRL_65_OHM (0x3 << 4) 450 #define TX_CUR1_2X (0x1 << 2) 451 #define TX_CUR_16_MA (0x3 << 0) 452 453 /* Definition for DPCD Register */ 454 #define DPCD_DPCD_REV (0x0000) 455 #define DPCD_MAX_LINK_RATE (0x0001) 456 #define DPCD_MAX_LANE_COUNT (0x0002) 457 #define DP_MAX_LANE_COUNT_MASK 0x1f 458 #define DP_TPS3_SUPPORTED (1 << 6) 459 #define DP_ENHANCED_FRAME_CAP (1 << 7) 460 461 #define DPCD_LINK_BW_SET (0x0100) 462 #define DPCD_LANE_COUNT_SET (0x0101) 463 464 #define DPCD_TRAINING_PATTERN_SET (0x0102) 465 #define DP_TRAINING_PATTERN_DISABLE 0 466 #define DP_TRAINING_PATTERN_1 1 467 #define DP_TRAINING_PATTERN_2 2 468 #define DP_TRAINING_PATTERN_3 3 469 #define DP_TRAINING_PATTERN_MASK 0x3 470 471 #define DPCD_TRAINING_LANE0_SET (0x0103) 472 #define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 473 #define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 474 #define DP_TRAIN_MAX_SWING_REACHED (1 << 2) 475 #define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) 476 #define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) 477 #define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) 478 #define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) 479 480 #define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) 481 #define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) 482 #define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) 483 #define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) 484 #define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) 485 486 #define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 487 #define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) 488 489 #define DPCD_LANE0_1_STATUS (0x0202) 490 #define DPCD_LANE2_3_STATUS (0x0203) 491 #define DP_LANE_CR_DONE (1 << 0) 492 #define DP_LANE_CHANNEL_EQ_DONE (1 << 1) 493 #define DP_LANE_SYMBOL_LOCKED (1 << 2) 494 #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE |\ 495 DP_LANE_CHANNEL_EQ_DONE |\ 496 DP_LANE_SYMBOL_LOCKED) 497 498 #define DPCD_LANE_ALIGN_STATUS_UPDATED (0x0204) 499 #define DP_INTERLANE_ALIGN_DONE (1 << 0) 500 #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) 501 #define DP_LINK_STATUS_UPDATED (1 << 7) 502 503 #define DPCD_ADJUST_REQUEST_LANE0_1 (0x0206) 504 #define DPCD_ADJUST_REQUEST_LANE2_3 (0x0207) 505 #define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 506 #define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 507 #define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c 508 #define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 509 #define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 510 #define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 511 #define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 512 #define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 513 514 #define DPCD_TEST_REQUEST (0x0218) 515 #define DPCD_TEST_RESPONSE (0x0260) 516 #define DPCD_TEST_EDID_CHECKSUM (0x0261) 517 #define DPCD_LINK_POWER_STATE (0x0600) 518 #define DP_SET_POWER_D0 0x1 519 #define DP_SET_POWER_D3 0x2 520 #define DP_SET_POWER_MASK 0x3 521 522 #define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) 523 #define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) 524 #define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f) 525 526 #define STREAM_ON_TIMEOUT 100 527 #define PLL_LOCK_TIMEOUT 10 528 #define DP_INIT_TRIES 10 529 530 #define EDID_ADDR 0x50 531 #define EDID_LENGTH 0x80 532 #define EDID_HEADER 0x00 533 #define EDID_EXTENSION_FLAG 0x7e 534 535 536 enum dpcd_request { 537 DPCD_READ, 538 DPCD_WRITE, 539 }; 540 541 enum dp_irq_type { 542 DP_IRQ_TYPE_HP_CABLE_IN, 543 DP_IRQ_TYPE_HP_CABLE_OUT, 544 DP_IRQ_TYPE_HP_CHANGE, 545 DP_IRQ_TYPE_UNKNOWN, 546 }; 547 548 enum color_coefficient { 549 COLOR_YCBCR601, 550 COLOR_YCBCR709 551 }; 552 553 enum dynamic_range { 554 VESA, 555 CEA 556 }; 557 558 enum clock_recovery_m_value_type { 559 CALCULATED_M, 560 REGISTER_M 561 }; 562 563 enum video_timing_recognition_type { 564 VIDEO_TIMING_FROM_CAPTURE, 565 VIDEO_TIMING_FROM_REGISTER 566 }; 567 568 enum pattern_set { 569 PRBS7, 570 D10_2, 571 TRAINING_PTN1, 572 TRAINING_PTN2, 573 DP_NONE 574 }; 575 576 enum color_space { 577 CS_RGB, 578 CS_YCBCR422, 579 CS_YCBCR444 580 }; 581 582 enum color_depth { 583 COLOR_6, 584 COLOR_8, 585 COLOR_10, 586 COLOR_12 587 }; 588 589 enum link_rate_type { 590 LINK_RATE_1_62GBPS = 0x06, 591 LINK_RATE_2_70GBPS = 0x0a 592 }; 593 594 enum link_lane_count_type { 595 LANE_CNT1 = 1, 596 LANE_CNT2 = 2, 597 LANE_CNT4 = 4 598 }; 599 600 enum link_training_state { 601 LT_START, 602 LT_CLK_RECOVERY, 603 LT_EQ_TRAINING, 604 FINISHED, 605 FAILED 606 }; 607 608 enum voltage_swing_level { 609 VOLTAGE_LEVEL_0, 610 VOLTAGE_LEVEL_1, 611 VOLTAGE_LEVEL_2, 612 VOLTAGE_LEVEL_3, 613 }; 614 615 enum pre_emphasis_level { 616 PRE_EMPHASIS_LEVEL_0, 617 PRE_EMPHASIS_LEVEL_1, 618 PRE_EMPHASIS_LEVEL_2, 619 PRE_EMPHASIS_LEVEL_3, 620 }; 621 622 enum analog_power_block { 623 AUX_BLOCK, 624 CH0_BLOCK, 625 CH1_BLOCK, 626 CH2_BLOCK, 627 CH3_BLOCK, 628 ANALOG_TOTAL, 629 POWER_ALL 630 }; 631 632 struct link_train { 633 unsigned char revision; 634 u8 link_rate; 635 u8 lane_count; 636 }; 637 638 #endif 639