1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (c) 2011 The Chromium OS Authors.
4  * Copyright (c) 2009-2015 NVIDIA Corporation
5  * Copyright (c) 2013 Lucas Stach
6  */
7 
8 #include <common.h>
9 #include <dm.h>
10 #include <log.h>
11 #include <linux/delay.h>
12 #include <linux/errno.h>
13 #include <asm/io.h>
14 #include <asm-generic/gpio.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch-tegra/usb.h>
17 #include <asm/arch-tegra/clk_rst.h>
18 #include <usb.h>
19 #include <usb/ulpi.h>
20 #include <linux/libfdt.h>
21 
22 #include "ehci.h"
23 
24 #define USB1_ADDR_MASK	0xFFFF0000
25 
26 #define HOSTPC1_DEVLC	0x84
27 #define HOSTPC1_PSPD(x)		(((x) >> 25) & 0x3)
28 
29 #ifdef CONFIG_USB_ULPI
30 	#ifndef CONFIG_USB_ULPI_VIEWPORT
31 	#error	"To use CONFIG_USB_ULPI on Tegra Boards you have to also \
32 		define CONFIG_USB_ULPI_VIEWPORT"
33 	#endif
34 #endif
35 
36 /* Parameters we need for USB */
37 enum {
38 	PARAM_DIVN,                     /* PLL FEEDBACK DIVIDer */
39 	PARAM_DIVM,                     /* PLL INPUT DIVIDER */
40 	PARAM_DIVP,                     /* POST DIVIDER (2^N) */
41 	PARAM_CPCON,                    /* BASE PLLC CHARGE Pump setup ctrl */
42 	PARAM_LFCON,                    /* BASE PLLC LOOP FILter setup ctrl */
43 	PARAM_ENABLE_DELAY_COUNT,       /* PLL-U Enable Delay Count */
44 	PARAM_STABLE_COUNT,             /* PLL-U STABLE count */
45 	PARAM_ACTIVE_DELAY_COUNT,       /* PLL-U Active delay count */
46 	PARAM_XTAL_FREQ_COUNT,          /* PLL-U XTAL frequency count */
47 	PARAM_DEBOUNCE_A_TIME,          /* 10MS DELAY for BIAS_DEBOUNCE_A */
48 	PARAM_BIAS_TIME,                /* 20US DELAY AFter bias cell op */
49 
50 	PARAM_COUNT
51 };
52 
53 /* Possible port types (dual role mode) */
54 enum dr_mode {
55 	DR_MODE_NONE = 0,
56 	DR_MODE_HOST,		/* supports host operation */
57 	DR_MODE_DEVICE,		/* supports device operation */
58 	DR_MODE_OTG,		/* supports both */
59 };
60 
61 enum usb_ctlr_type {
62 	USB_CTLR_T20,
63 	USB_CTLR_T30,
64 	USB_CTLR_T114,
65 	USB_CTLR_T210,
66 
67 	USB_CTRL_COUNT,
68 };
69 
70 /* Information about a USB port */
71 struct fdt_usb {
72 	struct ehci_ctrl ehci;
73 	struct usb_ctlr *reg;	/* address of registers in physical memory */
74 	unsigned utmi:1;	/* 1 if port has external tranceiver, else 0 */
75 	unsigned ulpi:1;	/* 1 if port has external ULPI transceiver */
76 	unsigned enabled:1;	/* 1 to enable, 0 to disable */
77 	unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */
78 	enum usb_ctlr_type type;
79 	enum usb_init_type init_type;
80 	enum dr_mode dr_mode;	/* dual role mode */
81 	enum periph_id periph_id;/* peripheral id */
82 	struct gpio_desc vbus_gpio;	/* GPIO for vbus enable */
83 	struct gpio_desc phy_reset_gpio; /* GPIO to reset ULPI phy */
84 };
85 
86 /*
87  * This table has USB timing parameters for each Oscillator frequency we
88  * support. There are four sets of values:
89  *
90  * 1. PLLU configuration information (reference clock is osc/clk_m and
91  * PLLU-FOs are fixed at 12MHz/60MHz/480MHz).
92  *
93  *  Reference frequency     13.0MHz      19.2MHz      12.0MHz      26.0MHz
94  *  ----------------------------------------------------------------------
95  *      DIVN                960 (0x3c0)  200 (0c8)    960 (3c0h)   960 (3c0)
96  *      DIVM                13 (0d)      4 (04)       12 (0c)      26 (1a)
97  * Filter frequency (MHz)   1            4.8          6            2
98  * CPCON                    1100b        0011b        1100b        1100b
99  * LFCON0                   0            0            0            0
100  *
101  * 2. PLL CONFIGURATION & PARAMETERS for different clock generators:
102  *
103  * Reference frequency     13.0MHz         19.2MHz         12.0MHz     26.0MHz
104  * ---------------------------------------------------------------------------
105  * PLLU_ENABLE_DLY_COUNT   02 (0x02)       03 (03)         02 (02)     04 (04)
106  * PLLU_STABLE_COUNT       51 (33)         75 (4B)         47 (2F)    102 (66)
107  * PLL_ACTIVE_DLY_COUNT    05 (05)         06 (06)         04 (04)     09 (09)
108  * XTAL_FREQ_COUNT        127 (7F)        187 (BB)        118 (76)    254 (FE)
109  *
110  * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and
111  * SessEnd. Each of these signals have their own debouncer and for each of
112  * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or
113  * BIAS_DEBOUNCE_B).
114  *
115  * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows:
116  *    0xffff -> No debouncing at all
117  *    <n> ms = <n> *1000 / (1/19.2MHz) / 4
118  *
119  * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have:
120  * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4  = 4800 = 0x12c0
121  *
122  * We need to use only DebounceA for BOOTROM. We don't need the DebounceB
123  * values, so we can keep those to default.
124  *
125  * 4. The 20 microsecond delay after bias cell operation.
126  */
127 static const unsigned T20_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
128 	/* DivN, DivM, DivP, CPCON, LFCON, Delays             Debounce, Bias */
129 	{ 0x3C0, 0x0D, 0x00, 0xC,   0,  0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 },
130 	{ 0x0C8, 0x04, 0x00, 0x3,   0,  0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 },
131 	{ 0x3C0, 0x0C, 0x00, 0xC,   0,  0x02, 0x2F, 0x04, 0x76, 0x7530, 5 },
132 	{ 0x3C0, 0x1A, 0x00, 0xC,   0,  0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 },
133 	{ 0x000, 0x00, 0x00, 0x0,   0,  0x00, 0x00, 0x00, 0x00, 0x0000, 0 },
134 	{ 0x000, 0x00, 0x00, 0x0,   0,  0x00, 0x00, 0x00, 0x00, 0x0000, 0 }
135 };
136 
137 static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
138 	/* DivN, DivM, DivP, CPCON, LFCON, Delays             Debounce, Bias */
139 	{ 0x3C0, 0x0D, 0x00, 0xC,   1,  0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 },
140 	{ 0x0C8, 0x04, 0x00, 0x3,   0,  0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 },
141 	{ 0x3C0, 0x0C, 0x00, 0xC,   1,  0x02, 0x2F, 0x08, 0x76, 0x7530, 5 },
142 	{ 0x3C0, 0x1A, 0x00, 0xC,   1,  0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 },
143 	{ 0x000, 0x00, 0x00, 0x0,   0,  0x00, 0x00, 0x00, 0x00, 0x0000, 0 },
144 	{ 0x000, 0x00, 0x00, 0x0,   0,  0x00, 0x00, 0x00, 0x00, 0x0000, 0 }
145 };
146 
147 static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
148 	/* DivN, DivM, DivP, CPCON, LFCON, Delays             Debounce, Bias */
149 	{ 0x3C0, 0x0D, 0x00, 0xC,   2,  0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 },
150 	{ 0x0C8, 0x04, 0x00, 0x3,   2,  0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 },
151 	{ 0x3C0, 0x0C, 0x00, 0xC,   2,  0x02, 0x2F, 0x08, 0x76, 0x7530, 5 },
152 	{ 0x3C0, 0x1A, 0x00, 0xC,   2,  0x04, 0x66, 0x09, 0xFE, 0xFDE8, 11 },
153 	{ 0x000, 0x00, 0x00, 0x0,   0,  0x00, 0x00, 0x00, 0x00, 0x0000, 0 },
154 	{ 0x000, 0x00, 0x00, 0x0,   0,  0x00, 0x00, 0x00, 0x00, 0x0000, 0 }
155 };
156 
157 /* NOTE: 13/26MHz settings are N/A for T210, so dupe 12MHz settings for now */
158 static const unsigned T210_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
159 	/* DivN, DivM, DivP, KCP,   KVCO,  Delays              Debounce, Bias */
160 	{ 0x028, 0x01, 0x01, 0x0,   0,  0x02, 0x2F, 0x08, 0x76,  32500,  5 },
161 	{ 0x019, 0x01, 0x01, 0x0,   0,  0x03, 0x4B, 0x0C, 0xBB,  48000,  8 },
162 	{ 0x028, 0x01, 0x01, 0x0,   0,  0x02, 0x2F, 0x08, 0x76,  30000,  5 },
163 	{ 0x028, 0x01, 0x01, 0x0,   0,  0x02, 0x2F, 0x08, 0x76,  65000,  5 },
164 	{ 0x019, 0x02, 0x01, 0x0,   0,  0x05, 0x96, 0x18, 0x177, 96000, 15 },
165 	{ 0x028, 0x04, 0x01, 0x0,   0,  0x04, 0x66, 0x09, 0xFE, 120000, 20 }
166 };
167 
168 /* UTMIP Idle Wait Delay */
169 static const u8 utmip_idle_wait_delay = 17;
170 
171 /* UTMIP Elastic limit */
172 static const u8 utmip_elastic_limit = 16;
173 
174 /* UTMIP High Speed Sync Start Delay */
175 static const u8 utmip_hs_sync_start_delay = 9;
176 
177 struct fdt_usb_controller {
178 	/* flag to determine whether controller supports hostpc register */
179 	u32 has_hostpc:1;
180 	const unsigned *pll_parameter;
181 };
182 
183 static struct fdt_usb_controller fdt_usb_controllers[USB_CTRL_COUNT] = {
184 	{
185 		.has_hostpc	= 0,
186 		.pll_parameter	= (const unsigned *)T20_usb_pll,
187 	},
188 	{
189 		.has_hostpc	= 1,
190 		.pll_parameter	= (const unsigned *)T30_usb_pll,
191 	},
192 	{
193 		.has_hostpc	= 1,
194 		.pll_parameter	= (const unsigned *)T114_usb_pll,
195 	},
196 	{
197 		.has_hostpc	= 1,
198 		.pll_parameter	= (const unsigned *)T210_usb_pll,
199 	},
200 };
201 
202 /*
203  * A known hardware issue where Connect Status Change bit of PORTSC register
204  * of USB1 controller will be set after Port Reset.
205  * We have to clear it in order for later device enumeration to proceed.
206  */
tegra_ehci_powerup_fixup(struct ehci_ctrl * ctrl,uint32_t * status_reg,uint32_t * reg)207 static void tegra_ehci_powerup_fixup(struct ehci_ctrl *ctrl,
208 				     uint32_t *status_reg, uint32_t *reg)
209 {
210 	struct fdt_usb *config = ctrl->priv;
211 	struct fdt_usb_controller *controller;
212 
213 	controller = &fdt_usb_controllers[config->type];
214 	mdelay(50);
215 	/* This is to avoid PORT_ENABLE bit to be cleared in "ehci-hcd.c". */
216 	if (controller->has_hostpc)
217 		*reg |= EHCI_PS_PE;
218 
219 	if (!config->has_legacy_mode)
220 		return;
221 	/* For EHCI_PS_CSC to be cleared in ehci_hcd.c */
222 	if (ehci_readl(status_reg) & EHCI_PS_CSC)
223 		*reg |= EHCI_PS_CSC;
224 }
225 
tegra_ehci_set_usbmode(struct ehci_ctrl * ctrl)226 static void tegra_ehci_set_usbmode(struct ehci_ctrl *ctrl)
227 {
228 	struct fdt_usb *config = ctrl->priv;
229 	struct usb_ctlr *usbctlr;
230 	uint32_t tmp;
231 
232 	usbctlr = config->reg;
233 
234 	tmp = ehci_readl(&usbctlr->usb_mode);
235 	tmp |= USBMODE_CM_HC;
236 	ehci_writel(&usbctlr->usb_mode, tmp);
237 }
238 
tegra_ehci_get_port_speed(struct ehci_ctrl * ctrl,uint32_t reg)239 static int tegra_ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg)
240 {
241 	struct fdt_usb *config = ctrl->priv;
242 	struct fdt_usb_controller *controller;
243 	uint32_t tmp;
244 	uint32_t *reg_ptr;
245 
246 	controller = &fdt_usb_controllers[config->type];
247 	if (controller->has_hostpc) {
248 		reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd +
249 				HOSTPC1_DEVLC);
250 		tmp = ehci_readl(reg_ptr);
251 		return HOSTPC1_PSPD(tmp);
252 	} else
253 		return PORTSC_PSPD(reg);
254 }
255 
256 /* Set up VBUS for host/device mode */
set_up_vbus(struct fdt_usb * config,enum usb_init_type init)257 static void set_up_vbus(struct fdt_usb *config, enum usb_init_type init)
258 {
259 	/*
260 	 * If we are an OTG port initializing in host mode,
261 	 * check if remote host is driving VBus and bail out in this case.
262 	 */
263 	if (init == USB_INIT_HOST &&
264 	    config->dr_mode == DR_MODE_OTG &&
265 	    (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) {
266 		printf("tegrausb: VBUS input active; not enabling as host\n");
267 		return;
268 	}
269 
270 	if (dm_gpio_is_valid(&config->vbus_gpio)) {
271 		int vbus_value;
272 
273 		vbus_value = (init == USB_INIT_HOST);
274 		dm_gpio_set_value(&config->vbus_gpio, vbus_value);
275 
276 		debug("set_up_vbus: GPIO %d %d\n",
277 		      gpio_get_number(&config->vbus_gpio), vbus_value);
278 	}
279 }
280 
usbf_reset_controller(struct fdt_usb * config,struct usb_ctlr * usbctlr)281 static void usbf_reset_controller(struct fdt_usb *config,
282 				  struct usb_ctlr *usbctlr)
283 {
284 	/* Reset the USB controller with 2us delay */
285 	reset_periph(config->periph_id, 2);
286 
287 	/*
288 	 * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under
289 	 * base address
290 	 */
291 	if (config->has_legacy_mode)
292 		setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE);
293 
294 	/* Put UTMIP1/3 in reset */
295 	setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
296 
297 	/* Enable the UTMIP PHY */
298 	if (config->utmi)
299 		setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB);
300 }
301 
get_pll_timing(struct fdt_usb_controller * controller)302 static const unsigned *get_pll_timing(struct fdt_usb_controller *controller)
303 {
304 	const unsigned *timing;
305 
306 	timing = controller->pll_parameter +
307 		clock_get_osc_freq() * PARAM_COUNT;
308 
309 	return timing;
310 }
311 
312 /* select the PHY to use with a USB controller */
init_phy_mux(struct fdt_usb * config,uint pts,enum usb_init_type init)313 static void init_phy_mux(struct fdt_usb *config, uint pts,
314 			 enum usb_init_type init)
315 {
316 	struct usb_ctlr *usbctlr = config->reg;
317 
318 #if defined(CONFIG_TEGRA20)
319 	if (config->periph_id == PERIPH_ID_USBD) {
320 		clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK,
321 				pts << PTS1_SHIFT);
322 		clrbits_le32(&usbctlr->port_sc1, STS1);
323 	} else {
324 		clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
325 				pts << PTS_SHIFT);
326 		clrbits_le32(&usbctlr->port_sc1, STS);
327 	}
328 #else
329 	/* Set to Host mode (if applicable) after Controller Reset was done */
330 	clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC,
331 			(init == USB_INIT_HOST) ? USBMODE_CM_HC : 0);
332 	/*
333 	 * Select PHY interface after setting host mode.
334 	 * For device mode, the ordering requirement is not an issue, since
335 	 * only the first USB controller supports device mode, and that USB
336 	 * controller can only talk to a UTMI PHY, so the PHY selection is
337 	 * already made at reset time, so this write is a no-op.
338 	 */
339 	clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK,
340 			pts << PTS_SHIFT);
341 	clrbits_le32(&usbctlr->hostpc1_devlc, STS);
342 #endif
343 }
344 
345 /* set up the UTMI USB controller with the parameters provided */
init_utmi_usb_controller(struct fdt_usb * config,enum usb_init_type init)346 static int init_utmi_usb_controller(struct fdt_usb *config,
347 				    enum usb_init_type init)
348 {
349 	struct fdt_usb_controller *controller;
350 	u32 b_sess_valid_mask, val;
351 	int loop_count;
352 	const unsigned *timing;
353 	struct usb_ctlr *usbctlr = config->reg;
354 	struct clk_rst_ctlr *clkrst;
355 	struct usb_ctlr *usb1ctlr;
356 
357 	clock_enable(config->periph_id);
358 
359 	/* Reset the usb controller */
360 	usbf_reset_controller(config, usbctlr);
361 
362 	/* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */
363 	clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
364 
365 	/* Follow the crystal clock disable by >100ns delay */
366 	udelay(1);
367 
368 	b_sess_valid_mask = (VBUS_B_SESS_VLD_SW_VALUE | VBUS_B_SESS_VLD_SW_EN);
369 	clrsetbits_le32(&usbctlr->phy_vbus_sensors, b_sess_valid_mask,
370 			(init == USB_INIT_DEVICE) ? b_sess_valid_mask : 0);
371 
372 	/*
373 	 * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP
374 	 * mux must be switched to actually use a_sess_vld threshold.
375 	 */
376 	if (config->dr_mode == DR_MODE_OTG &&
377 	    dm_gpio_is_valid(&config->vbus_gpio))
378 		clrsetbits_le32(&usbctlr->usb1_legacy_ctrl,
379 			VBUS_SENSE_CTL_MASK,
380 			VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT);
381 
382 	controller = &fdt_usb_controllers[config->type];
383 	debug("controller=%p, type=%d\n", controller, config->type);
384 
385 	/*
386 	 * PLL Delay CONFIGURATION settings. The following parameters control
387 	 * the bring up of the plls.
388 	 */
389 	timing = get_pll_timing(controller);
390 
391 	if (!controller->has_hostpc) {
392 		val = readl(&usbctlr->utmip_misc_cfg1);
393 		clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
394 				timing[PARAM_STABLE_COUNT] <<
395 				UTMIP_PLLU_STABLE_COUNT_SHIFT);
396 		clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
397 				timing[PARAM_ACTIVE_DELAY_COUNT] <<
398 				UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
399 		writel(val, &usbctlr->utmip_misc_cfg1);
400 
401 		/* Set PLL enable delay count and crystal frequency count */
402 		val = readl(&usbctlr->utmip_pll_cfg1);
403 		clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
404 				timing[PARAM_ENABLE_DELAY_COUNT] <<
405 				UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
406 		clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
407 				timing[PARAM_XTAL_FREQ_COUNT] <<
408 				UTMIP_XTAL_FREQ_COUNT_SHIFT);
409 		writel(val, &usbctlr->utmip_pll_cfg1);
410 	} else {
411 		clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
412 
413 		val = readl(&clkrst->crc_utmip_pll_cfg2);
414 		clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
415 				timing[PARAM_STABLE_COUNT] <<
416 				UTMIP_PLLU_STABLE_COUNT_SHIFT);
417 		clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
418 				timing[PARAM_ACTIVE_DELAY_COUNT] <<
419 				UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
420 		writel(val, &clkrst->crc_utmip_pll_cfg2);
421 
422 		/* Set PLL enable delay count and crystal frequency count */
423 		val = readl(&clkrst->crc_utmip_pll_cfg1);
424 		clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
425 				timing[PARAM_ENABLE_DELAY_COUNT] <<
426 				UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
427 		clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
428 				timing[PARAM_XTAL_FREQ_COUNT] <<
429 				UTMIP_XTAL_FREQ_COUNT_SHIFT);
430 		writel(val, &clkrst->crc_utmip_pll_cfg1);
431 
432 		/* Disable Power Down state for PLL */
433 		clrbits_le32(&clkrst->crc_utmip_pll_cfg1,
434 			     PLLU_POWERDOWN | PLL_ENABLE_POWERDOWN |
435 			     PLL_ACTIVE_POWERDOWN);
436 
437 		/* Recommended PHY settings for EYE diagram */
438 		val = readl(&usbctlr->utmip_xcvr_cfg0);
439 		clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK,
440 				0x4 << UTMIP_XCVR_SETUP_SHIFT);
441 		clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK,
442 				0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT);
443 		clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK,
444 				0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT);
445 		writel(val, &usbctlr->utmip_xcvr_cfg0);
446 		clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1,
447 				UTMIP_XCVR_TERM_RANGE_ADJ_MASK,
448 				0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT);
449 
450 		/* Some registers can be controlled from USB1 only. */
451 		if (config->periph_id != PERIPH_ID_USBD) {
452 			clock_enable(PERIPH_ID_USBD);
453 			/* Disable Reset if in Reset state */
454 			reset_set_enable(PERIPH_ID_USBD, 0);
455 		}
456 		usb1ctlr = (struct usb_ctlr *)
457 			((unsigned long)config->reg & USB1_ADDR_MASK);
458 		val = readl(&usb1ctlr->utmip_bias_cfg0);
459 		setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB);
460 		clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK,
461 				0x1 << UTMIP_HSDISCON_LEVEL_SHIFT);
462 		clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK,
463 				0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT);
464 		writel(val, &usb1ctlr->utmip_bias_cfg0);
465 
466 		/* Miscellaneous setting mentioned in Programming Guide */
467 		clrbits_le32(&usbctlr->utmip_misc_cfg0,
468 			     UTMIP_SUSPEND_EXIT_ON_EDGE);
469 	}
470 
471 	/* Setting the tracking length time */
472 	clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
473 		UTMIP_BIAS_PDTRK_COUNT_MASK,
474 		timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT);
475 
476 	/* Program debounce time for VBUS to become valid */
477 	clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
478 		UTMIP_DEBOUNCE_CFG0_MASK,
479 		timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT);
480 
481 	if (timing[PARAM_DEBOUNCE_A_TIME] > 0xFFFF) {
482 		clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
483 				UTMIP_DEBOUNCE_CFG0_MASK,
484 				(timing[PARAM_DEBOUNCE_A_TIME] >> 1)
485 				<< UTMIP_DEBOUNCE_CFG0_SHIFT);
486 		clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
487 				UTMIP_BIAS_DEBOUNCE_TIMESCALE_MASK,
488 				1 << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT);
489 	}
490 
491 	setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J);
492 
493 	/* Disable battery charge enabling bit */
494 	setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG);
495 
496 	clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE);
497 	setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL);
498 
499 	/*
500 	 * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT
501 	 * Setting these fields, together with default values of the
502 	 * other fields, results in programming the registers below as
503 	 * follows:
504 	 *         UTMIP_HSRX_CFG0 = 0x9168c000
505 	 *         UTMIP_HSRX_CFG1 = 0x13
506 	 */
507 
508 	/* Set PLL enable delay count and Crystal frequency count */
509 	val = readl(&usbctlr->utmip_hsrx_cfg0);
510 	clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK,
511 		utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT);
512 	clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK,
513 		utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT);
514 	writel(val, &usbctlr->utmip_hsrx_cfg0);
515 
516 	/* Configure the UTMIP_HS_SYNC_START_DLY */
517 	clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1,
518 		UTMIP_HS_SYNC_START_DLY_MASK,
519 		utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT);
520 
521 	/* Preceed the crystal clock disable by >100ns delay. */
522 	udelay(1);
523 
524 	/* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */
525 	setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
526 
527 	if (controller->has_hostpc) {
528 		if (config->periph_id == PERIPH_ID_USBD)
529 			clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
530 				     UTMIP_FORCE_PD_SAMP_A_POWERDOWN);
531 		if (config->periph_id == PERIPH_ID_USB2)
532 			clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
533 				     UTMIP_FORCE_PD_SAMP_B_POWERDOWN);
534 		if (config->periph_id == PERIPH_ID_USB3)
535 			clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
536 				     UTMIP_FORCE_PD_SAMP_C_POWERDOWN);
537 	}
538 	/* Finished the per-controller init. */
539 
540 	/* De-assert UTMIP_RESET to bring out of reset. */
541 	clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
542 
543 	/* Wait for the phy clock to become valid in 100 ms */
544 	for (loop_count = 100000; loop_count != 0; loop_count--) {
545 		if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
546 			break;
547 		udelay(1);
548 	}
549 	if (!loop_count)
550 		return -ETIMEDOUT;
551 
552 	/* Disable ICUSB FS/LS transceiver */
553 	clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
554 
555 	/* Select UTMI parallel interface */
556 	init_phy_mux(config, PTS_UTMI, init);
557 
558 	/* Deassert power down state */
559 	clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
560 		UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN);
561 	clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN |
562 		UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN);
563 
564 	if (controller->has_hostpc) {
565 		/*
566 		 * BIAS Pad Power Down is common among all 3 USB
567 		 * controllers and can be controlled from USB1 only.
568 		 */
569 		usb1ctlr = (struct usb_ctlr *)
570 			((unsigned long)config->reg & USB1_ADDR_MASK);
571 		clrbits_le32(&usb1ctlr->utmip_bias_cfg0, UTMIP_BIASPD);
572 		udelay(25);
573 		clrbits_le32(&usb1ctlr->utmip_bias_cfg1,
574 			     UTMIP_FORCE_PDTRK_POWERDOWN);
575 	}
576 	return 0;
577 }
578 
579 #ifdef CONFIG_USB_ULPI
580 /* if board file does not set a ULPI reference frequency we default to 24MHz */
581 #ifndef CONFIG_ULPI_REF_CLK
582 #define CONFIG_ULPI_REF_CLK 24000000
583 #endif
584 
585 /* set up the ULPI USB controller with the parameters provided */
init_ulpi_usb_controller(struct fdt_usb * config,enum usb_init_type init)586 static int init_ulpi_usb_controller(struct fdt_usb *config,
587 				    enum usb_init_type init)
588 {
589 	u32 val;
590 	int loop_count;
591 	struct ulpi_viewport ulpi_vp;
592 	struct usb_ctlr *usbctlr = config->reg;
593 	int ret;
594 
595 	/* set up ULPI reference clock on pllp_out4 */
596 	clock_enable(PERIPH_ID_DEV2_OUT);
597 	clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK);
598 
599 	/* reset ULPI phy */
600 	if (dm_gpio_is_valid(&config->phy_reset_gpio)) {
601 		/*
602 		 * This GPIO is typically active-low, and marked as such in
603 		 * device tree. dm_gpio_set_value() takes this into account
604 		 * and inverts the value we pass here if required. In other
605 		 * words, this first call logically asserts the reset signal,
606 		 * which typically results in driving the physical GPIO low,
607 		 * and the second call logically de-asserts the reset signal,
608 		 * which typically results in driver the GPIO high.
609 		 */
610 		dm_gpio_set_value(&config->phy_reset_gpio, 1);
611 		mdelay(5);
612 		dm_gpio_set_value(&config->phy_reset_gpio, 0);
613 	}
614 
615 	/* Reset the usb controller */
616 	clock_enable(config->periph_id);
617 	usbf_reset_controller(config, usbctlr);
618 
619 	/* enable pinmux bypass */
620 	setbits_le32(&usbctlr->ulpi_timing_ctrl_0,
621 			ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP);
622 
623 	/* Select ULPI parallel interface */
624 	init_phy_mux(config, PTS_ULPI, init);
625 
626 	/* enable ULPI transceiver */
627 	setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB);
628 
629 	/* configure ULPI transceiver timings */
630 	val = 0;
631 	writel(val, &usbctlr->ulpi_timing_ctrl_1);
632 
633 	val |= ULPI_DATA_TRIMMER_SEL(4);
634 	val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
635 	val |= ULPI_DIR_TRIMMER_SEL(4);
636 	writel(val, &usbctlr->ulpi_timing_ctrl_1);
637 	udelay(10);
638 
639 	val |= ULPI_DATA_TRIMMER_LOAD;
640 	val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
641 	val |= ULPI_DIR_TRIMMER_LOAD;
642 	writel(val, &usbctlr->ulpi_timing_ctrl_1);
643 
644 	/* set up phy for host operation with external vbus supply */
645 	ulpi_vp.port_num = 0;
646 	ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport;
647 
648 	ret = ulpi_init(&ulpi_vp);
649 	if (ret) {
650 		printf("Tegra ULPI viewport init failed\n");
651 		return ret;
652 	}
653 
654 	ulpi_set_vbus(&ulpi_vp, 1, 1);
655 	ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0);
656 
657 	/* enable wakeup events */
658 	setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC);
659 
660 	/* Enable and wait for the phy clock to become valid in 100 ms */
661 	setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
662 	for (loop_count = 100000; loop_count != 0; loop_count--) {
663 		if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
664 			break;
665 		udelay(1);
666 	}
667 	if (!loop_count)
668 		return -ETIMEDOUT;
669 	clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
670 
671 	return 0;
672 }
673 #else
init_ulpi_usb_controller(struct fdt_usb * config,enum usb_init_type init)674 static int init_ulpi_usb_controller(struct fdt_usb *config,
675 				    enum usb_init_type init)
676 {
677 	printf("No code to set up ULPI controller, please enable"
678 			"CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT");
679 	return -ENOSYS;
680 }
681 #endif
682 
config_clock(const u32 timing[])683 static void config_clock(const u32 timing[])
684 {
685 	debug("%s: DIVM = %d, DIVN = %d, DIVP = %d, cpcon/lfcon = %d/%d\n",
686 	      __func__, timing[PARAM_DIVM], timing[PARAM_DIVN],
687 	      timing[PARAM_DIVP], timing[PARAM_CPCON], timing[PARAM_LFCON]);
688 
689 	clock_start_pll(CLOCK_ID_USB,
690 		timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP],
691 		timing[PARAM_CPCON], timing[PARAM_LFCON]);
692 }
693 
fdt_decode_usb(struct udevice * dev,struct fdt_usb * config)694 static int fdt_decode_usb(struct udevice *dev, struct fdt_usb *config)
695 {
696 	const char *phy, *mode;
697 
698 	config->reg = (struct usb_ctlr *)dev_read_addr(dev);
699 	debug("reg=%p\n", config->reg);
700 	mode = dev_read_string(dev, "dr_mode");
701 	if (mode) {
702 		if (0 == strcmp(mode, "host"))
703 			config->dr_mode = DR_MODE_HOST;
704 		else if (0 == strcmp(mode, "peripheral"))
705 			config->dr_mode = DR_MODE_DEVICE;
706 		else if (0 == strcmp(mode, "otg"))
707 			config->dr_mode = DR_MODE_OTG;
708 		else {
709 			debug("%s: Cannot decode dr_mode '%s'\n", __func__,
710 			      mode);
711 			return -EINVAL;
712 		}
713 	} else {
714 		config->dr_mode = DR_MODE_HOST;
715 	}
716 
717 	phy = dev_read_string(dev, "phy_type");
718 	config->utmi = phy && 0 == strcmp("utmi", phy);
719 	config->ulpi = phy && 0 == strcmp("ulpi", phy);
720 	config->has_legacy_mode = dev_read_bool(dev, "nvidia,has-legacy-mode");
721 	config->periph_id = clock_decode_periph_id(dev);
722 	if (config->periph_id == PERIPH_ID_NONE) {
723 		debug("%s: Missing/invalid peripheral ID\n", __func__);
724 		return -EINVAL;
725 	}
726 	gpio_request_by_name(dev, "nvidia,vbus-gpio", 0, &config->vbus_gpio,
727 			     GPIOD_IS_OUT);
728 	gpio_request_by_name(dev, "nvidia,phy-reset-gpio", 0,
729 			     &config->phy_reset_gpio, GPIOD_IS_OUT);
730 	debug("legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, vbus=%d, phy_reset=%d, dr_mode=%d, reg=%p\n",
731 	      config->has_legacy_mode, config->utmi, config->ulpi,
732 	      config->periph_id, gpio_get_number(&config->vbus_gpio),
733 	      gpio_get_number(&config->phy_reset_gpio), config->dr_mode,
734 	      config->reg);
735 
736 	return 0;
737 }
738 
usb_common_init(struct fdt_usb * config,enum usb_init_type init)739 int usb_common_init(struct fdt_usb *config, enum usb_init_type init)
740 {
741 	int ret = 0;
742 
743 	switch (init) {
744 	case USB_INIT_HOST:
745 		switch (config->dr_mode) {
746 		case DR_MODE_HOST:
747 		case DR_MODE_OTG:
748 			break;
749 		default:
750 			printf("tegrausb: Invalid dr_mode %d for host mode\n",
751 			       config->dr_mode);
752 			return -1;
753 		}
754 		break;
755 	case USB_INIT_DEVICE:
756 		if (config->periph_id != PERIPH_ID_USBD) {
757 			printf("tegrausb: Device mode only supported on first USB controller\n");
758 			return -1;
759 		}
760 		if (!config->utmi) {
761 			printf("tegrausb: Device mode only supported with UTMI PHY\n");
762 			return -1;
763 		}
764 		switch (config->dr_mode) {
765 		case DR_MODE_DEVICE:
766 		case DR_MODE_OTG:
767 			break;
768 		default:
769 			printf("tegrausb: Invalid dr_mode %d for device mode\n",
770 			       config->dr_mode);
771 			return -1;
772 		}
773 		break;
774 	default:
775 		printf("tegrausb: Unknown USB_INIT_* %d\n", init);
776 		return -1;
777 	}
778 
779 	debug("%d, %d\n", config->utmi, config->ulpi);
780 	if (config->utmi)
781 		ret = init_utmi_usb_controller(config, init);
782 	else if (config->ulpi)
783 		ret = init_ulpi_usb_controller(config, init);
784 	if (ret)
785 		return ret;
786 
787 	set_up_vbus(config, init);
788 
789 	config->init_type = init;
790 
791 	return 0;
792 }
793 
usb_common_uninit(struct fdt_usb * priv)794 void usb_common_uninit(struct fdt_usb *priv)
795 {
796 	struct usb_ctlr *usbctlr;
797 
798 	usbctlr = priv->reg;
799 
800 	/* Stop controller */
801 	writel(0, &usbctlr->usb_cmd);
802 	udelay(1000);
803 
804 	/* Initiate controller reset */
805 	writel(2, &usbctlr->usb_cmd);
806 	udelay(1000);
807 }
808 
809 static const struct ehci_ops tegra_ehci_ops = {
810 	.set_usb_mode		= tegra_ehci_set_usbmode,
811 	.get_port_speed		= tegra_ehci_get_port_speed,
812 	.powerup_fixup		= tegra_ehci_powerup_fixup,
813 };
814 
ehci_usb_of_to_plat(struct udevice * dev)815 static int ehci_usb_of_to_plat(struct udevice *dev)
816 {
817 	struct fdt_usb *priv = dev_get_priv(dev);
818 	int ret;
819 
820 	ret = fdt_decode_usb(dev, priv);
821 	if (ret)
822 		return ret;
823 
824 	priv->type = dev_get_driver_data(dev);
825 
826 	return 0;
827 }
828 
ehci_usb_probe(struct udevice * dev)829 static int ehci_usb_probe(struct udevice *dev)
830 {
831 	struct usb_plat *plat = dev_get_plat(dev);
832 	struct fdt_usb *priv = dev_get_priv(dev);
833 	struct ehci_hccr *hccr;
834 	struct ehci_hcor *hcor;
835 	static bool clk_done;
836 	int ret;
837 
838 	ret = usb_common_init(priv, plat->init_type);
839 	if (ret)
840 		return ret;
841 	hccr = (struct ehci_hccr *)&priv->reg->cap_length;
842 	hcor = (struct ehci_hcor *)&priv->reg->usb_cmd;
843 	if (!clk_done) {
844 		config_clock(get_pll_timing(&fdt_usb_controllers[priv->type]));
845 		clk_done = true;
846 	}
847 
848 	return ehci_register(dev, hccr, hcor, &tegra_ehci_ops, 0,
849 			     plat->init_type);
850 }
851 
852 static const struct udevice_id ehci_usb_ids[] = {
853 	{ .compatible = "nvidia,tegra20-ehci", .data = USB_CTLR_T20 },
854 	{ .compatible = "nvidia,tegra30-ehci", .data = USB_CTLR_T30 },
855 	{ .compatible = "nvidia,tegra114-ehci", .data = USB_CTLR_T114 },
856 	{ .compatible = "nvidia,tegra210-ehci", .data = USB_CTLR_T210 },
857 	{ }
858 };
859 
860 U_BOOT_DRIVER(usb_ehci) = {
861 	.name	= "ehci_tegra",
862 	.id	= UCLASS_USB,
863 	.of_match = ehci_usb_ids,
864 	.of_to_plat = ehci_usb_of_to_plat,
865 	.probe = ehci_usb_probe,
866 	.remove = ehci_deregister,
867 	.ops	= &ehci_usb_ops,
868 	.plat_auto	= sizeof(struct usb_plat),
869 	.priv_auto	= sizeof(struct fdt_usb),
870 	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
871 };
872