1 /* 2 * URB OHCI HCD (Host Controller Driver) for USB. 3 * 4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> 5 * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net> 6 * 7 * usb-ohci.h 8 */ 9 10 /* 11 * e.g. PCI controllers need this 12 */ 13 14 #include <asm/cache.h> 15 #include <asm/io.h> 16 17 #ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS 18 # define ohci_readl(a) __swap_32(in_be32((u32 *)a)) 19 # define ohci_writel(a, b) out_be32((u32 *)b, __swap_32(a)) 20 #else 21 # define ohci_readl(a) readl(a) 22 # define ohci_writel(v, a) writel(v, a) 23 #endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */ 24 25 #if ARCH_DMA_MINALIGN > 16 26 #define ED_ALIGNMENT ARCH_DMA_MINALIGN 27 #else 28 #define ED_ALIGNMENT 16 29 #endif 30 31 #if CONFIG_IS_ENABLED(DM_USB) && ARCH_DMA_MINALIGN > 32 32 #define TD_ALIGNMENT ARCH_DMA_MINALIGN 33 #else 34 #define TD_ALIGNMENT 32 35 #endif 36 37 /* functions for doing board or CPU specific setup/cleanup */ 38 int usb_board_stop(void); 39 40 int usb_cpu_init(void); 41 int usb_cpu_stop(void); 42 int usb_cpu_init_fail(void); 43 44 /* ED States */ 45 #define ED_NEW 0x00 46 #define ED_UNLINK 0x01 47 #define ED_OPER 0x02 48 #define ED_DEL 0x04 49 #define ED_URB_DEL 0x08 50 51 /* usb_ohci_ed */ 52 struct ed { 53 __u32 hwINFO; 54 __u32 hwTailP; 55 __u32 hwHeadP; 56 __u32 hwNextED; 57 58 struct ed *ed_prev; 59 __u8 int_period; 60 __u8 int_branch; 61 __u8 int_load; 62 __u8 int_interval; 63 __u8 state; 64 __u8 type; 65 __u16 last_iso; 66 struct ed *ed_rm_list; 67 68 struct usb_device *usb_dev; 69 void *purb; 70 __u32 unused[2]; 71 } __attribute__((aligned(ED_ALIGNMENT))); 72 typedef struct ed ed_t; 73 74 75 /* TD info field */ 76 #define TD_CC 0xf0000000 77 #define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) 78 #define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) 79 #define TD_EC 0x0C000000 80 #define TD_T 0x03000000 81 #define TD_T_DATA0 0x02000000 82 #define TD_T_DATA1 0x03000000 83 #define TD_T_TOGGLE 0x00000000 84 #define TD_R 0x00040000 85 #define TD_DI 0x00E00000 86 #define TD_DI_SET(X) (((X) & 0x07)<< 21) 87 #define TD_DP 0x00180000 88 #define TD_DP_SETUP 0x00000000 89 #define TD_DP_IN 0x00100000 90 #define TD_DP_OUT 0x00080000 91 92 #define TD_ISO 0x00010000 93 #define TD_DEL 0x00020000 94 95 /* CC Codes */ 96 #define TD_CC_NOERROR 0x00 97 #define TD_CC_CRC 0x01 98 #define TD_CC_BITSTUFFING 0x02 99 #define TD_CC_DATATOGGLEM 0x03 100 #define TD_CC_STALL 0x04 101 #define TD_DEVNOTRESP 0x05 102 #define TD_PIDCHECKFAIL 0x06 103 #define TD_UNEXPECTEDPID 0x07 104 #define TD_DATAOVERRUN 0x08 105 #define TD_DATAUNDERRUN 0x09 106 #define TD_BUFFEROVERRUN 0x0C 107 #define TD_BUFFERUNDERRUN 0x0D 108 #define TD_NOTACCESSED 0x0F 109 110 111 #define MAXPSW 1 112 113 struct td { 114 __u32 hwINFO; 115 __u32 hwCBP; /* Current Buffer Pointer */ 116 __u32 hwNextTD; /* Next TD Pointer */ 117 __u32 hwBE; /* Memory Buffer End Pointer */ 118 119 __u16 hwPSW[MAXPSW]; 120 __u8 unused; 121 __u8 index; 122 struct ed *ed; 123 struct td *next_dl_td; 124 struct usb_device *usb_dev; 125 int transfer_len; 126 __u32 data; 127 128 __u32 unused2[2]; 129 } __attribute__((aligned(TD_ALIGNMENT))); 130 typedef struct td td_t; 131 132 #define OHCI_ED_SKIP (1 << 14) 133 134 /* 135 * The HCCA (Host Controller Communications Area) is a 256 byte 136 * structure defined in the OHCI spec. that the host controller is 137 * told the base address of. It must be 256-byte aligned. 138 */ 139 140 #define NUM_INTS 32 /* part of the OHCI standard */ 141 struct ohci_hcca { 142 __u32 int_table[NUM_INTS]; /* Interrupt ED table */ 143 __u16 frame_no; /* current frame number */ 144 __u16 pad1; /* set to 0 on each frame_no change */ 145 __u32 done_head; /* info returned for an interrupt */ 146 u8 reserved_for_hc[116]; 147 } __attribute__((aligned(256))); 148 149 150 /* 151 * Maximum number of root hub ports. 152 */ 153 #ifndef CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 154 # error "CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS undefined!" 155 #endif 156 157 /* 158 * This is the structure of the OHCI controller's memory mapped I/O 159 * region. This is Memory Mapped I/O. You must use the ohci_readl() and 160 * ohci_writel() macros defined in this file to access these!! 161 */ 162 struct ohci_regs { 163 /* control and status registers */ 164 __u32 revision; 165 __u32 control; 166 __u32 cmdstatus; 167 __u32 intrstatus; 168 __u32 intrenable; 169 __u32 intrdisable; 170 /* memory pointers */ 171 __u32 hcca; 172 __u32 ed_periodcurrent; 173 __u32 ed_controlhead; 174 __u32 ed_controlcurrent; 175 __u32 ed_bulkhead; 176 __u32 ed_bulkcurrent; 177 __u32 donehead; 178 /* frame counters */ 179 __u32 fminterval; 180 __u32 fmremaining; 181 __u32 fmnumber; 182 __u32 periodicstart; 183 __u32 lsthresh; 184 /* Root hub ports */ 185 struct ohci_roothub_regs { 186 __u32 a; 187 __u32 b; 188 __u32 status; 189 __u32 portstatus[CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS]; 190 } roothub; 191 } __attribute__((aligned(32))); 192 193 /* Some EHCI controls */ 194 #define EHCI_USBCMD_OFF 0x20 195 #define EHCI_USBCMD_HCRESET (1 << 1) 196 197 /* OHCI CONTROL AND STATUS REGISTER MASKS */ 198 199 /* 200 * HcControl (control) register masks 201 */ 202 #define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ 203 #define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ 204 #define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ 205 #define OHCI_CTRL_CLE (1 << 4) /* control list enable */ 206 #define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ 207 #define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ 208 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ 209 #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ 210 #define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ 211 212 /* pre-shifted values for HCFS */ 213 # define OHCI_USB_RESET (0 << 6) 214 # define OHCI_USB_RESUME (1 << 6) 215 # define OHCI_USB_OPER (2 << 6) 216 # define OHCI_USB_SUSPEND (3 << 6) 217 218 /* 219 * HcCommandStatus (cmdstatus) register masks 220 */ 221 #define OHCI_HCR (1 << 0) /* host controller reset */ 222 #define OHCI_CLF (1 << 1) /* control list filled */ 223 #define OHCI_BLF (1 << 2) /* bulk list filled */ 224 #define OHCI_OCR (1 << 3) /* ownership change request */ 225 #define OHCI_SOC (3 << 16) /* scheduling overrun count */ 226 227 /* 228 * masks used with interrupt registers: 229 * HcInterruptStatus (intrstatus) 230 * HcInterruptEnable (intrenable) 231 * HcInterruptDisable (intrdisable) 232 */ 233 #define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ 234 #define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ 235 #define OHCI_INTR_SF (1 << 2) /* start frame */ 236 #define OHCI_INTR_RD (1 << 3) /* resume detect */ 237 #define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ 238 #define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ 239 #define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ 240 #define OHCI_INTR_OC (1 << 30) /* ownership change */ 241 #define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ 242 243 244 /* Virtual Root HUB */ 245 struct virt_root_hub { 246 int devnum; /* Address of Root Hub endpoint */ 247 void *dev; /* was urb */ 248 void *int_addr; 249 int send; 250 int interval; 251 }; 252 253 /* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ 254 255 /* destination of request */ 256 #define RH_INTERFACE 0x01 257 #define RH_ENDPOINT 0x02 258 #define RH_OTHER 0x03 259 260 #define RH_CLASS 0x20 261 #define RH_VENDOR 0x40 262 263 /* Requests: bRequest << 8 | bmRequestType */ 264 #define RH_GET_STATUS 0x0080 265 #define RH_CLEAR_FEATURE 0x0100 266 #define RH_SET_FEATURE 0x0300 267 #define RH_SET_ADDRESS 0x0500 268 #define RH_GET_DESCRIPTOR 0x0680 269 #define RH_SET_DESCRIPTOR 0x0700 270 #define RH_GET_CONFIGURATION 0x0880 271 #define RH_SET_CONFIGURATION 0x0900 272 #define RH_GET_STATE 0x0280 273 #define RH_GET_INTERFACE 0x0A80 274 #define RH_SET_INTERFACE 0x0B00 275 #define RH_SYNC_FRAME 0x0C80 276 /* Our Vendor Specific Request */ 277 #define RH_SET_EP 0x2000 278 279 280 /* Hub port features */ 281 #define RH_PORT_CONNECTION 0x00 282 #define RH_PORT_ENABLE 0x01 283 #define RH_PORT_SUSPEND 0x02 284 #define RH_PORT_OVER_CURRENT 0x03 285 #define RH_PORT_RESET 0x04 286 #define RH_PORT_POWER 0x08 287 #define RH_PORT_LOW_SPEED 0x09 288 289 #define RH_C_PORT_CONNECTION 0x10 290 #define RH_C_PORT_ENABLE 0x11 291 #define RH_C_PORT_SUSPEND 0x12 292 #define RH_C_PORT_OVER_CURRENT 0x13 293 #define RH_C_PORT_RESET 0x14 294 295 /* Hub features */ 296 #define RH_C_HUB_LOCAL_POWER 0x00 297 #define RH_C_HUB_OVER_CURRENT 0x01 298 299 #define RH_DEVICE_REMOTE_WAKEUP 0x00 300 #define RH_ENDPOINT_STALL 0x01 301 302 #define RH_ACK 0x01 303 #define RH_REQ_ERR -1 304 #define RH_NACK 0x00 305 306 307 /* OHCI ROOT HUB REGISTER MASKS */ 308 309 /* roothub.portstatus [i] bits */ 310 #define RH_PS_CCS 0x00000001 /* current connect status */ 311 #define RH_PS_PES 0x00000002 /* port enable status*/ 312 #define RH_PS_PSS 0x00000004 /* port suspend status */ 313 #define RH_PS_POCI 0x00000008 /* port over current indicator */ 314 #define RH_PS_PRS 0x00000010 /* port reset status */ 315 #define RH_PS_PPS 0x00000100 /* port power status */ 316 #define RH_PS_LSDA 0x00000200 /* low speed device attached */ 317 #define RH_PS_CSC 0x00010000 /* connect status change */ 318 #define RH_PS_PESC 0x00020000 /* port enable status change */ 319 #define RH_PS_PSSC 0x00040000 /* port suspend status change */ 320 #define RH_PS_OCIC 0x00080000 /* over current indicator change */ 321 #define RH_PS_PRSC 0x00100000 /* port reset status change */ 322 323 /* roothub.status bits */ 324 #define RH_HS_LPS 0x00000001 /* local power status */ 325 #define RH_HS_OCI 0x00000002 /* over current indicator */ 326 #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ 327 #define RH_HS_LPSC 0x00010000 /* local power status change */ 328 #define RH_HS_OCIC 0x00020000 /* over current indicator change */ 329 #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ 330 331 /* roothub.b masks */ 332 #define RH_B_DR 0x0000ffff /* device removable flags */ 333 #define RH_B_PPCM 0xffff0000 /* port power control mask */ 334 335 /* roothub.a masks */ 336 #define RH_A_NDP (0xff << 0) /* number of downstream ports */ 337 #define RH_A_PSM (1 << 8) /* power switching mode */ 338 #define RH_A_NPS (1 << 9) /* no power switching */ 339 #define RH_A_DT (1 << 10) /* device type (mbz) */ 340 #define RH_A_OCPM (1 << 11) /* over current protection mode */ 341 #define RH_A_NOCP (1 << 12) /* no over current protection */ 342 #define RH_A_POTPGT (0xff << 24) /* power on to power good time */ 343 344 /* urb */ 345 #define N_URB_TD 48 346 typedef struct 347 { 348 ed_t *ed; 349 __u16 length; /* number of tds associated with this request */ 350 __u16 td_cnt; /* number of tds already serviced */ 351 struct usb_device *dev; 352 int state; 353 unsigned long pipe; 354 void *transfer_buffer; 355 int transfer_buffer_length; 356 int interval; 357 int actual_length; 358 int finished; 359 td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ 360 } urb_priv_t; 361 #define URB_DEL 1 362 363 #define NUM_EDS 32 /* num of preallocated endpoint descriptors */ 364 365 #define NUM_TD 64 /* we need more TDs than EDs */ 366 367 #define NUM_INT_DEVS 8 /* num of ohci_dev structs for int endpoints */ 368 369 typedef struct ohci_device { 370 ed_t ed[NUM_EDS] __aligned(ED_ALIGNMENT); 371 td_t tds[NUM_TD] __aligned(TD_ALIGNMENT); 372 int ed_cnt; 373 int devnum; 374 } ohci_dev_t; 375 376 /* 377 * This is the full ohci controller description 378 * 379 * Note how the "proper" USB information is just 380 * a subset of what the full implementation needs. (Linus) 381 */ 382 383 384 typedef struct ohci { 385 /* this allocates EDs for all possible endpoints */ 386 struct ohci_device ohci_dev __aligned(TD_ALIGNMENT); 387 struct ohci_device int_dev[NUM_INT_DEVS] __aligned(TD_ALIGNMENT); 388 struct ohci_hcca *hcca; /* hcca */ 389 /*dma_addr_t hcca_dma;*/ 390 391 int irq; 392 int disabled; /* e.g. got a UE, we're hung */ 393 int sleeping; 394 unsigned long flags; /* for HC bugs */ 395 396 struct ohci_regs *regs; /* OHCI controller's memory */ 397 398 int ohci_int_load[32]; /* load of the 32 Interrupt Chains (for load balancing)*/ 399 ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ 400 ed_t *ed_bulktail; /* last endpoint of bulk list */ 401 ed_t *ed_controltail; /* last endpoint of control list */ 402 int intrstatus; 403 __u32 hc_control; /* copy of the hc control reg */ 404 struct usb_device *dev[32]; 405 struct virt_root_hub rh; 406 407 const char *slot_name; 408 } ohci_t; 409 410 #if CONFIG_IS_ENABLED(DM_USB) 411 extern struct dm_usb_ops ohci_usb_ops; 412 413 int ohci_register(struct udevice *dev, struct ohci_regs *regs); 414 int ohci_deregister(struct udevice *dev); 415 #endif 416