1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * USB HOST XHCI Controller stack
4 *
5 * Based on xHCI host controller driver in linux-kernel
6 * by Sarah Sharp.
7 *
8 * Copyright (C) 2008 Intel Corp.
9 * Author: Sarah Sharp
10 *
11 * Copyright (C) 2013 Samsung Electronics Co.Ltd
12 * Authors: Vivek Gautam <gautam.vivek@samsung.com>
13 * Vikas Sajjan <vikas.sajjan@samsung.com>
14 */
15
16 #include <common.h>
17 #include <cpu_func.h>
18 #include <dm.h>
19 #include <log.h>
20 #include <asm/byteorder.h>
21 #include <usb.h>
22 #include <malloc.h>
23 #include <asm/cache.h>
24 #include <linux/bug.h>
25 #include <linux/errno.h>
26
27 #include <usb/xhci.h>
28
29 #define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE
30 /**
31 * flushes the address passed till the length
32 *
33 * @param addr pointer to memory region to be flushed
34 * @param len the length of the cache line to be flushed
35 * @return none
36 */
xhci_flush_cache(uintptr_t addr,u32 len)37 void xhci_flush_cache(uintptr_t addr, u32 len)
38 {
39 BUG_ON((void *)addr == NULL || len == 0);
40
41 flush_dcache_range(addr & ~(CACHELINE_SIZE - 1),
42 ALIGN(addr + len, CACHELINE_SIZE));
43 }
44
45 /**
46 * invalidates the address passed till the length
47 *
48 * @param addr pointer to memory region to be invalidates
49 * @param len the length of the cache line to be invalidated
50 * @return none
51 */
xhci_inval_cache(uintptr_t addr,u32 len)52 void xhci_inval_cache(uintptr_t addr, u32 len)
53 {
54 BUG_ON((void *)addr == NULL || len == 0);
55
56 invalidate_dcache_range(addr & ~(CACHELINE_SIZE - 1),
57 ALIGN(addr + len, CACHELINE_SIZE));
58 }
59
60
61 /**
62 * frees the "segment" pointer passed
63 *
64 * @param ptr pointer to "segement" to be freed
65 * @return none
66 */
xhci_segment_free(struct xhci_segment * seg)67 static void xhci_segment_free(struct xhci_segment *seg)
68 {
69 free(seg->trbs);
70 seg->trbs = NULL;
71
72 free(seg);
73 }
74
75 /**
76 * frees the "ring" pointer passed
77 *
78 * @param ptr pointer to "ring" to be freed
79 * @return none
80 */
xhci_ring_free(struct xhci_ring * ring)81 static void xhci_ring_free(struct xhci_ring *ring)
82 {
83 struct xhci_segment *seg;
84 struct xhci_segment *first_seg;
85
86 BUG_ON(!ring);
87
88 first_seg = ring->first_seg;
89 seg = first_seg->next;
90 while (seg != first_seg) {
91 struct xhci_segment *next = seg->next;
92 xhci_segment_free(seg);
93 seg = next;
94 }
95 xhci_segment_free(first_seg);
96
97 free(ring);
98 }
99
100 /**
101 * Free the scratchpad buffer array and scratchpad buffers
102 *
103 * @ctrl host controller data structure
104 * @return none
105 */
xhci_scratchpad_free(struct xhci_ctrl * ctrl)106 static void xhci_scratchpad_free(struct xhci_ctrl *ctrl)
107 {
108 if (!ctrl->scratchpad)
109 return;
110
111 ctrl->dcbaa->dev_context_ptrs[0] = 0;
112
113 free(xhci_bus_to_virt(ctrl, le64_to_cpu(ctrl->scratchpad->sp_array[0])));
114 free(ctrl->scratchpad->sp_array);
115 free(ctrl->scratchpad);
116 ctrl->scratchpad = NULL;
117 }
118
119 /**
120 * frees the "xhci_container_ctx" pointer passed
121 *
122 * @param ptr pointer to "xhci_container_ctx" to be freed
123 * @return none
124 */
xhci_free_container_ctx(struct xhci_container_ctx * ctx)125 static void xhci_free_container_ctx(struct xhci_container_ctx *ctx)
126 {
127 free(ctx->bytes);
128 free(ctx);
129 }
130
131 /**
132 * frees the virtual devices for "xhci_ctrl" pointer passed
133 *
134 * @param ptr pointer to "xhci_ctrl" whose virtual devices are to be freed
135 * @return none
136 */
xhci_free_virt_devices(struct xhci_ctrl * ctrl)137 static void xhci_free_virt_devices(struct xhci_ctrl *ctrl)
138 {
139 int i;
140 int slot_id;
141 struct xhci_virt_device *virt_dev;
142
143 /*
144 * refactored here to loop through all virt_dev
145 * Slot ID 0 is reserved
146 */
147 for (slot_id = 0; slot_id < MAX_HC_SLOTS; slot_id++) {
148 virt_dev = ctrl->devs[slot_id];
149 if (!virt_dev)
150 continue;
151
152 ctrl->dcbaa->dev_context_ptrs[slot_id] = 0;
153
154 for (i = 0; i < 31; ++i)
155 if (virt_dev->eps[i].ring)
156 xhci_ring_free(virt_dev->eps[i].ring);
157
158 if (virt_dev->in_ctx)
159 xhci_free_container_ctx(virt_dev->in_ctx);
160 if (virt_dev->out_ctx)
161 xhci_free_container_ctx(virt_dev->out_ctx);
162
163 free(virt_dev);
164 /* make sure we are pointing to NULL */
165 ctrl->devs[slot_id] = NULL;
166 }
167 }
168
169 /**
170 * frees all the memory allocated
171 *
172 * @param ptr pointer to "xhci_ctrl" to be cleaned up
173 * @return none
174 */
xhci_cleanup(struct xhci_ctrl * ctrl)175 void xhci_cleanup(struct xhci_ctrl *ctrl)
176 {
177 xhci_ring_free(ctrl->event_ring);
178 xhci_ring_free(ctrl->cmd_ring);
179 xhci_scratchpad_free(ctrl);
180 xhci_free_virt_devices(ctrl);
181 free(ctrl->erst.entries);
182 free(ctrl->dcbaa);
183 if (reset_valid(&ctrl->reset))
184 reset_free(&ctrl->reset);
185 memset(ctrl, '\0', sizeof(struct xhci_ctrl));
186 }
187
188 /**
189 * Malloc the aligned memory
190 *
191 * @param size size of memory to be allocated
192 * @return allocates the memory and returns the aligned pointer
193 */
xhci_malloc(unsigned int size)194 static void *xhci_malloc(unsigned int size)
195 {
196 void *ptr;
197 size_t cacheline_size = max(XHCI_ALIGNMENT, CACHELINE_SIZE);
198
199 ptr = memalign(cacheline_size, ALIGN(size, cacheline_size));
200 BUG_ON(!ptr);
201 memset(ptr, '\0', size);
202
203 xhci_flush_cache((uintptr_t)ptr, size);
204
205 return ptr;
206 }
207
208 /**
209 * Make the prev segment point to the next segment.
210 * Change the last TRB in the prev segment to be a Link TRB which points to the
211 * address of the next segment. The caller needs to set any Link TRB
212 * related flags, such as End TRB, Toggle Cycle, and no snoop.
213 *
214 * @param prev pointer to the previous segment
215 * @param next pointer to the next segment
216 * @param link_trbs flag to indicate whether to link the trbs or NOT
217 * @return none
218 */
xhci_link_segments(struct xhci_ctrl * ctrl,struct xhci_segment * prev,struct xhci_segment * next,bool link_trbs)219 static void xhci_link_segments(struct xhci_ctrl *ctrl, struct xhci_segment *prev,
220 struct xhci_segment *next, bool link_trbs)
221 {
222 u32 val;
223 u64 val_64 = 0;
224
225 if (!prev || !next)
226 return;
227 prev->next = next;
228 if (link_trbs) {
229 val_64 = xhci_virt_to_bus(ctrl, next->trbs);
230 prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr =
231 cpu_to_le64(val_64);
232
233 /*
234 * Set the last TRB in the segment to
235 * have a TRB type ID of Link TRB
236 */
237 val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
238 val &= ~TRB_TYPE_BITMASK;
239 val |= TRB_TYPE(TRB_LINK);
240 prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
241 }
242 }
243
244 /**
245 * Initialises the Ring's enqueue,dequeue,enq_seg pointers
246 *
247 * @param ring pointer to the RING to be intialised
248 * @return none
249 */
xhci_initialize_ring_info(struct xhci_ring * ring)250 static void xhci_initialize_ring_info(struct xhci_ring *ring)
251 {
252 /*
253 * The ring is empty, so the enqueue pointer == dequeue pointer
254 */
255 ring->enqueue = ring->first_seg->trbs;
256 ring->enq_seg = ring->first_seg;
257 ring->dequeue = ring->enqueue;
258 ring->deq_seg = ring->first_seg;
259
260 /*
261 * The ring is initialized to 0. The producer must write 1 to the
262 * cycle bit to handover ownership of the TRB, so PCS = 1.
263 * The consumer must compare CCS to the cycle bit to
264 * check ownership, so CCS = 1.
265 */
266 ring->cycle_state = 1;
267 }
268
269 /**
270 * Allocates a generic ring segment from the ring pool, sets the dma address,
271 * initializes the segment to zero, and sets the private next pointer to NULL.
272 * Section 4.11.1.1:
273 * "All components of all Command and Transfer TRBs shall be initialized to '0'"
274 *
275 * @param none
276 * @return pointer to the newly allocated SEGMENT
277 */
xhci_segment_alloc(void)278 static struct xhci_segment *xhci_segment_alloc(void)
279 {
280 struct xhci_segment *seg;
281
282 seg = malloc(sizeof(struct xhci_segment));
283 BUG_ON(!seg);
284
285 seg->trbs = xhci_malloc(SEGMENT_SIZE);
286
287 seg->next = NULL;
288
289 return seg;
290 }
291
292 /**
293 * Create a new ring with zero or more segments.
294 * TODO: current code only uses one-time-allocated single-segment rings
295 * of 1KB anyway, so we might as well get rid of all the segment and
296 * linking code (and maybe increase the size a bit, e.g. 4KB).
297 *
298 *
299 * Link each segment together into a ring.
300 * Set the end flag and the cycle toggle bit on the last segment.
301 * See section 4.9.2 and figures 15 and 16 of XHCI spec rev1.0.
302 *
303 * @param num_segs number of segments in the ring
304 * @param link_trbs flag to indicate whether to link the trbs or NOT
305 * @return pointer to the newly created RING
306 */
xhci_ring_alloc(struct xhci_ctrl * ctrl,unsigned int num_segs,bool link_trbs)307 struct xhci_ring *xhci_ring_alloc(struct xhci_ctrl *ctrl, unsigned int num_segs,
308 bool link_trbs)
309 {
310 struct xhci_ring *ring;
311 struct xhci_segment *prev;
312
313 ring = malloc(sizeof(struct xhci_ring));
314 BUG_ON(!ring);
315
316 if (num_segs == 0)
317 return ring;
318
319 ring->first_seg = xhci_segment_alloc();
320 BUG_ON(!ring->first_seg);
321
322 num_segs--;
323
324 prev = ring->first_seg;
325 while (num_segs > 0) {
326 struct xhci_segment *next;
327
328 next = xhci_segment_alloc();
329 BUG_ON(!next);
330
331 xhci_link_segments(ctrl, prev, next, link_trbs);
332
333 prev = next;
334 num_segs--;
335 }
336 xhci_link_segments(ctrl, prev, ring->first_seg, link_trbs);
337 if (link_trbs) {
338 /* See section 4.9.2.1 and 6.4.4.1 */
339 prev->trbs[TRBS_PER_SEGMENT-1].link.control |=
340 cpu_to_le32(LINK_TOGGLE);
341 }
342 xhci_initialize_ring_info(ring);
343
344 return ring;
345 }
346
347 /**
348 * Set up the scratchpad buffer array and scratchpad buffers
349 *
350 * @ctrl host controller data structure
351 * @return -ENOMEM if buffer allocation fails, 0 on success
352 */
xhci_scratchpad_alloc(struct xhci_ctrl * ctrl)353 static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl)
354 {
355 struct xhci_hccr *hccr = ctrl->hccr;
356 struct xhci_hcor *hcor = ctrl->hcor;
357 struct xhci_scratchpad *scratchpad;
358 uint64_t val_64;
359 int num_sp;
360 uint32_t page_size;
361 void *buf;
362 int i;
363
364 num_sp = HCS_MAX_SCRATCHPAD(xhci_readl(&hccr->cr_hcsparams2));
365 if (!num_sp)
366 return 0;
367
368 scratchpad = malloc(sizeof(*scratchpad));
369 if (!scratchpad)
370 goto fail_sp;
371 ctrl->scratchpad = scratchpad;
372
373 scratchpad->sp_array = xhci_malloc(num_sp * sizeof(u64));
374 if (!scratchpad->sp_array)
375 goto fail_sp2;
376
377 val_64 = xhci_virt_to_bus(ctrl, scratchpad->sp_array);
378 ctrl->dcbaa->dev_context_ptrs[0] = cpu_to_le64(val_64);
379
380 xhci_flush_cache((uintptr_t)&ctrl->dcbaa->dev_context_ptrs[0],
381 sizeof(ctrl->dcbaa->dev_context_ptrs[0]));
382
383 page_size = xhci_readl(&hcor->or_pagesize) & 0xffff;
384 for (i = 0; i < 16; i++) {
385 if ((0x1 & page_size) != 0)
386 break;
387 page_size = page_size >> 1;
388 }
389 BUG_ON(i == 16);
390
391 page_size = 1 << (i + 12);
392 buf = memalign(page_size, num_sp * page_size);
393 if (!buf)
394 goto fail_sp3;
395 memset(buf, '\0', num_sp * page_size);
396 xhci_flush_cache((uintptr_t)buf, num_sp * page_size);
397
398 for (i = 0; i < num_sp; i++) {
399 val_64 = xhci_virt_to_bus(ctrl, buf + i * page_size);
400 scratchpad->sp_array[i] = cpu_to_le64(val_64);
401 }
402
403 xhci_flush_cache((uintptr_t)scratchpad->sp_array,
404 sizeof(u64) * num_sp);
405
406 return 0;
407
408 fail_sp3:
409 free(scratchpad->sp_array);
410
411 fail_sp2:
412 free(scratchpad);
413 ctrl->scratchpad = NULL;
414
415 fail_sp:
416 return -ENOMEM;
417 }
418
419 /**
420 * Allocates the Container context
421 *
422 * @param ctrl Host controller data structure
423 * @param type type of XHCI Container Context
424 * @return NULL if failed else pointer to the context on success
425 */
426 static struct xhci_container_ctx
xhci_alloc_container_ctx(struct xhci_ctrl * ctrl,int type)427 *xhci_alloc_container_ctx(struct xhci_ctrl *ctrl, int type)
428 {
429 struct xhci_container_ctx *ctx;
430
431 ctx = malloc(sizeof(struct xhci_container_ctx));
432 BUG_ON(!ctx);
433
434 BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
435 ctx->type = type;
436 ctx->size = (MAX_EP_CTX_NUM + 1) *
437 CTX_SIZE(xhci_readl(&ctrl->hccr->cr_hccparams));
438 if (type == XHCI_CTX_TYPE_INPUT)
439 ctx->size += CTX_SIZE(xhci_readl(&ctrl->hccr->cr_hccparams));
440
441 ctx->bytes = xhci_malloc(ctx->size);
442
443 return ctx;
444 }
445
446 /**
447 * Allocating virtual device
448 *
449 * @param udev pointer to USB deivce structure
450 * @return 0 on success else -1 on failure
451 */
xhci_alloc_virt_device(struct xhci_ctrl * ctrl,unsigned int slot_id)452 int xhci_alloc_virt_device(struct xhci_ctrl *ctrl, unsigned int slot_id)
453 {
454 u64 byte_64 = 0;
455 struct xhci_virt_device *virt_dev;
456
457 /* Slot ID 0 is reserved */
458 if (ctrl->devs[slot_id]) {
459 printf("Virt dev for slot[%d] already allocated\n", slot_id);
460 return -EEXIST;
461 }
462
463 ctrl->devs[slot_id] = malloc(sizeof(struct xhci_virt_device));
464
465 if (!ctrl->devs[slot_id]) {
466 puts("Failed to allocate virtual device\n");
467 return -ENOMEM;
468 }
469
470 memset(ctrl->devs[slot_id], 0, sizeof(struct xhci_virt_device));
471 virt_dev = ctrl->devs[slot_id];
472
473 /* Allocate the (output) device context that will be used in the HC. */
474 virt_dev->out_ctx = xhci_alloc_container_ctx(ctrl,
475 XHCI_CTX_TYPE_DEVICE);
476 if (!virt_dev->out_ctx) {
477 puts("Failed to allocate out context for virt dev\n");
478 return -ENOMEM;
479 }
480
481 /* Allocate the (input) device context for address device command */
482 virt_dev->in_ctx = xhci_alloc_container_ctx(ctrl,
483 XHCI_CTX_TYPE_INPUT);
484 if (!virt_dev->in_ctx) {
485 puts("Failed to allocate in context for virt dev\n");
486 return -ENOMEM;
487 }
488
489 /* Allocate endpoint 0 ring */
490 virt_dev->eps[0].ring = xhci_ring_alloc(ctrl, 1, true);
491
492 byte_64 = xhci_virt_to_bus(ctrl, virt_dev->out_ctx->bytes);
493
494 /* Point to output device context in dcbaa. */
495 ctrl->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(byte_64);
496
497 xhci_flush_cache((uintptr_t)&ctrl->dcbaa->dev_context_ptrs[slot_id],
498 sizeof(__le64));
499 return 0;
500 }
501
502 /**
503 * Allocates the necessary data structures
504 * for XHCI host controller
505 *
506 * @param ctrl Host controller data structure
507 * @param hccr pointer to HOST Controller Control Registers
508 * @param hcor pointer to HOST Controller Operational Registers
509 * @return 0 if successful else -1 on failure
510 */
xhci_mem_init(struct xhci_ctrl * ctrl,struct xhci_hccr * hccr,struct xhci_hcor * hcor)511 int xhci_mem_init(struct xhci_ctrl *ctrl, struct xhci_hccr *hccr,
512 struct xhci_hcor *hcor)
513 {
514 uint64_t val_64;
515 uint64_t trb_64;
516 uint32_t val;
517 uint64_t deq;
518 int i;
519 struct xhci_segment *seg;
520
521 /* DCBAA initialization */
522 ctrl->dcbaa = xhci_malloc(sizeof(struct xhci_device_context_array));
523 if (ctrl->dcbaa == NULL) {
524 puts("unable to allocate DCBA\n");
525 return -ENOMEM;
526 }
527
528 val_64 = xhci_virt_to_bus(ctrl, ctrl->dcbaa);
529 /* Set the pointer in DCBAA register */
530 xhci_writeq(&hcor->or_dcbaap, val_64);
531
532 /* Command ring control pointer register initialization */
533 ctrl->cmd_ring = xhci_ring_alloc(ctrl, 1, true);
534
535 /* Set the address in the Command Ring Control register */
536 trb_64 = xhci_virt_to_bus(ctrl, ctrl->cmd_ring->first_seg->trbs);
537 val_64 = xhci_readq(&hcor->or_crcr);
538 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
539 (trb_64 & (u64) ~CMD_RING_RSVD_BITS) |
540 ctrl->cmd_ring->cycle_state;
541 xhci_writeq(&hcor->or_crcr, val_64);
542
543 /* write the address of db register */
544 val = xhci_readl(&hccr->cr_dboff);
545 val &= DBOFF_MASK;
546 ctrl->dba = (struct xhci_doorbell_array *)((char *)hccr + val);
547
548 /* write the address of runtime register */
549 val = xhci_readl(&hccr->cr_rtsoff);
550 val &= RTSOFF_MASK;
551 ctrl->run_regs = (struct xhci_run_regs *)((char *)hccr + val);
552
553 /* writting the address of ir_set structure */
554 ctrl->ir_set = &ctrl->run_regs->ir_set[0];
555
556 /* Event ring does not maintain link TRB */
557 ctrl->event_ring = xhci_ring_alloc(ctrl, ERST_NUM_SEGS, false);
558 ctrl->erst.entries = xhci_malloc(sizeof(struct xhci_erst_entry) *
559 ERST_NUM_SEGS);
560
561 ctrl->erst.num_entries = ERST_NUM_SEGS;
562
563 for (val = 0, seg = ctrl->event_ring->first_seg;
564 val < ERST_NUM_SEGS;
565 val++) {
566 struct xhci_erst_entry *entry = &ctrl->erst.entries[val];
567 trb_64 = xhci_virt_to_bus(ctrl, seg->trbs);
568 entry->seg_addr = cpu_to_le64(trb_64);
569 entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
570 entry->rsvd = 0;
571 seg = seg->next;
572 }
573 xhci_flush_cache((uintptr_t)ctrl->erst.entries,
574 ERST_NUM_SEGS * sizeof(struct xhci_erst_entry));
575
576 deq = xhci_virt_to_bus(ctrl, ctrl->event_ring->dequeue);
577
578 /* Update HC event ring dequeue pointer */
579 xhci_writeq(&ctrl->ir_set->erst_dequeue,
580 (u64)deq & (u64)~ERST_PTR_MASK);
581
582 /* set ERST count with the number of entries in the segment table */
583 val = xhci_readl(&ctrl->ir_set->erst_size);
584 val &= ERST_SIZE_MASK;
585 val |= ERST_NUM_SEGS;
586 xhci_writel(&ctrl->ir_set->erst_size, val);
587
588 /* this is the event ring segment table pointer */
589 val_64 = xhci_readq(&ctrl->ir_set->erst_base);
590 val_64 &= ERST_PTR_MASK;
591 val_64 |= xhci_virt_to_bus(ctrl, ctrl->erst.entries) & ~ERST_PTR_MASK;
592
593 xhci_writeq(&ctrl->ir_set->erst_base, val_64);
594
595 /* set up the scratchpad buffer array and scratchpad buffers */
596 xhci_scratchpad_alloc(ctrl);
597
598 /* initializing the virtual devices to NULL */
599 for (i = 0; i < MAX_HC_SLOTS; ++i)
600 ctrl->devs[i] = NULL;
601
602 /*
603 * Just Zero'ing this register completely,
604 * or some spurious Device Notification Events
605 * might screw things here.
606 */
607 xhci_writel(&hcor->or_dnctrl, 0x0);
608
609 return 0;
610 }
611
612 /**
613 * Give the input control context for the passed container context
614 *
615 * @param ctx pointer to the context
616 * @return pointer to the Input control context data
617 */
618 struct xhci_input_control_ctx
xhci_get_input_control_ctx(struct xhci_container_ctx * ctx)619 *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx)
620 {
621 BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT);
622 return (struct xhci_input_control_ctx *)ctx->bytes;
623 }
624
625 /**
626 * Give the slot context for the passed container context
627 *
628 * @param ctrl Host controller data structure
629 * @param ctx pointer to the context
630 * @return pointer to the slot control context data
631 */
xhci_get_slot_ctx(struct xhci_ctrl * ctrl,struct xhci_container_ctx * ctx)632 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_ctrl *ctrl,
633 struct xhci_container_ctx *ctx)
634 {
635 if (ctx->type == XHCI_CTX_TYPE_DEVICE)
636 return (struct xhci_slot_ctx *)ctx->bytes;
637
638 return (struct xhci_slot_ctx *)
639 (ctx->bytes + CTX_SIZE(xhci_readl(&ctrl->hccr->cr_hccparams)));
640 }
641
642 /**
643 * Gets the EP context from based on the ep_index
644 *
645 * @param ctrl Host controller data structure
646 * @param ctx context container
647 * @param ep_index index of the endpoint
648 * @return pointer to the End point context
649 */
xhci_get_ep_ctx(struct xhci_ctrl * ctrl,struct xhci_container_ctx * ctx,unsigned int ep_index)650 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_ctrl *ctrl,
651 struct xhci_container_ctx *ctx,
652 unsigned int ep_index)
653 {
654 /* increment ep index by offset of start of ep ctx array */
655 ep_index++;
656 if (ctx->type == XHCI_CTX_TYPE_INPUT)
657 ep_index++;
658
659 return (struct xhci_ep_ctx *)
660 (ctx->bytes +
661 (ep_index * CTX_SIZE(xhci_readl(&ctrl->hccr->cr_hccparams))));
662 }
663
664 /**
665 * Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
666 * Useful when you want to change one particular aspect of the endpoint
667 * and then issue a configure endpoint command.
668 *
669 * @param ctrl Host controller data structure
670 * @param in_ctx contains the input context
671 * @param out_ctx contains the input context
672 * @param ep_index index of the end point
673 * @return none
674 */
xhci_endpoint_copy(struct xhci_ctrl * ctrl,struct xhci_container_ctx * in_ctx,struct xhci_container_ctx * out_ctx,unsigned int ep_index)675 void xhci_endpoint_copy(struct xhci_ctrl *ctrl,
676 struct xhci_container_ctx *in_ctx,
677 struct xhci_container_ctx *out_ctx,
678 unsigned int ep_index)
679 {
680 struct xhci_ep_ctx *out_ep_ctx;
681 struct xhci_ep_ctx *in_ep_ctx;
682
683 out_ep_ctx = xhci_get_ep_ctx(ctrl, out_ctx, ep_index);
684 in_ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
685
686 in_ep_ctx->ep_info = out_ep_ctx->ep_info;
687 in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
688 in_ep_ctx->deq = out_ep_ctx->deq;
689 in_ep_ctx->tx_info = out_ep_ctx->tx_info;
690 }
691
692 /**
693 * Copy output xhci_slot_ctx to the input xhci_slot_ctx.
694 * Useful when you want to change one particular aspect of the endpoint
695 * and then issue a configure endpoint command.
696 * Only the context entries field matters, but
697 * we'll copy the whole thing anyway.
698 *
699 * @param ctrl Host controller data structure
700 * @param in_ctx contains the inpout context
701 * @param out_ctx contains the inpout context
702 * @return none
703 */
xhci_slot_copy(struct xhci_ctrl * ctrl,struct xhci_container_ctx * in_ctx,struct xhci_container_ctx * out_ctx)704 void xhci_slot_copy(struct xhci_ctrl *ctrl, struct xhci_container_ctx *in_ctx,
705 struct xhci_container_ctx *out_ctx)
706 {
707 struct xhci_slot_ctx *in_slot_ctx;
708 struct xhci_slot_ctx *out_slot_ctx;
709
710 in_slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
711 out_slot_ctx = xhci_get_slot_ctx(ctrl, out_ctx);
712
713 in_slot_ctx->dev_info = out_slot_ctx->dev_info;
714 in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
715 in_slot_ctx->tt_info = out_slot_ctx->tt_info;
716 in_slot_ctx->dev_state = out_slot_ctx->dev_state;
717 }
718
719 /**
720 * Setup an xHCI virtual device for a Set Address command
721 *
722 * @param udev pointer to the Device Data Structure
723 * @return returns negative value on failure else 0 on success
724 */
xhci_setup_addressable_virt_dev(struct xhci_ctrl * ctrl,struct usb_device * udev,int hop_portnr)725 void xhci_setup_addressable_virt_dev(struct xhci_ctrl *ctrl,
726 struct usb_device *udev, int hop_portnr)
727 {
728 struct xhci_virt_device *virt_dev;
729 struct xhci_ep_ctx *ep0_ctx;
730 struct xhci_slot_ctx *slot_ctx;
731 u32 port_num = 0;
732 u64 trb_64 = 0;
733 int slot_id = udev->slot_id;
734 int speed = udev->speed;
735 int route = 0;
736 #if CONFIG_IS_ENABLED(DM_USB)
737 struct usb_device *dev = udev;
738 struct usb_hub_device *hub;
739 #endif
740
741 virt_dev = ctrl->devs[slot_id];
742
743 BUG_ON(!virt_dev);
744
745 /* Extract the EP0 and Slot Ctrl */
746 ep0_ctx = xhci_get_ep_ctx(ctrl, virt_dev->in_ctx, 0);
747 slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->in_ctx);
748
749 /* Only the control endpoint is valid - one endpoint context */
750 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
751
752 #if CONFIG_IS_ENABLED(DM_USB)
753 /* Calculate the route string for this device */
754 port_num = dev->portnr;
755 while (!usb_hub_is_root_hub(dev->dev)) {
756 hub = dev_get_uclass_priv(dev->dev);
757 /*
758 * Each hub in the topology is expected to have no more than
759 * 15 ports in order for the route string of a device to be
760 * unique. SuperSpeed hubs are restricted to only having 15
761 * ports, but FS/LS/HS hubs are not. The xHCI specification
762 * says that if the port number the device is greater than 15,
763 * that portion of the route string shall be set to 15.
764 */
765 if (port_num > 15)
766 port_num = 15;
767 route |= port_num << (hub->hub_depth * 4);
768 dev = dev_get_parent_priv(dev->dev);
769 port_num = dev->portnr;
770 dev = dev_get_parent_priv(dev->dev->parent);
771 }
772
773 debug("route string %x\n", route);
774 #endif
775 slot_ctx->dev_info |= cpu_to_le32(route);
776
777 switch (speed) {
778 case USB_SPEED_SUPER:
779 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
780 break;
781 case USB_SPEED_HIGH:
782 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
783 break;
784 case USB_SPEED_FULL:
785 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
786 break;
787 case USB_SPEED_LOW:
788 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
789 break;
790 default:
791 /* Speed was set earlier, this shouldn't happen. */
792 BUG();
793 }
794
795 #if CONFIG_IS_ENABLED(DM_USB)
796 /* Set up TT fields to support FS/LS devices */
797 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) {
798 struct udevice *parent = udev->dev;
799
800 dev = udev;
801 do {
802 port_num = dev->portnr;
803 dev = dev_get_parent_priv(parent);
804 if (usb_hub_is_root_hub(dev->dev))
805 break;
806 parent = dev->dev->parent;
807 } while (dev->speed != USB_SPEED_HIGH);
808
809 if (!usb_hub_is_root_hub(dev->dev)) {
810 hub = dev_get_uclass_priv(dev->dev);
811 if (hub->tt.multi)
812 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
813 slot_ctx->tt_info |= cpu_to_le32(TT_PORT(port_num));
814 slot_ctx->tt_info |= cpu_to_le32(TT_SLOT(dev->slot_id));
815 }
816 }
817 #endif
818
819 port_num = hop_portnr;
820 debug("port_num = %d\n", port_num);
821
822 slot_ctx->dev_info2 |=
823 cpu_to_le32(((port_num & ROOT_HUB_PORT_MASK) <<
824 ROOT_HUB_PORT_SHIFT));
825
826 /* Step 4 - ring already allocated */
827 /* Step 5 */
828 ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
829 debug("SPEED = %d\n", speed);
830
831 switch (speed) {
832 case USB_SPEED_SUPER:
833 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(512));
834 debug("Setting Packet size = 512bytes\n");
835 break;
836 case USB_SPEED_HIGH:
837 /* USB core guesses at a 64-byte max packet first for FS devices */
838 case USB_SPEED_FULL:
839 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(64));
840 debug("Setting Packet size = 64bytes\n");
841 break;
842 case USB_SPEED_LOW:
843 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(8));
844 debug("Setting Packet size = 8bytes\n");
845 break;
846 default:
847 /* New speed? */
848 BUG();
849 }
850
851 /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
852 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3));
853
854 trb_64 = xhci_virt_to_bus(ctrl, virt_dev->eps[0].ring->first_seg->trbs);
855 ep0_ctx->deq = cpu_to_le64(trb_64 | virt_dev->eps[0].ring->cycle_state);
856
857 /*
858 * xHCI spec 6.2.3:
859 * software shall set 'Average TRB Length' to 8 for control endpoints.
860 */
861 ep0_ctx->tx_info = cpu_to_le32(EP_AVG_TRB_LENGTH(8));
862
863 /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
864
865 xhci_flush_cache((uintptr_t)ep0_ctx, sizeof(struct xhci_ep_ctx));
866 xhci_flush_cache((uintptr_t)slot_ctx, sizeof(struct xhci_slot_ctx));
867 }
868