1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Nexell Co., Ltd.
4 *
5 * Author: junghyun, kim <jhkim@nexell.co.kr>
6 *
7 * Copyright (C) 2020 Stefan Bosch <stefan_b@posteo.net>
8 */
9
10 #include <config.h>
11 #include <common.h>
12 #include <command.h>
13 #include <dm.h>
14 #include <mapmem.h>
15 #include <malloc.h>
16 #include <linux/compat.h>
17 #include <linux/err.h>
18 #include <video.h> /* For struct video_uc_plat */
19 #include <video_fb.h>
20 #include <lcd.h>
21 #include <asm/global_data.h>
22 #include <asm/io.h>
23 #include <asm/arch/display.h>
24 #include <asm/arch/display_dev.h>
25 #include "videomodes.h"
26
27 DECLARE_GLOBAL_DATA_PTR;
28
29 #if !defined(CONFIG_DM) && !defined(CONFIG_OF_CONTROL)
30 static struct nx_display_dev *dp_dev;
31 #endif
32
33 static char *const dp_dev_str[] = {
34 [DP_DEVICE_RESCONV] = "RESCONV",
35 [DP_DEVICE_RGBLCD] = "LCD",
36 [DP_DEVICE_HDMI] = "HDMI",
37 [DP_DEVICE_MIPI] = "MiPi",
38 [DP_DEVICE_LVDS] = "LVDS",
39 [DP_DEVICE_CVBS] = "TVOUT",
40 [DP_DEVICE_DP0] = "DP0",
41 [DP_DEVICE_DP1] = "DP1",
42 };
43
44 #if CONFIG_IS_ENABLED(OF_CONTROL)
nx_display_parse_dp_sync(ofnode node,struct dp_sync_info * sync)45 static void nx_display_parse_dp_sync(ofnode node, struct dp_sync_info *sync)
46 {
47 sync->h_active_len = ofnode_read_s32_default(node, "h_active_len", 0);
48 sync->h_sync_width = ofnode_read_s32_default(node, "h_sync_width", 0);
49 sync->h_back_porch = ofnode_read_s32_default(node, "h_back_porch", 0);
50 sync->h_front_porch = ofnode_read_s32_default(node, "h_front_porch", 0);
51 sync->h_sync_invert = ofnode_read_s32_default(node, "h_sync_invert", 0);
52 sync->v_active_len = ofnode_read_s32_default(node, "v_active_len", 0);
53 sync->v_sync_width = ofnode_read_s32_default(node, "v_sync_width", 0);
54 sync->v_back_porch = ofnode_read_s32_default(node, "v_back_porch", 0);
55 sync->v_front_porch = ofnode_read_s32_default(node, "v_front_porch", 0);
56 sync->v_sync_invert = ofnode_read_s32_default(node, "v_sync_invert", 0);
57 sync->pixel_clock_hz = ofnode_read_s32_default(node, "pixel_clock_hz", 0);
58
59 debug("DP: sync ->\n");
60 debug("ha:%d, hs:%d, hb:%d, hf:%d, hi:%d\n",
61 sync->h_active_len, sync->h_sync_width,
62 sync->h_back_porch, sync->h_front_porch, sync->h_sync_invert);
63 debug("va:%d, vs:%d, vb:%d, vf:%d, vi:%d\n",
64 sync->v_active_len, sync->v_sync_width,
65 sync->v_back_porch, sync->v_front_porch, sync->v_sync_invert);
66 }
67
nx_display_parse_dp_ctrl(ofnode node,struct dp_ctrl_info * ctrl)68 static void nx_display_parse_dp_ctrl(ofnode node, struct dp_ctrl_info *ctrl)
69 {
70 /* clock gen */
71 ctrl->clk_src_lv0 = ofnode_read_s32_default(node, "clk_src_lv0", 0);
72 ctrl->clk_div_lv0 = ofnode_read_s32_default(node, "clk_div_lv0", 0);
73 ctrl->clk_src_lv1 = ofnode_read_s32_default(node, "clk_src_lv1", 0);
74 ctrl->clk_div_lv1 = ofnode_read_s32_default(node, "clk_div_lv1", 0);
75
76 /* scan format */
77 ctrl->interlace = ofnode_read_s32_default(node, "interlace", 0);
78
79 /* syncgen format */
80 ctrl->out_format = ofnode_read_s32_default(node, "out_format", 0);
81 ctrl->invert_field = ofnode_read_s32_default(node, "invert_field", 0);
82 ctrl->swap_RB = ofnode_read_s32_default(node, "swap_RB", 0);
83 ctrl->yc_order = ofnode_read_s32_default(node, "yc_order", 0);
84
85 /* extern sync delay */
86 ctrl->delay_mask = ofnode_read_s32_default(node, "delay_mask", 0);
87 ctrl->d_rgb_pvd = ofnode_read_s32_default(node, "d_rgb_pvd", 0);
88 ctrl->d_hsync_cp1 = ofnode_read_s32_default(node, "d_hsync_cp1", 0);
89 ctrl->d_vsync_fram = ofnode_read_s32_default(node, "d_vsync_fram", 0);
90 ctrl->d_de_cp2 = ofnode_read_s32_default(node, "d_de_cp2", 0);
91
92 /* extern sync delay */
93 ctrl->vs_start_offset =
94 ofnode_read_s32_default(node, "vs_start_offset", 0);
95 ctrl->vs_end_offset = ofnode_read_s32_default(node, "vs_end_offset", 0);
96 ctrl->ev_start_offset =
97 ofnode_read_s32_default(node, "ev_start_offset", 0);
98 ctrl->ev_end_offset = ofnode_read_s32_default(node, "ev_end_offset", 0);
99
100 /* pad clock seletor */
101 ctrl->vck_select = ofnode_read_s32_default(node, "vck_select", 0);
102 ctrl->clk_inv_lv0 = ofnode_read_s32_default(node, "clk_inv_lv0", 0);
103 ctrl->clk_delay_lv0 = ofnode_read_s32_default(node, "clk_delay_lv0", 0);
104 ctrl->clk_inv_lv1 = ofnode_read_s32_default(node, "clk_inv_lv1", 0);
105 ctrl->clk_delay_lv1 = ofnode_read_s32_default(node, "clk_delay_lv1", 0);
106 ctrl->clk_sel_div1 = ofnode_read_s32_default(node, "clk_sel_div1", 0);
107
108 debug("DP: ctrl [%s] ->\n",
109 ctrl->interlace ? "Interlace" : " Progressive");
110 debug("cs0:%d, cd0:%d, cs1:%d, cd1:%d\n",
111 ctrl->clk_src_lv0, ctrl->clk_div_lv0,
112 ctrl->clk_src_lv1, ctrl->clk_div_lv1);
113 debug("fmt:0x%x, inv:%d, swap:%d, yb:0x%x\n",
114 ctrl->out_format, ctrl->invert_field,
115 ctrl->swap_RB, ctrl->yc_order);
116 debug("dm:0x%x, drp:%d, dhs:%d, dvs:%d, dde:0x%x\n",
117 ctrl->delay_mask, ctrl->d_rgb_pvd,
118 ctrl->d_hsync_cp1, ctrl->d_vsync_fram, ctrl->d_de_cp2);
119 debug("vss:%d, vse:%d, evs:%d, eve:%d\n",
120 ctrl->vs_start_offset, ctrl->vs_end_offset,
121 ctrl->ev_start_offset, ctrl->ev_end_offset);
122 debug("sel:%d, i0:%d, d0:%d, i1:%d, d1:%d, s1:%d\n",
123 ctrl->vck_select, ctrl->clk_inv_lv0, ctrl->clk_delay_lv0,
124 ctrl->clk_inv_lv1, ctrl->clk_delay_lv1, ctrl->clk_sel_div1);
125 }
126
nx_display_parse_dp_top_layer(ofnode node,struct dp_plane_top * top)127 static void nx_display_parse_dp_top_layer(ofnode node, struct dp_plane_top *top)
128 {
129 top->screen_width = ofnode_read_s32_default(node, "screen_width", 0);
130 top->screen_height = ofnode_read_s32_default(node, "screen_height", 0);
131 top->video_prior = ofnode_read_s32_default(node, "video_prior", 0);
132 top->interlace = ofnode_read_s32_default(node, "interlace", 0);
133 top->back_color = ofnode_read_s32_default(node, "back_color", 0);
134 top->plane_num = DP_PLANS_NUM;
135
136 debug("DP: top [%s] ->\n",
137 top->interlace ? "Interlace" : " Progressive");
138 debug("w:%d, h:%d, prior:%d, bg:0x%x\n",
139 top->screen_width, top->screen_height,
140 top->video_prior, top->back_color);
141 }
142
nx_display_parse_dp_layer(ofnode node,struct dp_plane_info * plane)143 static void nx_display_parse_dp_layer(ofnode node, struct dp_plane_info *plane)
144 {
145 plane->left = ofnode_read_s32_default(node, "left", 0);
146 plane->width = ofnode_read_s32_default(node, "width", 0);
147 plane->top = ofnode_read_s32_default(node, "top", 0);
148 plane->height = ofnode_read_s32_default(node, "height", 0);
149 plane->pixel_byte = ofnode_read_s32_default(node, "pixel_byte", 0);
150 plane->format = ofnode_read_s32_default(node, "format", 0);
151 plane->alpha_on = ofnode_read_s32_default(node, "alpha_on", 0);
152 plane->alpha_depth = ofnode_read_s32_default(node, "alpha", 0);
153 plane->tp_on = ofnode_read_s32_default(node, "tp_on", 0);
154 plane->tp_color = ofnode_read_s32_default(node, "tp_color", 0);
155
156 /* enable layer */
157 if (plane->fb_base)
158 plane->enable = 1;
159 else
160 plane->enable = 0;
161
162 if (plane->fb_base == 0) {
163 printf("fail : dp plane.%d invalid fb base [0x%x] ->\n",
164 plane->layer, plane->fb_base);
165 return;
166 }
167
168 debug("DP: plane.%d [0x%x] ->\n", plane->layer, plane->fb_base);
169 debug("f:0x%x, l:%d, t:%d, %d * %d, bpp:%d, a:%d(%d), t:%d(0x%x)\n",
170 plane->format, plane->left, plane->top, plane->width,
171 plane->height, plane->pixel_byte, plane->alpha_on,
172 plane->alpha_depth, plane->tp_on, plane->tp_color);
173 }
174
nx_display_parse_dp_planes(ofnode node,struct nx_display_dev * dp,struct video_uc_plat * plat)175 static void nx_display_parse_dp_planes(ofnode node,
176 struct nx_display_dev *dp,
177 struct video_uc_plat *plat)
178 {
179 const char *name;
180 ofnode subnode;
181
182 ofnode_for_each_subnode(subnode, node) {
183 name = ofnode_get_name(subnode);
184
185 if (strcmp(name, "layer_top") == 0)
186 nx_display_parse_dp_top_layer(subnode, &dp->top);
187
188 /*
189 * TODO: Is it sure that only one layer is used? Otherwise
190 * fb_base must be different?
191 */
192 if (strcmp(name, "layer_0") == 0) {
193 dp->planes[0].fb_base =
194 (uint)map_sysmem(plat->base, plat->size);
195 debug("%s(): dp->planes[0].fb_base == 0x%x\n", __func__,
196 (uint)dp->planes[0].fb_base);
197 nx_display_parse_dp_layer(subnode, &dp->planes[0]);
198 }
199
200 if (strcmp(name, "layer_1") == 0) {
201 dp->planes[1].fb_base =
202 (uint)map_sysmem(plat->base, plat->size);
203 debug("%s(): dp->planes[1].fb_base == 0x%x\n", __func__,
204 (uint)dp->planes[1].fb_base);
205 nx_display_parse_dp_layer(subnode, &dp->planes[1]);
206 }
207
208 if (strcmp(name, "layer_2") == 0) {
209 dp->planes[2].fb_base =
210 (uint)map_sysmem(plat->base, plat->size);
211 debug("%s(): dp->planes[2].fb_base == 0x%x\n", __func__,
212 (uint)dp->planes[2].fb_base);
213 nx_display_parse_dp_layer(subnode, &dp->planes[2]);
214 }
215 }
216 }
217
nx_display_parse_dp_lvds(ofnode node,struct nx_display_dev * dp)218 static int nx_display_parse_dp_lvds(ofnode node, struct nx_display_dev *dp)
219 {
220 struct dp_lvds_dev *dev = kzalloc(sizeof(*dev), GFP_KERNEL);
221
222 if (!dev) {
223 printf("failed to allocate display LVDS object.\n");
224 return -ENOMEM;
225 }
226
227 dp->device = dev;
228
229 dev->lvds_format = ofnode_read_s32_default(node, "format", 0);
230 dev->pol_inv_hs = ofnode_read_s32_default(node, "pol_inv_hs", 0);
231 dev->pol_inv_vs = ofnode_read_s32_default(node, "pol_inv_vs", 0);
232 dev->pol_inv_de = ofnode_read_s32_default(node, "pol_inv_de", 0);
233 dev->pol_inv_ck = ofnode_read_s32_default(node, "pol_inv_ck", 0);
234 dev->voltage_level = ofnode_read_s32_default(node, "voltage_level", 0);
235
236 if (!dev->voltage_level)
237 dev->voltage_level = DEF_VOLTAGE_LEVEL;
238
239 debug("DP: LVDS -> %s, voltage LV:0x%x\n",
240 dev->lvds_format == DP_LVDS_FORMAT_VESA ? "VESA" :
241 dev->lvds_format == DP_LVDS_FORMAT_JEIDA ? "JEIDA" : "LOC",
242 dev->voltage_level);
243 debug("pol inv hs:%d, vs:%d, de:%d, ck:%d\n",
244 dev->pol_inv_hs, dev->pol_inv_vs,
245 dev->pol_inv_de, dev->pol_inv_ck);
246
247 return 0;
248 }
249
nx_display_parse_dp_rgb(ofnode node,struct nx_display_dev * dp)250 static int nx_display_parse_dp_rgb(ofnode node, struct nx_display_dev *dp)
251 {
252 struct dp_rgb_dev *dev = kzalloc(sizeof(*dev), GFP_KERNEL);
253
254 if (!dev) {
255 printf("failed to allocate display RGB LCD object.\n");
256 return -ENOMEM;
257 }
258 dp->device = dev;
259
260 dev->lcd_mpu_type = ofnode_read_s32_default(node, "lcd_mpu_type", 0);
261
262 debug("DP: RGB -> MPU[%s]\n", dev->lcd_mpu_type ? "O" : "X");
263 return 0;
264 }
265
nx_display_parse_dp_mipi(ofnode node,struct nx_display_dev * dp)266 static int nx_display_parse_dp_mipi(ofnode node, struct nx_display_dev *dp)
267 {
268 struct dp_mipi_dev *dev = kzalloc(sizeof(*dev), GFP_KERNEL);
269
270 if (!dev) {
271 printf("failed to allocate display MiPi object.\n");
272 return -ENOMEM;
273 }
274 dp->device = dev;
275
276 dev->lp_bitrate = ofnode_read_s32_default(node, "lp_bitrate", 0);
277 dev->hs_bitrate = ofnode_read_s32_default(node, "hs_bitrate", 0);
278 dev->lpm_trans = 1;
279 dev->command_mode = 0;
280
281 debug("DP: MIPI ->\n");
282 debug("lp:%dmhz, hs:%dmhz\n", dev->lp_bitrate, dev->hs_bitrate);
283
284 return 0;
285 }
286
nx_display_parse_dp_hdmi(ofnode node,struct nx_display_dev * dp)287 static int nx_display_parse_dp_hdmi(ofnode node, struct nx_display_dev *dp)
288 {
289 struct dp_hdmi_dev *dev = kzalloc(sizeof(*dev), GFP_KERNEL);
290
291 if (!dev) {
292 printf("failed to allocate display HDMI object.\n");
293 return -ENOMEM;
294 }
295 dp->device = dev;
296
297 dev->preset = ofnode_read_s32_default(node, "preset", 0);
298
299 debug("DP: HDMI -> %d\n", dev->preset);
300
301 return 0;
302 }
303
nx_display_parse_dp_lcds(ofnode node,const char * type,struct nx_display_dev * dp)304 static int nx_display_parse_dp_lcds(ofnode node, const char *type,
305 struct nx_display_dev *dp)
306 {
307 if (strcmp(type, "lvds") == 0) {
308 dp->dev_type = DP_DEVICE_LVDS;
309 return nx_display_parse_dp_lvds(node, dp);
310 } else if (strcmp(type, "rgb") == 0) {
311 dp->dev_type = DP_DEVICE_RGBLCD;
312 return nx_display_parse_dp_rgb(node, dp);
313 } else if (strcmp(type, "mipi") == 0) {
314 dp->dev_type = DP_DEVICE_MIPI;
315 return nx_display_parse_dp_mipi(node, dp);
316 } else if (strcmp(type, "hdmi") == 0) {
317 dp->dev_type = DP_DEVICE_HDMI;
318 return nx_display_parse_dp_hdmi(node, dp);
319 }
320
321 printf("%s: node %s unknown display type\n", __func__,
322 ofnode_get_name(node));
323 return -EINVAL;
324
325 return 0;
326 }
327
328 #define DT_SYNC (1 << 0)
329 #define DT_CTRL (1 << 1)
330 #define DT_PLANES (1 << 2)
331 #define DT_DEVICE (1 << 3)
332
nx_display_parse_dt(struct udevice * dev,struct nx_display_dev * dp,struct video_uc_plat * plat)333 static int nx_display_parse_dt(struct udevice *dev,
334 struct nx_display_dev *dp,
335 struct video_uc_plat *plat)
336 {
337 const char *name, *dtype;
338 int ret = 0;
339 unsigned int dt_status = 0;
340 ofnode subnode;
341
342 if (!dev)
343 return -ENODEV;
344
345 dp->module = dev_read_s32_default(dev, "module", -1);
346 if (dp->module == -1)
347 dp->module = dev_read_s32_default(dev, "index", 0);
348
349 dtype = dev_read_string(dev, "lcd-type");
350
351 ofnode_for_each_subnode(subnode, dev_ofnode(dev)) {
352 name = ofnode_get_name(subnode);
353
354 if (strcmp("dp-sync", name) == 0) {
355 dt_status |= DT_SYNC;
356 nx_display_parse_dp_sync(subnode, &dp->sync);
357 }
358
359 if (strcmp("dp-ctrl", name) == 0) {
360 dt_status |= DT_CTRL;
361 nx_display_parse_dp_ctrl(subnode, &dp->ctrl);
362 }
363
364 if (strcmp("dp-planes", name) == 0) {
365 dt_status |= DT_PLANES;
366 nx_display_parse_dp_planes(subnode, dp, plat);
367 }
368
369 if (strcmp("dp-device", name) == 0) {
370 dt_status |= DT_DEVICE;
371 ret = nx_display_parse_dp_lcds(subnode, dtype, dp);
372 }
373 }
374
375 if (dt_status != (DT_SYNC | DT_CTRL | DT_PLANES | DT_DEVICE)) {
376 printf("Not enough DT config for display [0x%x]\n", dt_status);
377 return -ENODEV;
378 }
379
380 return ret;
381 }
382 #endif
383
nx_display_fixup_dp(struct nx_display_dev * dp)384 __weak int nx_display_fixup_dp(struct nx_display_dev *dp)
385 {
386 return 0;
387 }
388
nx_display_setup(void)389 static struct nx_display_dev *nx_display_setup(void)
390 {
391 struct nx_display_dev *dp;
392 int i, ret;
393 int node = 0;
394 struct video_uc_plat *plat = NULL;
395
396 struct udevice *dev;
397
398 /* call driver probe */
399 debug("DT: uclass device call...\n");
400
401 ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
402 if (ret) {
403 debug("%s(): uclass_get_device(UCLASS_VIDEO, 0, &dev) != 0 --> return NULL\n",
404 __func__);
405 return NULL;
406 }
407 plat = dev_get_uclass_plat(dev);
408 if (!dev) {
409 debug("%s(): dev_get_uclass_plat(dev) == NULL --> return NULL\n",
410 __func__);
411 return NULL;
412 }
413 dp = dev_get_priv(dev);
414 if (!dp) {
415 debug("%s(): dev_get_priv(dev) == NULL --> return NULL\n",
416 __func__);
417 return NULL;
418 }
419 node = dev_ofnode(dev).of_offset;
420
421 if (CONFIG_IS_ENABLED(OF_CONTROL)) {
422 ret = nx_display_parse_dt(dev, dp, plat);
423 if (ret)
424 goto err_setup;
425 }
426
427 nx_display_fixup_dp(dp);
428
429 for (i = 0; dp->top.plane_num > i; i++) {
430 dp->planes[i].layer = i;
431 if (dp->planes[i].enable && !dp->fb_plane) {
432 dp->fb_plane = &dp->planes[i];
433 dp->fb_addr = dp->fb_plane->fb_base;
434 dp->depth = dp->fb_plane->pixel_byte;
435 }
436 }
437
438 switch (dp->dev_type) {
439 #ifdef CONFIG_VIDEO_NX_RGB
440 case DP_DEVICE_RGBLCD:
441 nx_rgb_display(dp->module,
442 &dp->sync, &dp->ctrl, &dp->top,
443 dp->planes, (struct dp_rgb_dev *)dp->device);
444 break;
445 #endif
446 #ifdef CONFIG_VIDEO_NX_LVDS
447 case DP_DEVICE_LVDS:
448 nx_lvds_display(dp->module,
449 &dp->sync, &dp->ctrl, &dp->top,
450 dp->planes, (struct dp_lvds_dev *)dp->device);
451 break;
452 #endif
453 #ifdef CONFIG_VIDEO_NX_MIPI
454 case DP_DEVICE_MIPI:
455 nx_mipi_display(dp->module,
456 &dp->sync, &dp->ctrl, &dp->top,
457 dp->planes, (struct dp_mipi_dev *)dp->device);
458 break;
459 #endif
460 #ifdef CONFIG_VIDEO_NX_HDMI
461 case DP_DEVICE_HDMI:
462 nx_hdmi_display(dp->module,
463 &dp->sync, &dp->ctrl, &dp->top,
464 dp->planes, (struct dp_hdmi_dev *)dp->device);
465 break;
466 #endif
467 default:
468 printf("fail : not support lcd type %d !!!\n", dp->dev_type);
469 goto err_setup;
470 };
471
472 printf("LCD: [%s] dp.%d.%d %dx%d %dbpp FB:0x%08x\n",
473 dp_dev_str[dp->dev_type], dp->module, dp->fb_plane->layer,
474 dp->fb_plane->width, dp->fb_plane->height, dp->depth * 8,
475 dp->fb_addr);
476
477 return dp;
478
479 err_setup:
480 kfree(dp);
481
482 return NULL;
483 }
484
485 #if defined CONFIG_LCD
486
487 /* default lcd */
488 struct vidinfo panel_info = {
489 .vl_col = 320, .vl_row = 240, .vl_bpix = 32,
490 };
491
lcd_ctrl_init(void * lcdbase)492 void lcd_ctrl_init(void *lcdbase)
493 {
494 vidinfo_t *pi = &panel_info;
495 struct nx_display_dev *dp;
496 int bpix;
497
498 dp = nx_display_setup();
499 if (!dp)
500 return NULL;
501
502 switch (dp->depth) {
503 case 2:
504 bpix = LCD_COLOR16;
505 break;
506 case 3:
507 case 4:
508 bpix = LCD_COLOR32;
509 break;
510 default:
511 printf("fail : not support LCD bit per pixel %d\n",
512 dp->depth * 8);
513 return NULL;
514 }
515
516 dp->panel_info = pi;
517
518 /* set resolution with config */
519 pi->vl_bpix = bpix;
520 pi->vl_col = dp->fb_plane->width;
521 pi->vl_row = dp->fb_plane->height;
522 pi->priv = dp;
523 gd->fb_base = dp->fb_addr;
524 }
525
lcd_setcolreg(ushort regno,ushort red,ushort green,ushort blue)526 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
527 {
528 }
529
lcd_enable(void)530 __weak void lcd_enable(void)
531 {
532 }
533 #endif
534
nx_display_probe(struct udevice * dev)535 static int nx_display_probe(struct udevice *dev)
536 {
537 struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
538 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
539 struct nx_display_plat *plat = dev_get_plat(dev);
540 static GraphicDevice *graphic_device;
541 char addr[64];
542
543 debug("%s()\n", __func__);
544
545 if (!dev)
546 return -EINVAL;
547
548 if (!uc_plat) {
549 debug("%s(): video_uc_plat *plat == NULL --> return -EINVAL\n",
550 __func__);
551 return -EINVAL;
552 }
553
554 if (!uc_priv) {
555 debug("%s(): video_priv *uc_priv == NULL --> return -EINVAL\n",
556 __func__);
557 return -EINVAL;
558 }
559
560 if (!plat) {
561 debug("%s(): nx_display_plat *plat == NULL --> return -EINVAL\n",
562 __func__);
563 return -EINVAL;
564 }
565
566 struct nx_display_dev *dp;
567 unsigned int pp_index = 0;
568
569 dp = nx_display_setup();
570 if (!dp) {
571 debug("%s(): nx_display_setup() == 0 --> return -EINVAL\n",
572 __func__);
573 return -EINVAL;
574 }
575
576 switch (dp->depth) {
577 case 2:
578 pp_index = GDF_16BIT_565RGB;
579 uc_priv->bpix = VIDEO_BPP16;
580 break;
581 case 3:
582 /* There is no VIDEO_BPP24 because these values are of
583 * type video_log2_bpp
584 */
585 case 4:
586 pp_index = GDF_32BIT_X888RGB;
587 uc_priv->bpix = VIDEO_BPP32;
588 break;
589 default:
590 printf("fail : not support LCD bit per pixel %d\n",
591 dp->depth * 8);
592 return -EINVAL;
593 }
594
595 uc_priv->xsize = dp->fb_plane->width;
596 uc_priv->ysize = dp->fb_plane->height;
597 uc_priv->rot = 0;
598
599 graphic_device = &dp->graphic_device;
600 graphic_device->frameAdrs = dp->fb_addr;
601 graphic_device->gdfIndex = pp_index;
602 graphic_device->gdfBytesPP = dp->depth;
603 graphic_device->winSizeX = dp->fb_plane->width;
604 graphic_device->winSizeY = dp->fb_plane->height;
605 graphic_device->plnSizeX =
606 graphic_device->winSizeX * graphic_device->gdfBytesPP;
607
608 /*
609 * set environment variable "fb_addr" (frame buffer address), required
610 * for splash image. Because drv_video_init() in common/stdio.c is only
611 * called when CONFIG_VIDEO is set (and not if CONFIG_DM_VIDEO is set).
612 */
613 sprintf(addr, "0x%x", dp->fb_addr);
614 debug("%s(): env_set(\"fb_addr\", %s) ...\n", __func__, addr);
615 env_set("fb_addr", addr);
616
617 return 0;
618 }
619
nx_display_bind(struct udevice * dev)620 static int nx_display_bind(struct udevice *dev)
621 {
622 struct video_uc_plat *plat = dev_get_uclass_plat(dev);
623
624 debug("%s()\n", __func__);
625
626 /* Datasheet S5p4418:
627 * Resolution up to 2048 x 1280, up to 12 Bit per color (HDMI)
628 * Actual (max.) size is 0x1000000 because in U-Boot nanopi2-2016.01
629 * "#define CONFIG_FB_ADDR 0x77000000" and next address is
630 * "#define BMP_LOAD_ADDR 0x78000000"
631 */
632 plat->size = 0x1000000;
633
634 return 0;
635 }
636
637 static const struct udevice_id nx_display_ids[] = {
638 {.compatible = "nexell,nexell-display", },
639 {}
640 };
641
642 U_BOOT_DRIVER(nexell_display) = {
643 .name = "nexell-display",
644 .id = UCLASS_VIDEO,
645 .of_match = nx_display_ids,
646 .plat_auto = sizeof(struct nx_display_plat),
647 .bind = nx_display_bind,
648 .probe = nx_display_probe,
649 .priv_auto = sizeof(struct nx_display_dev),
650 };
651