1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2017 Intel Corporation <www.intel.com>
4 */
5
6 #include <common.h>
7 #include <cpu_func.h>
8 #include <errno.h>
9 #include <fdtdec.h>
10 #include <init.h>
11 #include <log.h>
12 #include <malloc.h>
13 #include <wait_bit.h>
14 #include <watchdog.h>
15 #include <asm/cache.h>
16 #include <asm/global_data.h>
17 #include <asm/io.h>
18 #include <asm/arch/fpga_manager.h>
19 #include <asm/arch/misc.h>
20 #include <asm/arch/reset_manager.h>
21 #include <asm/arch/sdram.h>
22 #include <linux/bitops.h>
23 #include <linux/delay.h>
24 #include <linux/kernel.h>
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 static void sdram_mmr_init(void);
29 static u64 sdram_size_calc(void);
30
31 /* FAWBANK - Number of Bank of a given device involved in the FAW period. */
32 #define ARRIA10_SDR_ACTIVATE_FAWBANK (0x1)
33
34 #define ARRIA_DDR_CONFIG(A, B, C, R) \
35 (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
36 #define DDR_CONFIG_ELEMENTS ARRAY_SIZE(ddr_config)
37 #define DDR_REG_SEQ2CORE 0xFFD0507C
38 #define DDR_REG_CORE2SEQ 0xFFD05078
39 #define DDR_READ_LATENCY_DELAY 40
40 #define DDR_SIZE_2GB_HEX 0x80000000
41
42 #define IO48_MMR_DRAMSTS 0xFFCFA0EC
43 #define IO48_MMR_NIOS2_RESERVE0 0xFFCFA110
44 #define IO48_MMR_NIOS2_RESERVE1 0xFFCFA114
45 #define IO48_MMR_NIOS2_RESERVE2 0xFFCFA118
46
47 #define SEQ2CORE_MASK 0xF
48 #define CORE2SEQ_INT_REQ 0xF
49 #define SEQ2CORE_INT_RESP_BIT 3
50
51 static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
52 (void *)SOCFPGA_SDR_ADDRESS;
53 static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =
54 (void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;
55 static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram
56 *socfpga_noc_fw_ddr_mpu_fpga2sdram_base =
57 (void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;
58 static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base =
59 (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
60 static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =
61 (void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;
62
63 /* The following are the supported configurations */
64 static u32 ddr_config[] = {
65 /* Chip - Row - Bank - Column Style */
66 /* All Types */
67 ARRIA_DDR_CONFIG(0, 3, 10, 12),
68 ARRIA_DDR_CONFIG(0, 3, 10, 13),
69 ARRIA_DDR_CONFIG(0, 3, 10, 14),
70 ARRIA_DDR_CONFIG(0, 3, 10, 15),
71 ARRIA_DDR_CONFIG(0, 3, 10, 16),
72 ARRIA_DDR_CONFIG(0, 3, 10, 17),
73 /* LPDDR x16 */
74 ARRIA_DDR_CONFIG(0, 3, 11, 14),
75 ARRIA_DDR_CONFIG(0, 3, 11, 15),
76 ARRIA_DDR_CONFIG(0, 3, 11, 16),
77 ARRIA_DDR_CONFIG(0, 3, 12, 15),
78 /* DDR4 Only */
79 ARRIA_DDR_CONFIG(0, 4, 10, 14),
80 ARRIA_DDR_CONFIG(0, 4, 10, 15),
81 ARRIA_DDR_CONFIG(0, 4, 10, 16),
82 ARRIA_DDR_CONFIG(0, 4, 10, 17), /* 14 */
83 /* Chip - Bank - Row - Column Style */
84 ARRIA_DDR_CONFIG(1, 3, 10, 12),
85 ARRIA_DDR_CONFIG(1, 3, 10, 13),
86 ARRIA_DDR_CONFIG(1, 3, 10, 14),
87 ARRIA_DDR_CONFIG(1, 3, 10, 15),
88 ARRIA_DDR_CONFIG(1, 3, 10, 16),
89 ARRIA_DDR_CONFIG(1, 3, 10, 17),
90 ARRIA_DDR_CONFIG(1, 3, 11, 14),
91 ARRIA_DDR_CONFIG(1, 3, 11, 15),
92 ARRIA_DDR_CONFIG(1, 3, 11, 16),
93 ARRIA_DDR_CONFIG(1, 3, 12, 15),
94 /* DDR4 Only */
95 ARRIA_DDR_CONFIG(1, 4, 10, 14),
96 ARRIA_DDR_CONFIG(1, 4, 10, 15),
97 ARRIA_DDR_CONFIG(1, 4, 10, 16),
98 ARRIA_DDR_CONFIG(1, 4, 10, 17),
99 };
100
match_ddr_conf(u32 ddr_conf)101 static int match_ddr_conf(u32 ddr_conf)
102 {
103 int i;
104
105 for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
106 if (ddr_conf == ddr_config[i])
107 return i;
108 }
109 return 0;
110 }
111
emif_clear(void)112 static int emif_clear(void)
113 {
114 writel(0, DDR_REG_CORE2SEQ);
115
116 return wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
117 SEQ2CORE_MASK, 0, 1000, 0);
118 }
119
emif_reset(void)120 static int emif_reset(void)
121 {
122 u32 c2s, s2c;
123 int ret;
124
125 c2s = readl(DDR_REG_CORE2SEQ);
126 s2c = readl(DDR_REG_SEQ2CORE);
127
128 debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
129 c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0),
130 readl(IO48_MMR_NIOS2_RESERVE1),
131 readl(IO48_MMR_NIOS2_RESERVE2),
132 readl(IO48_MMR_DRAMSTS));
133
134 if (s2c & SEQ2CORE_MASK) {
135 ret = emif_clear();
136 if (ret) {
137 debug("failed emif_clear()\n");
138 return -EPERM;
139 }
140 }
141
142 writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
143
144 ret = wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
145 SEQ2CORE_INT_RESP_BIT, false, 1000, false);
146 if (ret) {
147 debug("emif_reset failed to see interrupt acknowledge\n");
148 emif_clear();
149 return ret;
150 }
151
152 mdelay(1);
153
154 ret = emif_clear();
155 if (ret) {
156 debug("emif_clear() failed\n");
157 return -EPERM;
158 }
159 debug("emif_reset interrupt cleared\n");
160
161 debug("nr0=%08x nr1=%08x nr2=%08x\n",
162 readl(IO48_MMR_NIOS2_RESERVE0),
163 readl(IO48_MMR_NIOS2_RESERVE1),
164 readl(IO48_MMR_NIOS2_RESERVE2));
165
166 return 0;
167 }
168
ddr_setup(void)169 static int ddr_setup(void)
170 {
171 int i, ret;
172
173 /* Try 32 times to do a calibration */
174 for (i = 0; i < 32; i++) {
175 mdelay(500);
176 ret = wait_for_bit_le32(&socfpga_ecc_hmc_base->ddrcalstat,
177 BIT(0), true, 500, false);
178 if (!ret)
179 return 0;
180
181 ret = emif_reset();
182 if (ret)
183 puts("Error: Failed to reset EMIF\n");
184 }
185
186 puts("Error: Could Not Calibrate SDRAM\n");
187 return -EPERM;
188 }
189
sdram_is_ecc_enabled(void)190 static int sdram_is_ecc_enabled(void)
191 {
192 return !!(readl(&socfpga_ecc_hmc_base->eccctrl) &
193 ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK);
194 }
195
196 /* Initialize SDRAM ECC bits to avoid false DBE */
sdram_init_ecc_bits(u32 size)197 static void sdram_init_ecc_bits(u32 size)
198 {
199 icache_enable();
200
201 memset(0, 0, 0x8000);
202 gd->arch.tlb_addr = 0x4000;
203 gd->arch.tlb_size = PGTABLE_SIZE;
204
205 dcache_enable();
206
207 printf("DDRCAL: Scrubbing ECC RAM (%i MiB).\n", size >> 20);
208 memset((void *)0x8000, 0, size - 0x8000);
209 flush_dcache_all();
210 printf("DDRCAL: Scrubbing ECC RAM done.\n");
211 dcache_disable();
212 }
213
214 /* Function to startup the SDRAM*/
sdram_startup(void)215 static int sdram_startup(void)
216 {
217 /* Release NOC ddr scheduler from reset */
218 socfpga_reset_deassert_noc_ddr_scheduler();
219
220 /* Bringup the DDR (calibration and configuration) */
221 return ddr_setup();
222 }
223
sdram_size_calc(void)224 static u64 sdram_size_calc(void)
225 {
226 u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
227
228 u64 size = BIT(((dramaddrw &
229 IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK) >>
230 IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT) +
231 ((dramaddrw &
232 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
233 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT) +
234 ((dramaddrw &
235 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
236 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
237 ((dramaddrw &
238 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
239 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT) +
240 (dramaddrw & IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK));
241
242 size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) &
243 ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK));
244
245 debug("SDRAM size=%llu\n", size);
246
247 return size;
248 }
249
250 /* Function to initialize SDRAM MMR and NOC DDR scheduler*/
sdram_mmr_init(void)251 static void sdram_mmr_init(void)
252 {
253 u32 update_value, io48_value;
254 u32 ctrlcfg0 = readl(&socfpga_io48_mmr_base->ctrlcfg0);
255 u32 ctrlcfg1 = readl(&socfpga_io48_mmr_base->ctrlcfg1);
256 u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
257 u32 caltim0 = readl(&socfpga_io48_mmr_base->caltiming0);
258 u32 caltim1 = readl(&socfpga_io48_mmr_base->caltiming1);
259 u32 caltim2 = readl(&socfpga_io48_mmr_base->caltiming2);
260 u32 caltim3 = readl(&socfpga_io48_mmr_base->caltiming3);
261 u32 caltim4 = readl(&socfpga_io48_mmr_base->caltiming4);
262 u32 caltim9 = readl(&socfpga_io48_mmr_base->caltiming9);
263 u32 ddrioctl;
264
265 /*
266 * Configure the DDR IO size [0xFFCFB008]
267 * niosreserve0: Used to indicate DDR width &
268 * bit[7:0] = Number of data bits (0x20 for 32bit)
269 * bit[8] = 1 if user-mode OCT is present
270 * bit[9] = 1 if warm reset compiled into EMIF Cal Code
271 * bit[10] = 1 if warm reset is on during generation in EMIF Cal
272 * niosreserve1: IP ADCDS version encoded as 16 bit value
273 * bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
274 * 3=EAP, 4-6 are reserved)
275 * bit[5:3] = Service Pack # (e.g. 1)
276 * bit[9:6] = Minor Release #
277 * bit[14:10] = Major Release #
278 */
279 if ((readl(&socfpga_io48_mmr_base->niosreserve1) >> 6) & 0x1FF) {
280 update_value = readl(&socfpga_io48_mmr_base->niosreserve0);
281 writel(((update_value & 0xFF) >> 5),
282 &socfpga_ecc_hmc_base->ddrioctrl);
283 }
284
285 ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl);
286
287 /* Set the DDR Configuration [0xFFD12400] */
288 io48_value = ARRIA_DDR_CONFIG(
289 ((ctrlcfg1 &
290 IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK) >>
291 IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT),
292 ((dramaddrw &
293 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
294 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
295 ((dramaddrw &
296 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
297 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT),
298 (dramaddrw &
299 IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK),
300 ((dramaddrw &
301 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
302 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT));
303
304 update_value = match_ddr_conf(io48_value);
305 if (update_value)
306 writel(update_value,
307 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrconf);
308
309 /*
310 * Configure DDR timing [0xFFD1240C]
311 * RDTOMISS = tRTP + tRP + tRCD - BL/2
312 * WRTOMISS = WL + tWR + tRP + tRCD and
313 * WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns so...
314 * First part of equation is in memory clock units so divide by 2
315 * for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
316 * WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
317 */
318 u32 ctrlcfg0_cfg_ctrl_burst_len =
319 (ctrlcfg0 & IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK) >>
320 IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT;
321
322 u32 caltim0_cfg_act_to_rdwr = caltim0 &
323 IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK;
324
325 u32 caltim0_cfg_act_to_act =
326 (caltim0 & IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK) >>
327 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT;
328
329 u32 caltim0_cfg_act_to_act_db =
330 (caltim0 &
331 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK) >>
332 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT;
333
334 u32 caltim1_cfg_rd_to_wr =
335 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK) >>
336 IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT;
337
338 u32 caltim1_cfg_rd_to_rd_dc =
339 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK) >>
340 IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT;
341
342 u32 caltim1_cfg_rd_to_wr_dc =
343 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK) >>
344 IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT;
345
346 u32 caltim2_cfg_rd_to_pch =
347 (caltim2 & IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK) >>
348 IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT;
349
350 u32 caltim3_cfg_wr_to_rd =
351 (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK) >>
352 IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT;
353
354 u32 caltim3_cfg_wr_to_rd_dc =
355 (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK) >>
356 IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT;
357
358 u32 caltim4_cfg_pch_to_valid =
359 (caltim4 & IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK) >>
360 IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT;
361
362 u32 caltim9_cfg_4_act_to_act = caltim9 &
363 IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK;
364
365 update_value = (caltim2_cfg_rd_to_pch + caltim4_cfg_pch_to_valid +
366 caltim0_cfg_act_to_rdwr -
367 (ctrlcfg0_cfg_ctrl_burst_len >> 2));
368
369 io48_value = ((((readl(&socfpga_io48_mmr_base->dramtiming0) &
370 ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 +
371 (ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) -
372 /* Up to here was in memory cycles so divide by 2 */
373 caltim1_cfg_rd_to_wr + caltim0_cfg_act_to_rdwr +
374 caltim4_cfg_pch_to_valid);
375
376 writel(((caltim0_cfg_act_to_act <<
377 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB) |
378 (update_value <<
379 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB) |
380 (io48_value <<
381 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB) |
382 ((ctrlcfg0_cfg_ctrl_burst_len >> 2) <<
383 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB) |
384 (caltim1_cfg_rd_to_wr <<
385 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB) |
386 (caltim3_cfg_wr_to_rd <<
387 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB) |
388 (((ddrioctl == 1) ? 1 : 0) <<
389 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB)),
390 &socfpga_noc_ddr_scheduler_base->
391 ddr_t_main_scheduler_ddrtiming);
392
393 /* Configure DDR mode [0xFFD12410] [precharge = 0] */
394 writel(((ddrioctl ? 0 : 1) <<
395 ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB),
396 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode);
397
398 /* Configure the read latency [0xFFD12414] */
399 writel(((readl(&socfpga_io48_mmr_base->dramtiming0) &
400 ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) +
401 DDR_READ_LATENCY_DELAY,
402 &socfpga_noc_ddr_scheduler_base->
403 ddr_t_main_scheduler_readlatency);
404
405 /*
406 * Configuring timing values concerning activate commands
407 * [0xFFD12438] [FAWBANK alway 1 because always 4 bank DDR]
408 */
409 writel(((caltim0_cfg_act_to_act_db <<
410 ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB) |
411 (caltim9_cfg_4_act_to_act <<
412 ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB) |
413 (ARRIA10_SDR_ACTIVATE_FAWBANK <<
414 ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB)),
415 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_activate);
416
417 /*
418 * Configuring timing values concerning device to device data bus
419 * ownership change [0xFFD1243C]
420 */
421 writel(((caltim1_cfg_rd_to_rd_dc <<
422 ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB) |
423 (caltim1_cfg_rd_to_wr_dc <<
424 ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB) |
425 (caltim3_cfg_wr_to_rd_dc <<
426 ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB)),
427 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_devtodev);
428
429 /* Enable or disable the SDRAM ECC */
430 if (ctrlcfg1 & IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC) {
431 setbits_le32(&socfpga_ecc_hmc_base->eccctrl,
432 (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
433 ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
434 ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
435 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
436 (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
437 ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK));
438 setbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
439 (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
440 ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
441 } else {
442 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
443 (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
444 ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
445 ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
446 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
447 (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
448 ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
449 }
450 }
451
452 struct firewall_entry {
453 const char *prop_name;
454 const u32 cfg_addr;
455 const u32 en_addr;
456 const u32 en_bit;
457 };
458 #define FW_MPU_FPGA_ADDRESS \
459 ((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\
460 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS)
461
462 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(ADDR) \
463 (SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS + \
464 offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram, ADDR))
465
466 #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(ADDR) \
467 (SOCFPGA_SDR_FIREWALL_L3_ADDRESS + \
468 offsetof(struct socfpga_noc_fw_ddr_l3, ADDR))
469
470 const struct firewall_entry firewall_table[] = {
471 {
472 "mpu0",
473 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion0addr),
474 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
475 ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK
476 },
477 {
478 "mpu1",
479 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
480 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion1addr),
481 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
482 ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK
483 },
484 {
485 "mpu2",
486 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion2addr),
487 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
488 ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK
489 },
490 {
491 "mpu3",
492 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion3addr),
493 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
494 ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK
495 },
496 {
497 "l3-0",
498 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion0addr),
499 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
500 ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK
501 },
502 {
503 "l3-1",
504 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion1addr),
505 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
506 ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK
507 },
508 {
509 "l3-2",
510 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion2addr),
511 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
512 ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK
513 },
514 {
515 "l3-3",
516 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion3addr),
517 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
518 ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK
519 },
520 {
521 "l3-4",
522 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion4addr),
523 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
524 ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK
525 },
526 {
527 "l3-5",
528 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion5addr),
529 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
530 ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK
531 },
532 {
533 "l3-6",
534 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion6addr),
535 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
536 ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK
537 },
538 {
539 "l3-7",
540 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion7addr),
541 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
542 ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK
543 },
544 {
545 "fpga2sdram0-0",
546 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
547 (fpga2sdram0region0addr),
548 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
549 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK
550 },
551 {
552 "fpga2sdram0-1",
553 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
554 (fpga2sdram0region1addr),
555 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
556 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK
557 },
558 {
559 "fpga2sdram0-2",
560 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
561 (fpga2sdram0region2addr),
562 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
563 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK
564 },
565 {
566 "fpga2sdram0-3",
567 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
568 (fpga2sdram0region3addr),
569 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
570 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK
571 },
572 {
573 "fpga2sdram1-0",
574 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
575 (fpga2sdram1region0addr),
576 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
577 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK
578 },
579 {
580 "fpga2sdram1-1",
581 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
582 (fpga2sdram1region1addr),
583 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
584 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK
585 },
586 {
587 "fpga2sdram1-2",
588 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
589 (fpga2sdram1region2addr),
590 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
591 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK
592 },
593 {
594 "fpga2sdram1-3",
595 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
596 (fpga2sdram1region3addr),
597 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
598 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK
599 },
600 {
601 "fpga2sdram2-0",
602 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
603 (fpga2sdram2region0addr),
604 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
605 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK
606 },
607 {
608 "fpga2sdram2-1",
609 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
610 (fpga2sdram2region1addr),
611 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
612 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK
613 },
614 {
615 "fpga2sdram2-2",
616 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
617 (fpga2sdram2region2addr),
618 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
619 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK
620 },
621 {
622 "fpga2sdram2-3",
623 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
624 (fpga2sdram2region3addr),
625 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
626 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK
627 },
628
629 };
630
of_sdram_firewall_setup(const void * blob)631 static int of_sdram_firewall_setup(const void *blob)
632 {
633 int child, i, node, ret;
634 u32 start_end[2];
635 char name[32];
636
637 node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_NOC);
638 if (node < 0)
639 return -ENXIO;
640
641 child = fdt_first_subnode(blob, node);
642 if (child < 0)
643 return -ENXIO;
644
645 /* set to default state */
646 writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable);
647 writel(0, &socfpga_noc_fw_ddr_l3_base->enable);
648
649
650 for (i = 0; i < ARRAY_SIZE(firewall_table); i++) {
651 sprintf(name, "%s", firewall_table[i].prop_name);
652 ret = fdtdec_get_int_array(blob, child, name,
653 start_end, 2);
654 if (ret) {
655 sprintf(name, "altr,%s", firewall_table[i].prop_name);
656 ret = fdtdec_get_int_array(blob, child, name,
657 start_end, 2);
658 if (ret)
659 continue;
660 }
661
662 writel((start_end[0] & ALT_NOC_FW_DDR_ADDR_MASK) |
663 (start_end[1] << ALT_NOC_FW_DDR_END_ADDR_LSB),
664 firewall_table[i].cfg_addr);
665 setbits_le32(firewall_table[i].en_addr,
666 firewall_table[i].en_bit);
667 }
668
669 return 0;
670 }
671
ddr_calibration_sequence(void)672 int ddr_calibration_sequence(void)
673 {
674 WATCHDOG_RESET();
675
676 /* Check to see if SDRAM cal was success */
677 if (sdram_startup()) {
678 puts("DDRCAL: Failed\n");
679 return -EPERM;
680 }
681
682 puts("DDRCAL: Success\n");
683
684 WATCHDOG_RESET();
685
686 /* initialize the MMR register */
687 sdram_mmr_init();
688
689 /* assigning the SDRAM size */
690 u64 size = sdram_size_calc();
691
692 /*
693 * If size is less than zero, this is invalid/weird value from
694 * calculation, use default Config size.
695 * Up to 2GB is supported, 2GB would be used if more than that.
696 */
697 if (size <= 0)
698 gd->ram_size = PHYS_SDRAM_1_SIZE;
699 else if (DDR_SIZE_2GB_HEX <= size)
700 gd->ram_size = DDR_SIZE_2GB_HEX;
701 else
702 gd->ram_size = (u32)size;
703
704 /* setup the dram info within bd */
705 dram_init_banksize();
706
707 if (of_sdram_firewall_setup(gd->fdt_blob))
708 puts("FW: Error Configuring Firewall\n");
709
710 if (sdram_is_ecc_enabled())
711 sdram_init_ecc_bits(gd->ram_size);
712
713 return 0;
714 }
715