1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH
4 */
5
6 #include <common.h>
7 #include <bootstage.h>
8 #include <dm.h>
9 #include <init.h>
10 #include <log.h>
11 #include <asm/global_data.h>
12 #include <dm/ofnode.h>
13 #include <mapmem.h>
14 #include <asm/arch-rockchip/timer.h>
15 #include <dt-structs.h>
16 #include <timer.h>
17 #include <asm/io.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20
21 #if CONFIG_IS_ENABLED(OF_PLATDATA)
22 struct rockchip_timer_plat {
23 struct dtd_rockchip_rk3368_timer dtd;
24 };
25 #endif
26
27 /* Driver private data. Contains timer id. Could be either 0 or 1. */
28 struct rockchip_timer_priv {
29 struct rk_timer *timer;
30 };
31
rockchip_timer_get_curr_value(struct rk_timer * timer)32 static inline int64_t rockchip_timer_get_curr_value(struct rk_timer *timer)
33 {
34 uint64_t timebase_h, timebase_l;
35 uint64_t cntr;
36
37 timebase_l = readl(&timer->timer_curr_value0);
38 timebase_h = readl(&timer->timer_curr_value1);
39
40 cntr = timebase_h << 32 | timebase_l;
41 return cntr;
42 }
43
44 #if CONFIG_IS_ENABLED(BOOTSTAGE)
timer_get_boot_us(void)45 ulong timer_get_boot_us(void)
46 {
47 uint64_t ticks = 0;
48 uint32_t rate;
49 uint64_t us;
50 int ret;
51
52 ret = dm_timer_init();
53
54 if (!ret) {
55 /* The timer is available */
56 rate = timer_get_rate(gd->timer);
57 timer_get_count(gd->timer, &ticks);
58 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
59 } else if (ret == -EAGAIN) {
60 /* We have been called so early that the DM is not ready,... */
61 ofnode node = offset_to_ofnode(-1);
62 struct rk_timer *timer = NULL;
63
64 /*
65 * ... so we try to access the raw timer, if it is specified
66 * via the tick-timer property in /chosen.
67 */
68 node = ofnode_get_chosen_node("tick-timer");
69 if (!ofnode_valid(node)) {
70 debug("%s: no /chosen/tick-timer\n", __func__);
71 return 0;
72 }
73
74 timer = (struct rk_timer *)ofnode_get_addr(node);
75
76 /* This timer is down-counting */
77 ticks = ~0uLL - rockchip_timer_get_curr_value(timer);
78 if (ofnode_read_u32(node, "clock-frequency", &rate)) {
79 debug("%s: could not read clock-frequency\n", __func__);
80 return 0;
81 }
82 #endif
83 } else {
84 return 0;
85 }
86
87 us = (ticks * 1000) / rate;
88 return us;
89 }
90 #endif
91
rockchip_timer_get_count(struct udevice * dev)92 static u64 rockchip_timer_get_count(struct udevice *dev)
93 {
94 struct rockchip_timer_priv *priv = dev_get_priv(dev);
95 uint64_t cntr = rockchip_timer_get_curr_value(priv->timer);
96
97 /* timers are down-counting */
98 return ~0ull - cntr;
99 }
100
rockchip_clk_of_to_plat(struct udevice * dev)101 static int rockchip_clk_of_to_plat(struct udevice *dev)
102 {
103 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
104 struct rockchip_timer_priv *priv = dev_get_priv(dev);
105
106 priv->timer = dev_read_addr_ptr(dev);
107 if (!priv->timer)
108 return -ENOENT;
109 #endif
110
111 return 0;
112 }
113
rockchip_timer_start(struct udevice * dev)114 static int rockchip_timer_start(struct udevice *dev)
115 {
116 struct rockchip_timer_priv *priv = dev_get_priv(dev);
117 const uint64_t reload_val = ~0uLL;
118 const uint32_t reload_val_l = reload_val & 0xffffffff;
119 const uint32_t reload_val_h = reload_val >> 32;
120
121 /* don't reinit, if the timer is already running and set up */
122 if ((readl(&priv->timer->timer_ctrl_reg) & 1) == 1 &&
123 (readl(&priv->timer->timer_load_count0) == reload_val_l) &&
124 (readl(&priv->timer->timer_load_count1) == reload_val_h))
125 return 0;
126
127 /* disable timer and reset all control */
128 writel(0, &priv->timer->timer_ctrl_reg);
129 /* write reload value */
130 writel(reload_val_l, &priv->timer->timer_load_count0);
131 writel(reload_val_h, &priv->timer->timer_load_count1);
132 /* enable timer */
133 writel(1, &priv->timer->timer_ctrl_reg);
134
135 return 0;
136 }
137
rockchip_timer_probe(struct udevice * dev)138 static int rockchip_timer_probe(struct udevice *dev)
139 {
140 #if CONFIG_IS_ENABLED(OF_PLATDATA)
141 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
142 struct rockchip_timer_priv *priv = dev_get_priv(dev);
143 struct rockchip_timer_plat *plat = dev_get_plat(dev);
144
145 priv->timer = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
146 uc_priv->clock_rate = plat->dtd.clock_frequency;
147 #endif
148
149 return rockchip_timer_start(dev);
150 }
151
152 static const struct timer_ops rockchip_timer_ops = {
153 .get_count = rockchip_timer_get_count,
154 };
155
156 static const struct udevice_id rockchip_timer_ids[] = {
157 { .compatible = "rockchip,rk3188-timer" },
158 { .compatible = "rockchip,rk3288-timer" },
159 { .compatible = "rockchip,rk3368-timer" },
160 {}
161 };
162
163 U_BOOT_DRIVER(rockchip_rk3368_timer) = {
164 .name = "rockchip_rk3368_timer",
165 .id = UCLASS_TIMER,
166 .of_match = rockchip_timer_ids,
167 .probe = rockchip_timer_probe,
168 .ops = &rockchip_timer_ops,
169 .priv_auto = sizeof(struct rockchip_timer_priv),
170 #if CONFIG_IS_ENABLED(OF_PLATDATA)
171 .plat_auto = sizeof(struct rockchip_timer_plat),
172 #endif
173 .of_to_plat = rockchip_clk_of_to_plat,
174 };
175