1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012 Samsung Electronics
4 *
5 * Author: InKi Dae <inki.dae@samsung.com>
6 * Author: Donghwa Lee <dh09.lee@samsung.com>
7 */
8
9 #include <config.h>
10 #include <common.h>
11 #include <display.h>
12 #include <div64.h>
13 #include <dm.h>
14 #include <fdtdec.h>
15 #include <log.h>
16 #include <asm/global_data.h>
17 #include <linux/libfdt.h>
18 #include <panel.h>
19 #include <video.h>
20 #include <video_bridge.h>
21 #include <asm/io.h>
22 #include <asm/arch/cpu.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/clk.h>
25 #include <asm/arch/mipi_dsim.h>
26 #include <asm/arch/dp_info.h>
27 #include <asm/arch/fb.h>
28 #include <asm/arch/pinmux.h>
29 #include <asm/arch/system.h>
30 #include <asm/gpio.h>
31 #include <linux/errno.h>
32
33 DECLARE_GLOBAL_DATA_PTR;
34
35 enum {
36 FIMD_RGB_INTERFACE = 1,
37 FIMD_CPU_INTERFACE = 2,
38 };
39
40 enum exynos_fb_rgb_mode_t {
41 MODE_RGB_P = 0,
42 MODE_BGR_P = 1,
43 MODE_RGB_S = 2,
44 MODE_BGR_S = 3,
45 };
46
47 struct exynos_fb_priv {
48 ushort vl_col; /* Number of columns (i.e. 640) */
49 ushort vl_row; /* Number of rows (i.e. 480) */
50 ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */
51 ushort vl_width; /* Width of display area in millimeters */
52 ushort vl_height; /* Height of display area in millimeters */
53
54 /* LCD configuration register */
55 u_char vl_freq; /* Frequency */
56 u_char vl_clkp; /* Clock polarity */
57 u_char vl_oep; /* Output Enable polarity */
58 u_char vl_hsp; /* Horizontal Sync polarity */
59 u_char vl_vsp; /* Vertical Sync polarity */
60 u_char vl_dp; /* Data polarity */
61 u_char vl_bpix; /* Bits per pixel */
62
63 /* Horizontal control register. Timing from data sheet */
64 u_char vl_hspw; /* Horz sync pulse width */
65 u_char vl_hfpd; /* Wait before of line */
66 u_char vl_hbpd; /* Wait end of line */
67
68 /* Vertical control register. */
69 u_char vl_vspw; /* Vertical sync pulse width */
70 u_char vl_vfpd; /* Wait before of frame */
71 u_char vl_vbpd; /* Wait end of frame */
72 u_char vl_cmd_allow_len; /* Wait end of frame */
73
74 unsigned int win_id;
75 unsigned int init_delay;
76 unsigned int power_on_delay;
77 unsigned int reset_delay;
78 unsigned int interface_mode;
79 unsigned int mipi_enabled;
80 unsigned int dp_enabled;
81 unsigned int cs_setup;
82 unsigned int wr_setup;
83 unsigned int wr_act;
84 unsigned int wr_hold;
85 unsigned int logo_on;
86 unsigned int logo_width;
87 unsigned int logo_height;
88 int logo_x_offset;
89 int logo_y_offset;
90 unsigned long logo_addr;
91 unsigned int rgb_mode;
92 unsigned int resolution;
93
94 /* parent clock name(MPLL, EPLL or VPLL) */
95 unsigned int pclk_name;
96 /* ratio value for source clock from parent clock. */
97 unsigned int sclk_div;
98
99 unsigned int dual_lcd_enabled;
100 struct exynos_fb *reg;
101 struct exynos_platform_mipi_dsim *dsim_platform_data_dt;
102 };
103
exynos_fimd_set_dualrgb(struct exynos_fb_priv * priv,bool enabled)104 static void exynos_fimd_set_dualrgb(struct exynos_fb_priv *priv, bool enabled)
105 {
106 struct exynos_fb *reg = priv->reg;
107 unsigned int cfg = 0;
108
109 if (enabled) {
110 cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT |
111 EXYNOS_DUALRGB_VDEN_EN_ENABLE;
112
113 /* in case of Line Split mode, MAIN_CNT doesn't neet to set. */
114 cfg |= EXYNOS_DUALRGB_SUB_CNT(priv->vl_col / 2) |
115 EXYNOS_DUALRGB_MAIN_CNT(0);
116 }
117
118 writel(cfg, ®->dualrgb);
119 }
120
exynos_fimd_set_dp_clkcon(struct exynos_fb_priv * priv,unsigned int enabled)121 static void exynos_fimd_set_dp_clkcon(struct exynos_fb_priv *priv,
122 unsigned int enabled)
123 {
124 struct exynos_fb *reg = priv->reg;
125 unsigned int cfg = 0;
126
127 if (enabled)
128 cfg = EXYNOS_DP_CLK_ENABLE;
129
130 writel(cfg, ®->dp_mie_clkcon);
131 }
132
exynos_fimd_set_par(struct exynos_fb_priv * priv,unsigned int win_id)133 static void exynos_fimd_set_par(struct exynos_fb_priv *priv,
134 unsigned int win_id)
135 {
136 struct exynos_fb *reg = priv->reg;
137 unsigned int cfg = 0;
138
139 /* set window control */
140 cfg = readl((unsigned int)®->wincon0 +
141 EXYNOS_WINCON(win_id));
142
143 cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE |
144 EXYNOS_WINCON_HAWSWP_ENABLE | EXYNOS_WINCON_WSWP_ENABLE |
145 EXYNOS_WINCON_BURSTLEN_MASK | EXYNOS_WINCON_BPPMODE_MASK |
146 EXYNOS_WINCON_INRGB_MASK | EXYNOS_WINCON_DATAPATH_MASK);
147
148 /* DATAPATH is DMA */
149 cfg |= EXYNOS_WINCON_DATAPATH_DMA;
150
151 cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
152
153 /* dma burst is 16 */
154 cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
155
156 switch (priv->vl_bpix) {
157 case 4:
158 cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
159 break;
160 default:
161 cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
162 break;
163 }
164
165 writel(cfg, (unsigned int)®->wincon0 +
166 EXYNOS_WINCON(win_id));
167
168 /* set window position to x=0, y=0*/
169 cfg = EXYNOS_VIDOSD_LEFT_X(0) | EXYNOS_VIDOSD_TOP_Y(0);
170 writel(cfg, (unsigned int)®->vidosd0a +
171 EXYNOS_VIDOSD(win_id));
172
173 cfg = EXYNOS_VIDOSD_RIGHT_X(priv->vl_col - 1) |
174 EXYNOS_VIDOSD_BOTTOM_Y(priv->vl_row - 1) |
175 EXYNOS_VIDOSD_RIGHT_X_E(1) |
176 EXYNOS_VIDOSD_BOTTOM_Y_E(0);
177
178 writel(cfg, (unsigned int)®->vidosd0b +
179 EXYNOS_VIDOSD(win_id));
180
181 /* set window size for window0*/
182 cfg = EXYNOS_VIDOSD_SIZE(priv->vl_col * priv->vl_row);
183 writel(cfg, (unsigned int)®->vidosd0c +
184 EXYNOS_VIDOSD(win_id));
185 }
186
exynos_fimd_set_buffer_address(struct exynos_fb_priv * priv,unsigned int win_id,ulong lcd_base_addr)187 static void exynos_fimd_set_buffer_address(struct exynos_fb_priv *priv,
188 unsigned int win_id,
189 ulong lcd_base_addr)
190 {
191 struct exynos_fb *reg = priv->reg;
192 unsigned long start_addr, end_addr;
193
194 start_addr = lcd_base_addr;
195 end_addr = start_addr + ((priv->vl_col * (VNBITS(priv->vl_bpix) / 8)) *
196 priv->vl_row);
197
198 writel(start_addr, (unsigned int)®->vidw00add0b0 +
199 EXYNOS_BUFFER_OFFSET(win_id));
200 writel(end_addr, (unsigned int)®->vidw00add1b0 +
201 EXYNOS_BUFFER_OFFSET(win_id));
202 }
203
exynos_fimd_set_clock(struct exynos_fb_priv * priv)204 static void exynos_fimd_set_clock(struct exynos_fb_priv *priv)
205 {
206 struct exynos_fb *reg = priv->reg;
207 unsigned int cfg = 0, div = 0, remainder, remainder_div;
208 unsigned long pixel_clock;
209 unsigned long long src_clock;
210
211 if (priv->dual_lcd_enabled) {
212 pixel_clock = priv->vl_freq *
213 (priv->vl_hspw + priv->vl_hfpd +
214 priv->vl_hbpd + priv->vl_col / 2) *
215 (priv->vl_vspw + priv->vl_vfpd +
216 priv->vl_vbpd + priv->vl_row);
217 } else if (priv->interface_mode == FIMD_CPU_INTERFACE) {
218 pixel_clock = priv->vl_freq *
219 priv->vl_width * priv->vl_height *
220 (priv->cs_setup + priv->wr_setup +
221 priv->wr_act + priv->wr_hold + 1);
222 } else {
223 pixel_clock = priv->vl_freq *
224 (priv->vl_hspw + priv->vl_hfpd +
225 priv->vl_hbpd + priv->vl_col) *
226 (priv->vl_vspw + priv->vl_vfpd +
227 priv->vl_vbpd + priv->vl_row);
228 }
229
230 cfg = readl(®->vidcon0);
231 cfg &= ~(EXYNOS_VIDCON0_CLKSEL_MASK | EXYNOS_VIDCON0_CLKVALUP_MASK |
232 EXYNOS_VIDCON0_CLKVAL_F(0xFF) | EXYNOS_VIDCON0_VCLKEN_MASK |
233 EXYNOS_VIDCON0_CLKDIR_MASK);
234 cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS |
235 EXYNOS_VIDCON0_VCLKEN_NORMAL | EXYNOS_VIDCON0_CLKDIR_DIVIDED);
236
237 src_clock = (unsigned long long) get_lcd_clk();
238
239 /* get quotient and remainder. */
240 remainder = do_div(src_clock, pixel_clock);
241 div = src_clock;
242
243 remainder *= 10;
244 remainder_div = remainder / pixel_clock;
245
246 /* round about one places of decimals. */
247 if (remainder_div >= 5)
248 div++;
249
250 /* in case of dual lcd mode. */
251 if (priv->dual_lcd_enabled)
252 div--;
253
254 cfg |= EXYNOS_VIDCON0_CLKVAL_F(div - 1);
255 writel(cfg, ®->vidcon0);
256 }
257
exynos_set_trigger(struct exynos_fb_priv * priv)258 void exynos_set_trigger(struct exynos_fb_priv *priv)
259 {
260 struct exynos_fb *reg = priv->reg;
261 unsigned int cfg = 0;
262
263 cfg = readl(®->trigcon);
264
265 cfg |= (EXYNOS_I80SOFT_TRIG_EN | EXYNOS_I80START_TRIG);
266
267 writel(cfg, ®->trigcon);
268 }
269
exynos_is_i80_frame_done(struct exynos_fb_priv * priv)270 int exynos_is_i80_frame_done(struct exynos_fb_priv *priv)
271 {
272 struct exynos_fb *reg = priv->reg;
273 unsigned int cfg = 0;
274 int status;
275
276 cfg = readl(®->trigcon);
277
278 /* frame done func is valid only when TRIMODE[0] is set to 1. */
279 status = (cfg & EXYNOS_I80STATUS_TRIG_DONE) ==
280 EXYNOS_I80STATUS_TRIG_DONE;
281
282 return status;
283 }
284
exynos_fimd_lcd_on(struct exynos_fb_priv * priv)285 static void exynos_fimd_lcd_on(struct exynos_fb_priv *priv)
286 {
287 struct exynos_fb *reg = priv->reg;
288 unsigned int cfg = 0;
289
290 /* display on */
291 cfg = readl(®->vidcon0);
292 cfg |= (EXYNOS_VIDCON0_ENVID_ENABLE | EXYNOS_VIDCON0_ENVID_F_ENABLE);
293 writel(cfg, ®->vidcon0);
294 }
295
exynos_fimd_window_on(struct exynos_fb_priv * priv,unsigned int win_id)296 static void exynos_fimd_window_on(struct exynos_fb_priv *priv,
297 unsigned int win_id)
298 {
299 struct exynos_fb *reg = priv->reg;
300 unsigned int cfg = 0;
301
302 /* enable window */
303 cfg = readl((unsigned int)®->wincon0 +
304 EXYNOS_WINCON(win_id));
305 cfg |= EXYNOS_WINCON_ENWIN_ENABLE;
306 writel(cfg, (unsigned int)®->wincon0 +
307 EXYNOS_WINCON(win_id));
308
309 cfg = readl(®->winshmap);
310 cfg |= EXYNOS_WINSHMAP_CH_ENABLE(win_id);
311 writel(cfg, ®->winshmap);
312 }
313
exynos_fimd_lcd_off(struct exynos_fb_priv * priv)314 void exynos_fimd_lcd_off(struct exynos_fb_priv *priv)
315 {
316 struct exynos_fb *reg = priv->reg;
317 unsigned int cfg = 0;
318
319 cfg = readl(®->vidcon0);
320 cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE);
321 writel(cfg, ®->vidcon0);
322 }
323
exynos_fimd_window_off(struct exynos_fb_priv * priv,unsigned int win_id)324 void exynos_fimd_window_off(struct exynos_fb_priv *priv, unsigned int win_id)
325 {
326 struct exynos_fb *reg = priv->reg;
327 unsigned int cfg = 0;
328
329 cfg = readl((unsigned int)®->wincon0 +
330 EXYNOS_WINCON(win_id));
331 cfg &= EXYNOS_WINCON_ENWIN_DISABLE;
332 writel(cfg, (unsigned int)®->wincon0 +
333 EXYNOS_WINCON(win_id));
334
335 cfg = readl(®->winshmap);
336 cfg &= ~EXYNOS_WINSHMAP_CH_DISABLE(win_id);
337 writel(cfg, ®->winshmap);
338 }
339
340 /*
341 * The reset value for FIMD SYSMMU register MMU_CTRL is 3
342 * on Exynos5420 and newer versions.
343 * This means FIMD SYSMMU is on by default on Exynos5420
344 * and newer versions.
345 * Since in u-boot we don't use SYSMMU, we should disable
346 * those FIMD SYSMMU.
347 * Note that there are 2 SYSMMU for FIMD: m0 and m1.
348 * m0 handles windows 0 and 4, and m1 handles windows 1, 2 and 3.
349 * We disable both of them here.
350 */
exynos_fimd_disable_sysmmu(void)351 void exynos_fimd_disable_sysmmu(void)
352 {
353 u32 *sysmmufimd;
354 unsigned int node;
355 int node_list[2];
356 int count;
357 int i;
358
359 count = fdtdec_find_aliases_for_id(gd->fdt_blob, "fimd",
360 COMPAT_SAMSUNG_EXYNOS_SYSMMU, node_list, 2);
361 for (i = 0; i < count; i++) {
362 node = node_list[i];
363 if (node <= 0) {
364 debug("Can't get device node for fimd sysmmu\n");
365 return;
366 }
367
368 sysmmufimd = (u32 *)fdtdec_get_addr(gd->fdt_blob, node, "reg");
369 if (!sysmmufimd) {
370 debug("Can't get base address for sysmmu fimdm0");
371 return;
372 }
373
374 writel(0x0, sysmmufimd);
375 }
376 }
377
exynos_fimd_lcd_init(struct udevice * dev)378 void exynos_fimd_lcd_init(struct udevice *dev)
379 {
380 struct exynos_fb_priv *priv = dev_get_priv(dev);
381 struct video_uc_plat *plat = dev_get_uclass_plat(dev);
382 struct exynos_fb *reg = priv->reg;
383 unsigned int cfg = 0, rgb_mode;
384 unsigned int offset;
385 unsigned int node;
386
387 node = dev_of_offset(dev);
388 if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu"))
389 exynos_fimd_disable_sysmmu();
390
391 offset = exynos_fimd_get_base_offset();
392
393 rgb_mode = priv->rgb_mode;
394
395 if (priv->interface_mode == FIMD_RGB_INTERFACE) {
396 cfg |= EXYNOS_VIDCON0_VIDOUT_RGB;
397 writel(cfg, ®->vidcon0);
398
399 cfg = readl(®->vidcon2);
400 cfg &= ~(EXYNOS_VIDCON2_WB_MASK |
401 EXYNOS_VIDCON2_TVFORMATSEL_MASK |
402 EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK);
403 cfg |= EXYNOS_VIDCON2_WB_DISABLE;
404 writel(cfg, ®->vidcon2);
405
406 /* set polarity */
407 cfg = 0;
408 if (!priv->vl_clkp)
409 cfg |= EXYNOS_VIDCON1_IVCLK_RISING_EDGE;
410 if (!priv->vl_hsp)
411 cfg |= EXYNOS_VIDCON1_IHSYNC_INVERT;
412 if (!priv->vl_vsp)
413 cfg |= EXYNOS_VIDCON1_IVSYNC_INVERT;
414 if (!priv->vl_dp)
415 cfg |= EXYNOS_VIDCON1_IVDEN_INVERT;
416
417 writel(cfg, (unsigned int)®->vidcon1 + offset);
418
419 /* set timing */
420 cfg = EXYNOS_VIDTCON0_VFPD(priv->vl_vfpd - 1);
421 cfg |= EXYNOS_VIDTCON0_VBPD(priv->vl_vbpd - 1);
422 cfg |= EXYNOS_VIDTCON0_VSPW(priv->vl_vspw - 1);
423 writel(cfg, (unsigned int)®->vidtcon0 + offset);
424
425 cfg = EXYNOS_VIDTCON1_HFPD(priv->vl_hfpd - 1);
426 cfg |= EXYNOS_VIDTCON1_HBPD(priv->vl_hbpd - 1);
427 cfg |= EXYNOS_VIDTCON1_HSPW(priv->vl_hspw - 1);
428
429 writel(cfg, (unsigned int)®->vidtcon1 + offset);
430
431 /* set lcd size */
432 cfg = EXYNOS_VIDTCON2_HOZVAL(priv->vl_col - 1) |
433 EXYNOS_VIDTCON2_LINEVAL(priv->vl_row - 1) |
434 EXYNOS_VIDTCON2_HOZVAL_E(priv->vl_col - 1) |
435 EXYNOS_VIDTCON2_LINEVAL_E(priv->vl_row - 1);
436
437 writel(cfg, (unsigned int)®->vidtcon2 + offset);
438 }
439
440 /* set display mode */
441 cfg = readl(®->vidcon0);
442 cfg &= ~EXYNOS_VIDCON0_PNRMODE_MASK;
443 cfg |= (rgb_mode << EXYNOS_VIDCON0_PNRMODE_SHIFT);
444 writel(cfg, ®->vidcon0);
445
446 /* set par */
447 exynos_fimd_set_par(priv, priv->win_id);
448
449 /* set memory address */
450 exynos_fimd_set_buffer_address(priv, priv->win_id, plat->base);
451
452 /* set buffer size */
453 cfg = EXYNOS_VIDADDR_PAGEWIDTH(priv->vl_col *
454 VNBITS(priv->vl_bpix) / 8) |
455 EXYNOS_VIDADDR_PAGEWIDTH_E(priv->vl_col *
456 VNBITS(priv->vl_bpix) / 8) |
457 EXYNOS_VIDADDR_OFFSIZE(0) |
458 EXYNOS_VIDADDR_OFFSIZE_E(0);
459
460 writel(cfg, (unsigned int)®->vidw00add2 +
461 EXYNOS_BUFFER_SIZE(priv->win_id));
462
463 /* set clock */
464 exynos_fimd_set_clock(priv);
465
466 /* set rgb mode to dual lcd. */
467 exynos_fimd_set_dualrgb(priv, priv->dual_lcd_enabled);
468
469 /* display on */
470 exynos_fimd_lcd_on(priv);
471
472 /* window on */
473 exynos_fimd_window_on(priv, priv->win_id);
474
475 exynos_fimd_set_dp_clkcon(priv, priv->dp_enabled);
476 }
477
exynos_fimd_calc_fbsize(struct exynos_fb_priv * priv)478 unsigned long exynos_fimd_calc_fbsize(struct exynos_fb_priv *priv)
479 {
480 return priv->vl_col * priv->vl_row * (VNBITS(priv->vl_bpix) / 8);
481 }
482
exynos_fb_of_to_plat(struct udevice * dev)483 int exynos_fb_of_to_plat(struct udevice *dev)
484 {
485 struct exynos_fb_priv *priv = dev_get_priv(dev);
486 unsigned int node = dev_of_offset(dev);
487 const void *blob = gd->fdt_blob;
488 fdt_addr_t addr;
489
490 addr = dev_read_addr(dev);
491 if (addr == FDT_ADDR_T_NONE) {
492 debug("Can't get the FIMD base address\n");
493 return -EINVAL;
494 }
495 priv->reg = (struct exynos_fb *)addr;
496
497 priv->vl_col = fdtdec_get_int(blob, node, "samsung,vl-col", 0);
498 if (priv->vl_col == 0) {
499 debug("Can't get XRES\n");
500 return -ENXIO;
501 }
502
503 priv->vl_row = fdtdec_get_int(blob, node, "samsung,vl-row", 0);
504 if (priv->vl_row == 0) {
505 debug("Can't get YRES\n");
506 return -ENXIO;
507 }
508
509 priv->vl_width = fdtdec_get_int(blob, node,
510 "samsung,vl-width", 0);
511
512 priv->vl_height = fdtdec_get_int(blob, node,
513 "samsung,vl-height", 0);
514
515 priv->vl_freq = fdtdec_get_int(blob, node, "samsung,vl-freq", 0);
516 if (priv->vl_freq == 0) {
517 debug("Can't get refresh rate\n");
518 return -ENXIO;
519 }
520
521 if (fdtdec_get_bool(blob, node, "samsung,vl-clkp"))
522 priv->vl_clkp = VIDEO_ACTIVE_LOW;
523
524 if (fdtdec_get_bool(blob, node, "samsung,vl-oep"))
525 priv->vl_oep = VIDEO_ACTIVE_LOW;
526
527 if (fdtdec_get_bool(blob, node, "samsung,vl-hsp"))
528 priv->vl_hsp = VIDEO_ACTIVE_LOW;
529
530 if (fdtdec_get_bool(blob, node, "samsung,vl-vsp"))
531 priv->vl_vsp = VIDEO_ACTIVE_LOW;
532
533 if (fdtdec_get_bool(blob, node, "samsung,vl-dp"))
534 priv->vl_dp = VIDEO_ACTIVE_LOW;
535
536 priv->vl_bpix = fdtdec_get_int(blob, node, "samsung,vl-bpix", 0);
537 if (priv->vl_bpix == 0) {
538 debug("Can't get bits per pixel\n");
539 return -ENXIO;
540 }
541
542 priv->vl_hspw = fdtdec_get_int(blob, node, "samsung,vl-hspw", 0);
543 if (priv->vl_hspw == 0) {
544 debug("Can't get hsync width\n");
545 return -ENXIO;
546 }
547
548 priv->vl_hfpd = fdtdec_get_int(blob, node, "samsung,vl-hfpd", 0);
549 if (priv->vl_hfpd == 0) {
550 debug("Can't get right margin\n");
551 return -ENXIO;
552 }
553
554 priv->vl_hbpd = (u_char)fdtdec_get_int(blob, node,
555 "samsung,vl-hbpd", 0);
556 if (priv->vl_hbpd == 0) {
557 debug("Can't get left margin\n");
558 return -ENXIO;
559 }
560
561 priv->vl_vspw = (u_char)fdtdec_get_int(blob, node,
562 "samsung,vl-vspw", 0);
563 if (priv->vl_vspw == 0) {
564 debug("Can't get vsync width\n");
565 return -ENXIO;
566 }
567
568 priv->vl_vfpd = fdtdec_get_int(blob, node,
569 "samsung,vl-vfpd", 0);
570 if (priv->vl_vfpd == 0) {
571 debug("Can't get lower margin\n");
572 return -ENXIO;
573 }
574
575 priv->vl_vbpd = fdtdec_get_int(blob, node, "samsung,vl-vbpd", 0);
576 if (priv->vl_vbpd == 0) {
577 debug("Can't get upper margin\n");
578 return -ENXIO;
579 }
580
581 priv->vl_cmd_allow_len = fdtdec_get_int(blob, node,
582 "samsung,vl-cmd-allow-len", 0);
583
584 priv->win_id = fdtdec_get_int(blob, node, "samsung,winid", 0);
585 priv->init_delay = fdtdec_get_int(blob, node,
586 "samsung,init-delay", 0);
587 priv->power_on_delay = fdtdec_get_int(blob, node,
588 "samsung,power-on-delay", 0);
589 priv->reset_delay = fdtdec_get_int(blob, node,
590 "samsung,reset-delay", 0);
591 priv->interface_mode = fdtdec_get_int(blob, node,
592 "samsung,interface-mode", 0);
593 priv->mipi_enabled = fdtdec_get_int(blob, node,
594 "samsung,mipi-enabled", 0);
595 priv->dp_enabled = fdtdec_get_int(blob, node,
596 "samsung,dp-enabled", 0);
597 priv->cs_setup = fdtdec_get_int(blob, node,
598 "samsung,cs-setup", 0);
599 priv->wr_setup = fdtdec_get_int(blob, node,
600 "samsung,wr-setup", 0);
601 priv->wr_act = fdtdec_get_int(blob, node, "samsung,wr-act", 0);
602 priv->wr_hold = fdtdec_get_int(blob, node, "samsung,wr-hold", 0);
603
604 priv->logo_on = fdtdec_get_int(blob, node, "samsung,logo-on", 0);
605 if (priv->logo_on) {
606 priv->logo_width = fdtdec_get_int(blob, node,
607 "samsung,logo-width", 0);
608 priv->logo_height = fdtdec_get_int(blob, node,
609 "samsung,logo-height", 0);
610 priv->logo_addr = fdtdec_get_int(blob, node,
611 "samsung,logo-addr", 0);
612 }
613
614 priv->rgb_mode = fdtdec_get_int(blob, node,
615 "samsung,rgb-mode", 0);
616 priv->pclk_name = fdtdec_get_int(blob, node,
617 "samsung,pclk-name", 0);
618 priv->sclk_div = fdtdec_get_int(blob, node,
619 "samsung,sclk-div", 0);
620 priv->dual_lcd_enabled = fdtdec_get_int(blob, node,
621 "samsung,dual-lcd-enabled", 0);
622
623 return 0;
624 }
625
exynos_fb_probe(struct udevice * dev)626 static int exynos_fb_probe(struct udevice *dev)
627 {
628 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
629 struct exynos_fb_priv *priv = dev_get_priv(dev);
630 struct udevice *panel, *bridge;
631 struct udevice *dp;
632 int ret;
633
634 debug("%s: start\n", __func__);
635 set_system_display_ctrl();
636 set_lcd_clk();
637
638 #ifdef CONFIG_EXYNOS_MIPI_DSIM
639 exynos_init_dsim_platform_data(&panel_info);
640 #endif
641 exynos_fimd_lcd_init(dev);
642
643 ret = uclass_first_device(UCLASS_PANEL, &panel);
644 if (ret) {
645 printf("LCD panel failed to probe\n");
646 return ret;
647 }
648 if (!panel) {
649 printf("LCD panel not found\n");
650 return -ENODEV;
651 }
652
653 ret = uclass_first_device(UCLASS_DISPLAY, &dp);
654 if (ret) {
655 debug("%s: Display device error %d\n", __func__, ret);
656 return ret;
657 }
658 if (!dev) {
659 debug("%s: Display device missing\n", __func__);
660 return -ENODEV;
661 }
662 ret = display_enable(dp, 18, NULL);
663 if (ret) {
664 debug("%s: Display enable error %d\n", __func__, ret);
665 return ret;
666 }
667
668 /* backlight / pwm */
669 ret = panel_enable_backlight(panel);
670 if (ret) {
671 debug("%s: backlight error: %d\n", __func__, ret);
672 return ret;
673 }
674
675 ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &bridge);
676 if (!ret)
677 ret = video_bridge_set_backlight(bridge, 80);
678 if (ret) {
679 debug("%s: No video bridge, or no backlight on bridge\n",
680 __func__);
681 exynos_pinmux_config(PERIPH_ID_PWM0, 0);
682 }
683
684 uc_priv->xsize = priv->vl_col;
685 uc_priv->ysize = priv->vl_row;
686 uc_priv->bpix = priv->vl_bpix;
687
688 /* Enable flushing after LCD writes if requested */
689 video_set_flush_dcache(dev, true);
690
691 return 0;
692 }
693
exynos_fb_bind(struct udevice * dev)694 static int exynos_fb_bind(struct udevice *dev)
695 {
696 struct video_uc_plat *plat = dev_get_uclass_plat(dev);
697
698 /* This is the maximum panel size we expect to see */
699 plat->size = 1920 * 1080 * 2;
700
701 return 0;
702 }
703
704 static const struct video_ops exynos_fb_ops = {
705 };
706
707 static const struct udevice_id exynos_fb_ids[] = {
708 { .compatible = "samsung,exynos-fimd" },
709 { }
710 };
711
712 U_BOOT_DRIVER(exynos_fb) = {
713 .name = "exynos_fb",
714 .id = UCLASS_VIDEO,
715 .of_match = exynos_fb_ids,
716 .ops = &exynos_fb_ops,
717 .bind = exynos_fb_bind,
718 .probe = exynos_fb_probe,
719 .of_to_plat = exynos_fb_of_to_plat,
720 .priv_auto = sizeof(struct exynos_fb_priv),
721 };
722