1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2017 NXP 4 */ 5 6 #ifndef __ASM_ARCH_IMX8M_REGS_H__ 7 #define __ASM_ARCH_IMX8M_REGS_H__ 8 9 #define ARCH_MXC 10 11 #include <asm/mach-imx/regs-lcdif.h> 12 13 #define ROM_VERSION_A0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800 14 #define ROM_VERSION_B0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800 15 16 #define M4_BOOTROM_BASE_ADDR 0x007E0000 17 18 #define GPIO1_BASE_ADDR 0X30200000 19 #define GPIO2_BASE_ADDR 0x30210000 20 #define GPIO3_BASE_ADDR 0x30220000 21 #define GPIO4_BASE_ADDR 0x30230000 22 #define GPIO5_BASE_ADDR 0x30240000 23 #define WDOG1_BASE_ADDR 0x30280000 24 #define WDOG2_BASE_ADDR 0x30290000 25 #define WDOG3_BASE_ADDR 0x302A0000 26 #define IOMUXC_BASE_ADDR 0x30330000 27 #define IOMUXC_GPR_BASE_ADDR 0x30340000 28 #define OCOTP_BASE_ADDR 0x30350000 29 #define ANATOP_BASE_ADDR 0x30360000 30 #define CCM_BASE_ADDR 0x30380000 31 #define SRC_BASE_ADDR 0x30390000 32 #define GPC_BASE_ADDR 0x303A0000 33 34 #define SYSCNT_RD_BASE_ADDR 0x306A0000 35 #define SYSCNT_CMP_BASE_ADDR 0x306B0000 36 #define SYSCNT_CTRL_BASE_ADDR 0x306C0000 37 38 #define UART1_BASE_ADDR 0x30860000 39 #define UART3_BASE_ADDR 0x30880000 40 #define UART2_BASE_ADDR 0x30890000 41 #define I2C1_BASE_ADDR 0x30A20000 42 #define I2C2_BASE_ADDR 0x30A30000 43 #define I2C3_BASE_ADDR 0x30A40000 44 #define I2C4_BASE_ADDR 0x30A50000 45 #define UART4_BASE_ADDR 0x30A60000 46 #define USDHC1_BASE_ADDR 0x30B40000 47 #define USDHC2_BASE_ADDR 0x30B50000 48 #ifdef CONFIG_IMX8MM 49 #define USDHC3_BASE_ADDR 0x30B60000 50 #endif 51 52 #define TZASC_BASE_ADDR 0x32F80000 53 54 #define MXS_LCDIF_BASE IS_ENABLED(CONFIG_IMX8MQ) ? \ 55 0x30320000 : 0x32e00000 56 57 #define SRC_IPS_BASE_ADDR 0x30390000 58 #define SRC_DDRC_RCR_ADDR 0x30391000 59 #define SRC_DDRC2_RCR_ADDR 0x30391004 60 61 #define DDRC_DDR_SS_GPR0 0x3d000000 62 #define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000)) 63 #define DDR_CSD1_BASE_ADDR 0x40000000 64 65 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000 66 #define FEC_QUIRK_ENET_MAC 67 68 #define CAAM_ARB_BASE_ADDR (0x00100000) 69 #define CAAM_ARB_END_ADDR (0x00107FFF) 70 #define CAAM_IPS_BASE_ADDR (0x30900000) 71 #define CONFIG_SYS_FSL_SEC_OFFSET (0) 72 #define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ 73 CONFIG_SYS_FSL_SEC_OFFSET) 74 #define CONFIG_SYS_FSL_JR0_OFFSET (0x1000) 75 #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \ 76 CONFIG_SYS_FSL_JR0_OFFSET) 77 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 78 #if !defined(__ASSEMBLY__) 79 #include <asm/types.h> 80 #include <linux/bitops.h> 81 #include <stdbool.h> 82 83 #define GPR_TZASC_EN BIT(0) 84 #define GPR_TZASC_EN_LOCK BIT(16) 85 86 #define SRC_SCR_M4_ENABLE_OFFSET 3 87 #define SRC_SCR_M4_ENABLE_MASK BIT(3) 88 #define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 0 89 #define SRC_SCR_M4C_NON_SCLR_RST_MASK BIT(0) 90 #define SRC_DDR1_ENABLE_MASK 0x8F000000UL 91 #define SRC_DDR2_ENABLE_MASK 0x8F000000UL 92 #define SRC_DDR1_RCR_PHY_PWROKIN_N_MASK BIT(3) 93 #define SRC_DDR1_RCR_PHY_RESET_MASK BIT(2) 94 #define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1) 95 #define SRC_DDR1_RCR_PRESET_N_MASK BIT(0) 96 97 struct iomuxc_gpr_base_regs { 98 u32 gpr[47]; 99 }; 100 101 struct ocotp_regs { 102 u32 ctrl; 103 u32 ctrl_set; 104 u32 ctrl_clr; 105 u32 ctrl_tog; 106 u32 timing; 107 u32 rsvd0[3]; 108 u32 data; 109 u32 rsvd1[3]; 110 u32 read_ctrl; 111 u32 rsvd2[3]; 112 u32 read_fuse_data; 113 u32 rsvd3[3]; 114 u32 sw_sticky; 115 u32 rsvd4[3]; 116 u32 scs; 117 u32 scs_set; 118 u32 scs_clr; 119 u32 scs_tog; 120 u32 crc_addr; 121 u32 rsvd5[3]; 122 u32 crc_value; 123 u32 rsvd6[3]; 124 u32 version; 125 u32 rsvd7[0xdb]; 126 127 /* fuse banks */ 128 struct fuse_bank { 129 u32 fuse_regs[0x10]; 130 } bank[0]; 131 }; 132 133 #ifdef CONFIG_IMX8MP 134 struct fuse_bank0_regs { 135 u32 lock; 136 u32 rsvd0[7]; 137 u32 uid_low; 138 u32 rsvd1[3]; 139 u32 uid_high; 140 u32 rsvd2[3]; 141 }; 142 #else 143 struct fuse_bank0_regs { 144 u32 lock; 145 u32 rsvd0[3]; 146 u32 uid_low; 147 u32 rsvd1[3]; 148 u32 uid_high; 149 u32 rsvd2[7]; 150 }; 151 #endif 152 153 struct fuse_bank1_regs { 154 u32 tester3; 155 u32 rsvd0[3]; 156 u32 tester4; 157 u32 rsvd1[3]; 158 u32 tester5; 159 u32 rsvd2[3]; 160 u32 cfg0; 161 u32 rsvd3[3]; 162 }; 163 164 struct fuse_bank3_regs { 165 u32 mem_trim0; 166 u32 rsvd0[3]; 167 u32 mem_trim1; 168 u32 rsvd1[3]; 169 u32 mem_trim2; 170 u32 rsvd2[3]; 171 u32 ana0; 172 u32 rsvd3[3]; 173 }; 174 175 struct fuse_bank9_regs { 176 u32 mac_addr0; 177 u32 rsvd0[3]; 178 u32 mac_addr1; 179 u32 rsvd1[11]; 180 }; 181 182 struct fuse_bank38_regs { 183 u32 ana_trim1; /* trim0 is at 0xD70, bank 37*/ 184 u32 rsvd0[3]; 185 u32 ana_trim2; 186 u32 rsvd1[3]; 187 u32 ana_trim3; 188 u32 rsvd2[3]; 189 u32 ana_trim4; 190 u32 rsvd3[3]; 191 }; 192 193 struct fuse_bank39_regs { 194 u32 ana_trim5; 195 u32 rsvd[15]; 196 }; 197 198 #ifdef CONFIG_IMX8MQ 199 struct anamix_pll { 200 u32 audio_pll1_cfg0; 201 u32 audio_pll1_cfg1; 202 u32 audio_pll2_cfg0; 203 u32 audio_pll2_cfg1; 204 u32 video_pll_cfg0; 205 u32 video_pll_cfg1; 206 u32 gpu_pll_cfg0; 207 u32 gpu_pll_cfg1; 208 u32 vpu_pll_cfg0; 209 u32 vpu_pll_cfg1; 210 u32 arm_pll_cfg0; 211 u32 arm_pll_cfg1; 212 u32 sys_pll1_cfg0; 213 u32 sys_pll1_cfg1; 214 u32 sys_pll1_cfg2; 215 u32 sys_pll2_cfg0; 216 u32 sys_pll2_cfg1; 217 u32 sys_pll2_cfg2; 218 u32 sys_pll3_cfg0; 219 u32 sys_pll3_cfg1; 220 u32 sys_pll3_cfg2; 221 u32 video_pll2_cfg0; 222 u32 video_pll2_cfg1; 223 u32 video_pll2_cfg2; 224 u32 dram_pll_cfg0; 225 u32 dram_pll_cfg1; 226 u32 dram_pll_cfg2; 227 u32 digprog; 228 u32 osc_misc_cfg; 229 u32 pllout_monitor_cfg; 230 u32 frac_pllout_div_cfg; 231 u32 sscg_pllout_div_cfg; 232 }; 233 #else 234 struct anamix_pll { 235 u32 audio_pll1_gnrl_ctl; 236 u32 audio_pll1_fdiv_ctl0; 237 u32 audio_pll1_fdiv_ctl1; 238 u32 audio_pll1_sscg_ctl; 239 u32 audio_pll1_mnit_ctl; 240 u32 audio_pll2_gnrl_ctl; 241 u32 audio_pll2_fdiv_ctl0; 242 u32 audio_pll2_fdiv_ctl1; 243 u32 audio_pll2_sscg_ctl; 244 u32 audio_pll2_mnit_ctl; 245 u32 video_pll1_gnrl_ctl; 246 u32 video_pll1_fdiv_ctl0; 247 u32 video_pll1_fdiv_ctl1; 248 u32 video_pll1_sscg_ctl; 249 u32 video_pll1_mnit_ctl; 250 u32 reserved[5]; 251 u32 dram_pll_gnrl_ctl; 252 u32 dram_pll_fdiv_ctl0; 253 u32 dram_pll_fdiv_ctl1; 254 u32 dram_pll_sscg_ctl; 255 u32 dram_pll_mnit_ctl; 256 u32 gpu_pll_gnrl_ctl; 257 u32 gpu_pll_div_ctl; 258 u32 gpu_pll_locked_ctl1; 259 u32 gpu_pll_mnit_ctl; 260 u32 vpu_pll_gnrl_ctl; 261 u32 vpu_pll_div_ctl; 262 u32 vpu_pll_locked_ctl1; 263 u32 vpu_pll_mnit_ctl; 264 u32 arm_pll_gnrl_ctl; 265 u32 arm_pll_div_ctl; 266 u32 arm_pll_locked_ctl1; 267 u32 arm_pll_mnit_ctl; 268 u32 sys_pll1_gnrl_ctl; 269 u32 sys_pll1_div_ctl; 270 u32 sys_pll1_locked_ctl1; 271 u32 reserved2[24]; 272 u32 sys_pll1_mnit_ctl; 273 u32 sys_pll2_gnrl_ctl; 274 u32 sys_pll2_div_ctl; 275 u32 sys_pll2_locked_ctl1; 276 u32 sys_pll2_mnit_ctl; 277 u32 sys_pll3_gnrl_ctl; 278 u32 sys_pll3_div_ctl; 279 u32 sys_pll3_locked_ctl1; 280 u32 sys_pll3_mnit_ctl; 281 u32 anamix_misc_ctl; 282 u32 anamix_clk_mnit_ctl; 283 u32 reserved3[437]; 284 u32 digprog; 285 }; 286 #endif 287 288 /* System Reset Controller (SRC) */ 289 struct src { 290 u32 scr; 291 u32 a53rcr; 292 u32 a53rcr1; 293 u32 m4rcr; 294 u32 reserved1[4]; 295 u32 usbophy1_rcr; 296 u32 usbophy2_rcr; 297 u32 mipiphy_rcr; 298 u32 pciephy_rcr; 299 u32 hdmi_rcr; 300 u32 disp_rcr; 301 u32 reserved2[2]; 302 u32 gpu_rcr; 303 u32 vpu_rcr; 304 u32 pcie2_rcr; 305 u32 mipiphy1_rcr; 306 u32 mipiphy2_rcr; 307 u32 reserved3; 308 u32 sbmr1; 309 u32 srsr; 310 u32 reserved4[2]; 311 u32 sisr; 312 u32 simr; 313 u32 sbmr2; 314 u32 gpr1; 315 u32 gpr2; 316 u32 gpr3; 317 u32 gpr4; 318 u32 gpr5; 319 u32 gpr6; 320 u32 gpr7; 321 u32 gpr8; 322 u32 gpr9; 323 u32 gpr10; 324 u32 reserved5[985]; 325 u32 ddr1_rcr; 326 u32 ddr2_rcr; 327 }; 328 329 #define WDOG_WDT_MASK BIT(3) 330 #define WDOG_WDZST_MASK BIT(0) 331 struct wdog_regs { 332 u16 wcr; /* Control */ 333 u16 wsr; /* Service */ 334 u16 wrsr; /* Reset Status */ 335 u16 wicr; /* Interrupt Control */ 336 u16 wmcr; /* Miscellaneous Control */ 337 }; 338 339 struct bootrom_sw_info { 340 u8 reserved_1; 341 u8 boot_dev_instance; 342 u8 boot_dev_type; 343 u8 reserved_2; 344 u32 core_freq; 345 u32 axi_freq; 346 u32 ddr_freq; 347 u32 tick_freq; 348 u32 reserved_3[3]; 349 }; 350 351 #define ROM_SW_INFO_ADDR_B0 (IS_ENABLED(CONFIG_IMX8MQ) ? 0x00000968 :\ 352 0x000009e8) 353 #define ROM_SW_INFO_ADDR_A0 0x000009e8 354 355 #define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \ 356 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 : \ 357 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_B0 358 359 struct gpc_reg { 360 u32 lpcr_bsc; 361 u32 lpcr_ad; 362 u32 lpcr_cpu1; 363 u32 lpcr_cpu2; 364 u32 lpcr_cpu3; 365 u32 slpcr; 366 u32 mst_cpu_mapping; 367 u32 mmdc_cpu_mapping; 368 u32 mlpcr; 369 u32 pgc_ack_sel; 370 u32 pgc_ack_sel_m4; 371 u32 gpc_misc; 372 u32 imr1_core0; 373 u32 imr2_core0; 374 u32 imr3_core0; 375 u32 imr4_core0; 376 u32 imr1_core1; 377 u32 imr2_core1; 378 u32 imr3_core1; 379 u32 imr4_core1; 380 u32 imr1_cpu1; 381 u32 imr2_cpu1; 382 u32 imr3_cpu1; 383 u32 imr4_cpu1; 384 u32 imr1_cpu3; 385 u32 imr2_cpu3; 386 u32 imr3_cpu3; 387 u32 imr4_cpu3; 388 u32 isr1_cpu0; 389 u32 isr2_cpu0; 390 u32 isr3_cpu0; 391 u32 isr4_cpu0; 392 u32 isr1_cpu1; 393 u32 isr2_cpu1; 394 u32 isr3_cpu1; 395 u32 isr4_cpu1; 396 u32 isr1_cpu2; 397 u32 isr2_cpu2; 398 u32 isr3_cpu2; 399 u32 isr4_cpu2; 400 u32 isr1_cpu3; 401 u32 isr2_cpu3; 402 u32 isr3_cpu3; 403 u32 isr4_cpu3; 404 u32 slt0_cfg; 405 u32 slt1_cfg; 406 u32 slt2_cfg; 407 u32 slt3_cfg; 408 u32 slt4_cfg; 409 u32 slt5_cfg; 410 u32 slt6_cfg; 411 u32 slt7_cfg; 412 u32 slt8_cfg; 413 u32 slt9_cfg; 414 u32 slt10_cfg; 415 u32 slt11_cfg; 416 u32 slt12_cfg; 417 u32 slt13_cfg; 418 u32 slt14_cfg; 419 u32 pgc_cpu_0_1_mapping; 420 u32 cpu_pgc_up_trg; 421 u32 mix_pgc_up_trg; 422 u32 pu_pgc_up_trg; 423 u32 cpu_pgc_dn_trg; 424 u32 mix_pgc_dn_trg; 425 u32 pu_pgc_dn_trg; 426 u32 lpcr_bsc2; 427 u32 pgc_cpu_2_3_mapping; 428 u32 lps_cpu0; 429 u32 lps_cpu1; 430 u32 lps_cpu2; 431 u32 lps_cpu3; 432 u32 gpc_gpr; 433 u32 gtor; 434 u32 debug_addr1; 435 u32 debug_addr2; 436 u32 cpu_pgc_up_status1; 437 u32 mix_pgc_up_status0; 438 u32 mix_pgc_up_status1; 439 u32 mix_pgc_up_status2; 440 u32 m4_mix_pgc_up_status0; 441 u32 m4_mix_pgc_up_status1; 442 u32 m4_mix_pgc_up_status2; 443 u32 pu_pgc_up_status0; 444 u32 pu_pgc_up_status1; 445 u32 pu_pgc_up_status2; 446 u32 m4_pu_pgc_up_status0; 447 u32 m4_pu_pgc_up_status1; 448 u32 m4_pu_pgc_up_status2; 449 u32 a53_lp_io_0; 450 u32 a53_lp_io_1; 451 u32 a53_lp_io_2; 452 u32 cpu_pgc_dn_status1; 453 u32 mix_pgc_dn_status0; 454 u32 mix_pgc_dn_status1; 455 u32 mix_pgc_dn_status2; 456 u32 m4_mix_pgc_dn_status0; 457 u32 m4_mix_pgc_dn_status1; 458 u32 m4_mix_pgc_dn_status2; 459 u32 pu_pgc_dn_status0; 460 u32 pu_pgc_dn_status1; 461 u32 pu_pgc_dn_status2; 462 u32 m4_pu_pgc_dn_status0; 463 u32 m4_pu_pgc_dn_status1; 464 u32 m4_pu_pgc_dn_status2; 465 u32 res[3]; 466 u32 mix_pdn_flg; 467 u32 pu_pdn_flg; 468 u32 m4_mix_pdn_flg; 469 u32 m4_pu_pdn_flg; 470 u32 imr1_core2; 471 u32 imr2_core2; 472 u32 imr3_core2; 473 u32 imr4_core2; 474 u32 imr1_core3; 475 u32 imr2_core3; 476 u32 imr3_core3; 477 u32 imr4_core3; 478 u32 pgc_ack_sel_pu; 479 u32 pgc_ack_sel_m4_pu; 480 u32 slt15_cfg; 481 u32 slt16_cfg; 482 u32 slt17_cfg; 483 u32 slt18_cfg; 484 u32 slt19_cfg; 485 u32 gpc_pu_pwrhsk; 486 u32 slt0_cfg_pu; 487 u32 slt1_cfg_pu; 488 u32 slt2_cfg_pu; 489 u32 slt3_cfg_pu; 490 u32 slt4_cfg_pu; 491 u32 slt5_cfg_pu; 492 u32 slt6_cfg_pu; 493 u32 slt7_cfg_pu; 494 u32 slt8_cfg_pu; 495 u32 slt9_cfg_pu; 496 u32 slt10_cfg_pu; 497 u32 slt11_cfg_pu; 498 u32 slt12_cfg_pu; 499 u32 slt13_cfg_pu; 500 u32 slt14_cfg_pu; 501 u32 slt15_cfg_pu; 502 u32 slt16_cfg_pu; 503 u32 slt17_cfg_pu; 504 u32 slt18_cfg_pu; 505 u32 slt19_cfg_pu; 506 }; 507 508 struct pgc_reg { 509 u32 pgcr; 510 u32 pgpupscr; 511 u32 pgpdnscr; 512 u32 pgsr; 513 u32 pgauxsw; 514 u32 pgdr; 515 }; 516 #endif 517 #endif 518