1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2019 DENX Software Engineering
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
5 *
6 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
7 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
8 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
9 *
10 */
11
12 #include <common.h>
13 #include <asm/io.h>
14 #include <malloc.h>
15 #include <clk-uclass.h>
16 #include <dm/device.h>
17 #include <dm/devres.h>
18 #include <dm/uclass.h>
19 #include <dm/lists.h>
20 #include <dm/device-internal.h>
21 #include <linux/bug.h>
22 #include <linux/clk-provider.h>
23 #include <linux/err.h>
24 #include <linux/log2.h>
25 #include <div64.h>
26 #include <clk.h>
27 #include "clk.h"
28
29 #define UBOOT_DM_CLK_CCF_DIVIDER "ccf_clk_divider"
30
clk_divider_get_table_div(const struct clk_div_table * table,unsigned int val)31 unsigned int clk_divider_get_table_div(const struct clk_div_table *table,
32 unsigned int val)
33 {
34 const struct clk_div_table *clkt;
35
36 for (clkt = table; clkt->div; clkt++)
37 if (clkt->val == val)
38 return clkt->div;
39 return 0;
40 }
41
_get_div(const struct clk_div_table * table,unsigned int val,unsigned long flags,u8 width)42 static unsigned int _get_div(const struct clk_div_table *table,
43 unsigned int val, unsigned long flags, u8 width)
44 {
45 if (flags & CLK_DIVIDER_ONE_BASED)
46 return val;
47 if (flags & CLK_DIVIDER_POWER_OF_TWO)
48 return 1 << val;
49 if (flags & CLK_DIVIDER_MAX_AT_ZERO)
50 return val ? val : clk_div_mask(width) + 1;
51 if (table)
52 return clk_divider_get_table_div(table, val);
53 return val + 1;
54 }
55
divider_recalc_rate(struct clk * hw,unsigned long parent_rate,unsigned int val,const struct clk_div_table * table,unsigned long flags,unsigned long width)56 unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
57 unsigned int val,
58 const struct clk_div_table *table,
59 unsigned long flags, unsigned long width)
60 {
61 unsigned int div;
62
63 div = _get_div(table, val, flags, width);
64 if (!div) {
65 WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
66 "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
67 clk_hw_get_name(hw));
68 return parent_rate;
69 }
70
71 return DIV_ROUND_UP_ULL((u64)parent_rate, div);
72 }
73
clk_divider_recalc_rate(struct clk * clk)74 static ulong clk_divider_recalc_rate(struct clk *clk)
75 {
76 struct clk_divider *divider = to_clk_divider(clk);
77 unsigned long parent_rate = clk_get_parent_rate(clk);
78 unsigned int val;
79
80 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
81 val = divider->io_divider_val;
82 #else
83 val = readl(divider->reg);
84 #endif
85 val >>= divider->shift;
86 val &= clk_div_mask(divider->width);
87
88 return divider_recalc_rate(clk, parent_rate, val, divider->table,
89 divider->flags, divider->width);
90 }
91
clk_divider_is_valid_table_div(const struct clk_div_table * table,unsigned int div)92 bool clk_divider_is_valid_table_div(const struct clk_div_table *table,
93 unsigned int div)
94 {
95 const struct clk_div_table *clkt;
96
97 for (clkt = table; clkt->div; clkt++)
98 if (clkt->div == div)
99 return true;
100 return false;
101 }
102
clk_divider_is_valid_div(const struct clk_div_table * table,unsigned int div,unsigned long flags)103 bool clk_divider_is_valid_div(const struct clk_div_table *table,
104 unsigned int div, unsigned long flags)
105 {
106 if (flags & CLK_DIVIDER_POWER_OF_TWO)
107 return is_power_of_2(div);
108 if (table)
109 return clk_divider_is_valid_table_div(table, div);
110 return true;
111 }
112
clk_divider_get_table_val(const struct clk_div_table * table,unsigned int div)113 unsigned int clk_divider_get_table_val(const struct clk_div_table *table,
114 unsigned int div)
115 {
116 const struct clk_div_table *clkt;
117
118 for (clkt = table; clkt->div; clkt++)
119 if (clkt->div == div)
120 return clkt->val;
121 return 0;
122 }
123
_get_val(const struct clk_div_table * table,unsigned int div,unsigned long flags,u8 width)124 static unsigned int _get_val(const struct clk_div_table *table,
125 unsigned int div, unsigned long flags, u8 width)
126 {
127 if (flags & CLK_DIVIDER_ONE_BASED)
128 return div;
129 if (flags & CLK_DIVIDER_POWER_OF_TWO)
130 return __ffs(div);
131 if (flags & CLK_DIVIDER_MAX_AT_ZERO)
132 return (div == clk_div_mask(width) + 1) ? 0 : div;
133 if (table)
134 return clk_divider_get_table_val(table, div);
135 return div - 1;
136 }
divider_get_val(unsigned long rate,unsigned long parent_rate,const struct clk_div_table * table,u8 width,unsigned long flags)137 int divider_get_val(unsigned long rate, unsigned long parent_rate,
138 const struct clk_div_table *table, u8 width,
139 unsigned long flags)
140 {
141 unsigned int div, value;
142
143 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
144
145 if (!clk_divider_is_valid_div(table, div, flags))
146 return -EINVAL;
147
148 value = _get_val(table, div, flags, width);
149
150 return min_t(unsigned int, value, clk_div_mask(width));
151 }
152
clk_divider_set_rate(struct clk * clk,unsigned long rate)153 static ulong clk_divider_set_rate(struct clk *clk, unsigned long rate)
154 {
155 struct clk_divider *divider = to_clk_divider(clk);
156 unsigned long parent_rate = clk_get_parent_rate(clk);
157 int value;
158 u32 val;
159
160 value = divider_get_val(rate, parent_rate, divider->table,
161 divider->width, divider->flags);
162 if (value < 0)
163 return value;
164
165 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
166 val = clk_div_mask(divider->width) << (divider->shift + 16);
167 } else {
168 val = readl(divider->reg);
169 val &= ~(clk_div_mask(divider->width) << divider->shift);
170 }
171 val |= (u32)value << divider->shift;
172 writel(val, divider->reg);
173
174 return clk_get_rate(clk);
175 }
176
177 const struct clk_ops clk_divider_ops = {
178 .get_rate = clk_divider_recalc_rate,
179 .set_rate = clk_divider_set_rate,
180 };
181
_register_divider(struct device * dev,const char * name,const char * parent_name,unsigned long flags,void __iomem * reg,u8 shift,u8 width,u8 clk_divider_flags,const struct clk_div_table * table)182 static struct clk *_register_divider(struct device *dev, const char *name,
183 const char *parent_name, unsigned long flags,
184 void __iomem *reg, u8 shift, u8 width,
185 u8 clk_divider_flags, const struct clk_div_table *table)
186 {
187 struct clk_divider *div;
188 struct clk *clk;
189 int ret;
190
191 if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
192 if (width + shift > 16) {
193 pr_warn("divider value exceeds LOWORD field\n");
194 return ERR_PTR(-EINVAL);
195 }
196 }
197
198 /* allocate the divider */
199 div = kzalloc(sizeof(*div), GFP_KERNEL);
200 if (!div)
201 return ERR_PTR(-ENOMEM);
202
203 /* struct clk_divider assignments */
204 div->reg = reg;
205 div->shift = shift;
206 div->width = width;
207 div->flags = clk_divider_flags;
208 div->table = table;
209 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
210 div->io_divider_val = *(u32 *)reg;
211 #endif
212
213 /* register the clock */
214 clk = &div->clk;
215 clk->flags = flags;
216
217 ret = clk_register(clk, UBOOT_DM_CLK_CCF_DIVIDER, name, parent_name);
218 if (ret) {
219 kfree(div);
220 return ERR_PTR(ret);
221 }
222
223 return clk;
224 }
225
clk_register_divider(struct device * dev,const char * name,const char * parent_name,unsigned long flags,void __iomem * reg,u8 shift,u8 width,u8 clk_divider_flags)226 struct clk *clk_register_divider(struct device *dev, const char *name,
227 const char *parent_name, unsigned long flags,
228 void __iomem *reg, u8 shift, u8 width,
229 u8 clk_divider_flags)
230 {
231 struct clk *clk;
232
233 clk = _register_divider(dev, name, parent_name, flags, reg, shift,
234 width, clk_divider_flags, NULL);
235 if (IS_ERR(clk))
236 return ERR_CAST(clk);
237 return clk;
238 }
239
240 U_BOOT_DRIVER(ccf_clk_divider) = {
241 .name = UBOOT_DM_CLK_CCF_DIVIDER,
242 .id = UCLASS_CLK,
243 .ops = &clk_divider_ops,
244 .flags = DM_FLAG_PRE_RELOC,
245 };
246