1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2019 Western Digital Corporation or its affiliates.
4 *
5 * Author: Anup Patel <anup.patel@wdc.com>
6 */
7
8 #include <common.h>
9 #include <clk-uclass.h>
10 #include <div64.h>
11 #include <dm.h>
12 #include <linux/err.h>
13
14 struct clk_fixed_factor {
15 struct clk parent;
16 unsigned int div;
17 unsigned int mult;
18 };
19
20 #define to_clk_fixed_factor(dev) \
21 ((struct clk_fixed_factor *)dev_get_plat(dev))
22
clk_fixed_factor_get_rate(struct clk * clk)23 static ulong clk_fixed_factor_get_rate(struct clk *clk)
24 {
25 uint64_t rate;
26 struct clk_fixed_factor *ff = to_clk_fixed_factor(clk->dev);
27
28 rate = clk_get_rate(&ff->parent);
29 if (IS_ERR_VALUE(rate))
30 return rate;
31
32 do_div(rate, ff->div);
33
34 return rate * ff->mult;
35 }
36
37 const struct clk_ops clk_fixed_factor_ops = {
38 .get_rate = clk_fixed_factor_get_rate,
39 };
40
clk_fixed_factor_of_to_plat(struct udevice * dev)41 static int clk_fixed_factor_of_to_plat(struct udevice *dev)
42 {
43 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
44 int err;
45 struct clk_fixed_factor *ff = to_clk_fixed_factor(dev);
46
47 err = clk_get_by_index(dev, 0, &ff->parent);
48 if (err)
49 return err;
50
51 ff->div = dev_read_u32_default(dev, "clock-div", 1);
52 ff->mult = dev_read_u32_default(dev, "clock-mult", 1);
53 #endif
54
55 return 0;
56 }
57
58 static const struct udevice_id clk_fixed_factor_match[] = {
59 {
60 .compatible = "fixed-factor-clock",
61 },
62 { /* sentinel */ }
63 };
64
65 U_BOOT_DRIVER(clk_fixed_factor) = {
66 .name = "fixed_factor_clock",
67 .id = UCLASS_CLK,
68 .of_match = clk_fixed_factor_match,
69 .of_to_plat = clk_fixed_factor_of_to_plat,
70 .plat_auto = sizeof(struct clk_fixed_factor),
71 .ops = &clk_fixed_factor_ops,
72 };
73