1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2020 Microchip Technology Inc.
4 * Padmarao Begari <padmarao.begari@microchip.com>
5 */
6 #include <common.h>
7 #include <clk.h>
8 #include <clk-uclass.h>
9 #include <dm.h>
10 #include <log.h>
11 #include <dm/device.h>
12 #include <dm/devres.h>
13 #include <dm/uclass.h>
14 #include <linux/err.h>
15
16 #include "mpfs_clk.h"
17
18 /* All methods are delegated to CCF clocks */
19
mpfs_clk_get_rate(struct clk * clk)20 static ulong mpfs_clk_get_rate(struct clk *clk)
21 {
22 struct clk *c;
23 int err = clk_get_by_id(clk->id, &c);
24
25 if (err)
26 return err;
27 return clk_get_rate(c);
28 }
29
mpfs_clk_set_rate(struct clk * clk,unsigned long rate)30 static ulong mpfs_clk_set_rate(struct clk *clk, unsigned long rate)
31 {
32 struct clk *c;
33 int err = clk_get_by_id(clk->id, &c);
34
35 if (err)
36 return err;
37 return clk_set_rate(c, rate);
38 }
39
mpfs_clk_set_parent(struct clk * clk,struct clk * parent)40 static int mpfs_clk_set_parent(struct clk *clk, struct clk *parent)
41 {
42 struct clk *c, *p;
43 int err = clk_get_by_id(clk->id, &c);
44
45 if (err)
46 return err;
47
48 err = clk_get_by_id(parent->id, &p);
49 if (err)
50 return err;
51
52 return clk_set_parent(c, p);
53 }
54
mpfs_clk_endisable(struct clk * clk,bool enable)55 static int mpfs_clk_endisable(struct clk *clk, bool enable)
56 {
57 struct clk *c;
58 int err = clk_get_by_id(clk->id, &c);
59
60 if (err)
61 return err;
62 return enable ? clk_enable(c) : clk_disable(c);
63 }
64
mpfs_clk_enable(struct clk * clk)65 static int mpfs_clk_enable(struct clk *clk)
66 {
67 return mpfs_clk_endisable(clk, true);
68 }
69
mpfs_clk_disable(struct clk * clk)70 static int mpfs_clk_disable(struct clk *clk)
71 {
72 return mpfs_clk_endisable(clk, false);
73 }
74
mpfs_clk_probe(struct udevice * dev)75 static int mpfs_clk_probe(struct udevice *dev)
76 {
77 int ret;
78 void __iomem *base;
79 u32 clk_rate;
80 const char *parent_clk_name;
81 struct clk *clk = dev_get_priv(dev);
82
83 base = dev_read_addr_ptr(dev);
84 if (!base)
85 return -EINVAL;
86
87 ret = clk_get_by_index(dev, 0, clk);
88 if (ret)
89 return ret;
90
91 dev_read_u32(clk->dev, "clock-frequency", &clk_rate);
92 parent_clk_name = clk->dev->name;
93
94 ret = mpfs_clk_register_cfgs(base, clk_rate, parent_clk_name);
95 if (ret)
96 return ret;
97
98 ret = mpfs_clk_register_periphs(base, clk_rate, "clk_ahb");
99
100 return ret;
101 }
102
103 static const struct clk_ops mpfs_clk_ops = {
104 .set_rate = mpfs_clk_set_rate,
105 .get_rate = mpfs_clk_get_rate,
106 .set_parent = mpfs_clk_set_parent,
107 .enable = mpfs_clk_enable,
108 .disable = mpfs_clk_disable,
109 };
110
111 static const struct udevice_id mpfs_of_match[] = {
112 { .compatible = "microchip,mpfs-clkcfg" },
113 { }
114 };
115
116 U_BOOT_DRIVER(mpfs_clk) = {
117 .name = "mpfs_clk",
118 .id = UCLASS_CLK,
119 .of_match = mpfs_of_match,
120 .ops = &mpfs_clk_ops,
121 .probe = mpfs_clk_probe,
122 .priv_auto = sizeof(struct clk),
123 .flags = DM_FLAG_PRE_RELOC,
124 };
125