1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2020 Microchip Technology Inc. 4 * Padmarao Begari <padmarao.begari@microchip.com> 5 */ 6 #ifndef __MICROCHIP_MPFS_CLK_H 7 #define __MICROCHIP_MPFS_CLK_H 8 9 #include <linux/clk-provider.h> 10 /** 11 * mpfs_clk_register_cfgs() - register configuration clocks 12 * 13 * @base: base address of the mpfs system register. 14 * @clk_rate: the mpfs pll clock rate. 15 * @parent_name: a pointer to parent clock name. 16 * @return zero on success, or a negative error code. 17 */ 18 int mpfs_clk_register_cfgs(void __iomem *base, u32 clk_rate, 19 const char *parent_name); 20 /** 21 * mpfs_clk_register_periphs() - register peripheral clocks 22 * 23 * @base: base address of the mpfs system register. 24 * @clk_rate: the mpfs pll clock rate. 25 * @parent_name: a pointer to parent clock name. 26 * @return zero on success, or a negative error code. 27 */ 28 int mpfs_clk_register_periphs(void __iomem *base, u32 clk_rate, 29 const char *parent_name); 30 /** 31 * divider_get_val() - get the clock divider value 32 * 33 * @rate: requested clock rate. 34 * @parent_rate: parent clock rate. 35 * @table: a pointer to clock divider table. 36 * @width: width of the divider bit field. 37 * @flags: common clock framework flags. 38 * @return divider value on success, or a negative error code. 39 */ 40 int divider_get_val(unsigned long rate, unsigned long parent_rate, 41 const struct clk_div_table *table, 42 u8 width, unsigned long flags); 43 44 #endif /* __MICROCHIP_MPFS_CLK_H */ 45