1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
4 *
5 * Copyright 2020 NXP
6 * Copyright (C) 2014-2015, Freescale Semiconductor
7 *
8 * Mingkai Hu <Mingkai.hu@freescale.com>
9 */
10
11/include/ "skeleton64.dtsi"
12
13/ {
14	compatible = "fsl,ls1043a";
15	interrupt-parent = <&gic>;
16
17	sysclk: sysclk {
18		compatible = "fixed-clock";
19		#clock-cells = <0>;
20		clock-frequency = <100000000>;
21		clock-output-names = "sysclk";
22	};
23
24	gic: interrupt-controller@1400000 {
25		compatible = "arm,gic-400";
26		#interrupt-cells = <3>;
27		interrupt-controller;
28		reg = <0x0 0x1401000 0 0x1000>, /* GICD */
29		      <0x0 0x1402000 0 0x2000>, /* GICC */
30		      <0x0 0x1404000 0 0x2000>, /* GICH */
31		      <0x0 0x1406000 0 0x2000>; /* GICV */
32		interrupts = <1 9 0xf08>;
33	};
34
35	soc: soc {
36		compatible = "simple-bus";
37		#address-cells = <2>;
38		#size-cells = <2>;
39		ranges;
40
41		clockgen: clocking@1ee1000 {
42			compatible = "fsl,ls1043a-clockgen";
43			reg = <0x0 0x1ee1000 0x0 0x1000>;
44			#clock-cells = <2>;
45			clocks = <&sysclk>;
46		};
47
48		dspi0: dspi@2100000 {
49			compatible = "fsl,vf610-dspi";
50			#address-cells = <1>;
51			#size-cells = <0>;
52			reg = <0x0 0x2100000 0x0 0x10000>;
53			interrupts = <0 64 0x4>;
54			clock-names = "dspi";
55			clocks = <&clockgen 4 0>;
56			num-cs = <6>;
57			big-endian;
58			status = "disabled";
59		};
60
61		dspi1: dspi@2110000 {
62			compatible = "fsl,vf610-dspi";
63			#address-cells = <1>;
64			#size-cells = <0>;
65			reg = <0x0 0x2110000 0x0 0x10000>;
66			interrupts = <0 65 0x4>;
67			clock-names = "dspi";
68			clocks = <&clockgen 4 0>;
69			num-cs = <6>;
70			big-endian;
71			status = "disabled";
72		};
73
74		esdhc: esdhc@1560000 {
75			compatible = "fsl,esdhc";
76			reg = <0x0 0x1560000 0x0 0x10000>;
77			interrupts = <0 62 0x4>;
78			big-endian;
79			bus-width = <4>;
80		};
81
82		gpio0: gpio@2300000 {
83			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
84			reg = <0x0 0x2300000 0x0 0x10000>;
85			interrupts = <0 66 0x4>;
86			gpio-controller;
87			#gpio-cells = <2>;
88			interrupt-controller;
89			#interrupt-cells = <2>;
90		};
91
92		gpio1: gpio@2310000 {
93			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
94			reg = <0x0 0x2310000 0x0 0x10000>;
95			interrupts = <0 67 0x4>;
96			gpio-controller;
97			#gpio-cells = <2>;
98			interrupt-controller;
99			#interrupt-cells = <2>;
100		};
101
102		gpio2: gpio@2320000 {
103			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
104			reg = <0x0 0x2320000 0x0 0x10000>;
105			interrupts = <0 68 0x4>;
106			gpio-controller;
107			#gpio-cells = <2>;
108			interrupt-controller;
109			#interrupt-cells = <2>;
110		};
111
112		gpio3: gpio@2330000 {
113			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
114			reg = <0x0 0x2330000 0x0 0x10000>;
115			interrupts = <0 134 0x4>;
116			gpio-controller;
117			#gpio-cells = <2>;
118			interrupt-controller;
119			#interrupt-cells = <2>;
120		};
121
122		ifc: ifc@1530000 {
123			compatible = "fsl,ifc", "simple-bus";
124			reg = <0x0 0x1530000 0x0 0x10000>;
125			interrupts = <0 43 0x4>;
126		};
127
128		i2c0: i2c@2180000 {
129			compatible = "fsl,vf610-i2c";
130			#address-cells = <1>;
131			#size-cells = <0>;
132			reg = <0x0 0x2180000 0x0 0x10000>;
133			interrupts = <0 56 0x4>;
134			clock-names = "i2c";
135			clocks = <&clockgen 4 0>;
136			status = "disabled";
137		};
138
139		i2c1: i2c@2190000 {
140			compatible = "fsl,vf610-i2c";
141			#address-cells = <1>;
142			#size-cells = <0>;
143			reg = <0x0 0x2190000 0x0 0x10000>;
144			interrupts = <0 57 0x4>;
145			clock-names = "i2c";
146			clocks = <&clockgen 4 0>;
147			status = "disabled";
148		};
149
150		i2c2: i2c@21a0000 {
151			compatible = "fsl,vf610-i2c";
152			#address-cells = <1>;
153			#size-cells = <0>;
154			reg = <0x0 0x21a0000 0x0 0x10000>;
155			interrupts = <0 58 0x4>;
156			clock-names = "i2c";
157			clocks = <&clockgen 4 0>;
158			status = "disabled";
159		};
160
161		i2c3: i2c@21b0000 {
162			compatible = "fsl,vf610-i2c";
163			#address-cells = <1>;
164			#size-cells = <0>;
165			reg = <0x0 0x21b0000 0x0 0x10000>;
166			interrupts = <0 59 0x4>;
167			clock-names = "i2c";
168			clocks = <&clockgen 4 0>;
169			status = "disabled";
170		};
171
172		duart0: serial@21c0500 {
173			compatible = "fsl,ns16550", "ns16550a";
174			reg = <0x00 0x21c0500 0x0 0x100>;
175			interrupts = <0 54 0x4>;
176			clocks = <&clockgen 4 0>;
177		};
178
179		duart1: serial@21c0600 {
180			compatible = "fsl,ns16550", "ns16550a";
181			reg = <0x00 0x21c0600 0x0 0x100>;
182			interrupts = <0 54 0x4>;
183			clocks = <&clockgen 4 0>;
184		};
185
186		duart2: serial@21d0500 {
187			compatible = "fsl,ns16550", "ns16550a";
188			reg = <0x0 0x21d0500 0x0 0x100>;
189			interrupts = <0 55 0x4>;
190			clocks = <&clockgen 4 0>;
191		};
192
193		duart3: serial@21d0600 {
194			compatible = "fsl,ns16550", "ns16550a";
195			reg = <0x0 0x21d0600 0x0 0x100>;
196			interrupts = <0 55 0x4>;
197			clocks = <&clockgen 4 0>;
198		};
199
200		lpuart0: serial@2950000 {
201			compatible = "fsl,ls1021a-lpuart";
202			reg = <0x0 0x2950000 0x0 0x1000>;
203			interrupts = <0 48 0x4>;
204			clocks = <&sysclk>;
205			clock-names = "ipg";
206			status = "disabled";
207		};
208
209		lpuart1: serial@2960000 {
210			compatible = "fsl,ls1021a-lpuart";
211			reg = <0x0 0x2960000 0x0 0x1000>;
212			interrupts = <0 49 0x4>;
213			clocks = <&sysclk>;
214			clock-names = "ipg";
215			status = "disabled";
216		};
217
218		lpuart2: serial@2970000 {
219			compatible = "fsl,ls1021a-lpuart";
220			reg = <0x0 0x2970000 0x0 0x1000>;
221			interrupts = <0 50 0x4>;
222			clock-names = "ipg";
223			clocks = <&sysclk>;
224			status = "disabled";
225		};
226
227		lpuart3: serial@2980000 {
228			compatible = "fsl,ls1021a-lpuart";
229			reg = <0x0 0x2980000 0x0 0x1000>;
230			interrupts = <0 51 0x4>;
231			clocks = <&sysclk>;
232			clock-names = "ipg";
233			status = "disabled";
234		};
235
236		lpuart4: serial@2990000 {
237			compatible = "fsl,ls1021a-lpuart";
238			reg = <0x0 0x2990000 0x0 0x1000>;
239			interrupts = <0 52 0x4>;
240			clocks = <&sysclk>;
241			clock-names = "ipg";
242			status = "disabled";
243		};
244
245		lpuart5: serial@29a0000 {
246			compatible = "fsl,ls1021a-lpuart";
247			reg = <0x0 0x29a0000 0x0 0x1000>;
248			interrupts = <0 53 0x4>;
249			clocks = <&sysclk>;
250			clock-names = "ipg";
251			status = "disabled";
252		};
253		qspi: quadspi@1550000 {
254			compatible = "fsl,ls1021a-qspi";
255			#address-cells = <1>;
256			#size-cells = <0>;
257			reg = <0x0 0x1550000 0x0 0x10000>,
258				<0x0 0x40000000 0x0 0x1000000>;
259			reg-names = "QuadSPI", "QuadSPI-memory";
260			status = "disabled";
261		};
262
263		usb0: usb3@2f00000 {
264			compatible = "fsl,layerscape-dwc3";
265			reg = <0x0 0x2f00000 0x0 0x10000>;
266			interrupts = <0 60 0x4>;
267			dr_mode = "host";
268		};
269
270		usb1: usb3@3000000 {
271			compatible = "fsl,layerscape-dwc3";
272			reg = <0x0 0x3000000 0x0 0x10000>;
273			interrupts = <0 61 0x4>;
274			dr_mode = "host";
275		};
276
277		usb2: usb3@3100000 {
278			compatible = "fsl,layerscape-dwc3";
279			reg = <0x0 0x3100000 0x0 0x10000>;
280			interrupts = <0 63 0x4>;
281			dr_mode = "host";
282		};
283
284		pcie1: pcie@3400000 {
285			compatible = "fsl,ls-pcie", "snps,dw-pcie";
286			reg = <0x00 0x03400000 0x0 0x10000   /* dbi registers */
287			       0x00 0x03410000 0x0 0x10000   /* lut registers */
288			       0x40 0x00000000 0x0 0x20000>; /* configuration space */
289			reg-names = "dbi", "lut", "config";
290			big-endian;
291			#address-cells = <3>;
292			#size-cells = <2>;
293			device_type = "pci";
294			bus-range = <0x0 0xff>;
295			ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000   /* downstream I/O */
296				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
297		};
298
299		pcie2: pcie@3500000 {
300			compatible = "fsl,ls-pcie", "snps,dw-pcie";
301			reg = <0x00 0x03500000 0x0 0x10000   /* dbi registers */
302			       0x00 0x03510000 0x0 0x10000   /* lut registers */
303			       0x48 0x00000000 0x0 0x20000>; /* configuration space */
304			reg-names = "dbi", "lut", "config";
305			big-endian;
306			#address-cells = <3>;
307			#size-cells = <2>;
308			device_type = "pci";
309			num-lanes = <2>;
310			bus-range = <0x0 0xff>;
311			ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000   /* downstream I/O */
312				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
313		};
314
315		pcie3: pcie@3600000 {
316			compatible = "fsl,ls-pcie", "snps,dw-pcie";
317			reg = <0x00 0x03600000 0x0 0x10000   /* dbi registers */
318			       0x00 0x03610000 0x0 0x10000   /* lut registers */
319			       0x50 0x00000000 0x0 0x20000>; /* configuration space */
320			reg-names = "dbi", "lut", "config";
321			big-endian;
322			#address-cells = <3>;
323			#size-cells = <2>;
324			device_type = "pci";
325			bus-range = <0x0 0xff>;
326			ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000   /* downstream I/O */
327				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
328		};
329
330		sata: sata@3200000 {
331			compatible = "fsl,ls1043a-ahci";
332			reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
333			       0x0 0x20140520 0x0 0x4>;  /* ecc sata addr*/
334			reg-names = "sata-base", "ecc-addr";
335			interrupts = <0 69 4>;
336			clocks = <&clockgen 4 0>;
337			status = "disabled";
338		};
339	};
340};
341