1// SPDX-License-Identifier: (GPL-2.0) 2/* 3 * support for the imx6 based aristainetos2c+2d boards 4 * 5 * Copyright (C) 2019 Heiko Schocher <hs@denx.de> 6 * Copyright (C) 2015 Heiko Schocher <hs@denx.de> 7 * 8 */ 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/clock/imx6qdl-clock.h> 11 12#include "imx6qdl-aristainetos2-common.dtsi" 13 14/ { 15 leds { 16 compatible = "gpio-leds"; 17 pinctrl-names = "default"; 18 pinctrl-0 = <&pinctrl_gpio>; 19 20 LED_blue { 21 label = "led_blue"; 22 gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; 23 }; 24 25 LED_green { 26 label = "led_green"; 27 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; 28 }; 29 30 LED_red { 31 label = "led_red"; 32 gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; 33 }; 34 35 LED_yellow { 36 label = "led_yellow"; 37 gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; 38 }; 39 40 LED_ena { 41 label = "led_ena"; 42 gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; 43 }; 44 }; 45}; 46 47&ecspi1 { 48 fsl,spi-num-chipselects = <3>; 49 cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH 50 &gpio4 10 GPIO_ACTIVE_HIGH 51 &gpio4 11 GPIO_ACTIVE_HIGH>; 52 pinctrl-names = "default"; 53 pinctrl-0 = <&pinctrl_ecspi1>; 54 status = "okay"; 55 pinctrl-assert-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; 56 pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; 57 58 flash: m25p80@0 { 59 #address-cells = <1>; 60 #size-cells = <1>; 61 compatible = "micron,n25q128a11", "jedec,spi-nor"; 62 spi-max-frequency = <20000000>; 63 reg = <0>; 64 }; 65}; 66 67&ecspi4 { 68 fsl,spi-num-chipselects = <2>; 69 cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>; 70 pinctrl-names = "default"; 71 pinctrl-0 = <&pinctrl_ecspi4>; 72 status = "okay"; 73}; 74 75&i2c1 { 76 tpm@20 { 77 compatible = "infineon,slb9645tt"; 78 reg = <0x20>; 79 }; 80}; 81 82&gpio7 { 83 eMMC_reset { 84 gpio-hog; 85 output-high; 86 gpios = <8 GPIO_ACTIVE_HIGH>; 87 }; 88}; 89 90&can1 { 91 pinctrl-names = "default"; 92 pinctrl-0 = <&pinctrl_flexcan1>; 93 status = "okay"; 94}; 95 96&can2 { 97 pinctrl-names = "default"; 98 pinctrl-0 = <&pinctrl_flexcan2>; 99 status = "okay"; 100}; 101 102&usdhc1 { 103 pinctrl-names = "default"; 104 pinctrl-0 = <&pinctrl_usdhc1>; 105 cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; 106 wp-gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; 107 no-1-8-v; 108 status = "okay"; 109}; 110 111&usdhc2 { 112 pinctrl-names = "default"; 113 pinctrl-0 = <&pinctrl_usdhc2>; 114 bus-width = <8>; 115 no-1-8-v; 116 non-removable; 117 status = "okay"; 118}; 119 120&iomuxc { 121 pinctrl_ecspi1: ecspi1grp { 122 fsl,pins = < 123 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 124 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 125 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 126 /* SS0# */ 127 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1 128 /* SS1# */ 129 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 130 /* SS2# */ 131 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 132 /* WP pin NOR Flash */ 133 MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0 134 /* Flash nReset */ 135 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0 136 >; 137 }; 138 139 pinctrl_ecspi4: ecspi4grp { 140 fsl,pins = < 141 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 142 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 143 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 144 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ 145 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ 146 >; 147 }; 148 149 pinctrl_gpio: gpiogrp { 150 fsl,pins = < 151 /* led enable */ 152 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 153 /* LCD power enable */ 154 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0 155 /* led yellow */ 156 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0 157 /* led red */ 158 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x4001b0b0 159 /* led green */ 160 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0 161 /* led blue */ 162 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0 163 /* Profibus IRQ */ 164 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 165 /* FPGA IRQ currently unused*/ 166 MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 167 /* Display reset because of clock failure */ 168 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0 169 /* spi bus #2 SS driver enable */ 170 MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 171 /* RST_LOC# PHY reset input (has pull-down!)*/ 172 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0 173 /* Touchscreen IRQ */ 174 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 175 /* PCIe reset */ 176 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0 177 /* make sure pin is GPIO and not ENET_REF_CLK */ 178 MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001a0b0 179 /* TPM PP */ 180 MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x4001b0b0 181 /* TPM Reset */ 182 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0 183 /* eMMC Reset# */ 184 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0 185 >; 186 }; 187 188 pinctrl_flexcan1: flexcan1grp { 189 fsl,pins = < 190 MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0 191 MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0 192 >; 193 }; 194 195 pinctrl_flexcan2: flexcan2grp { 196 fsl,pins = < 197 MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 198 MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 199 >; 200 }; 201 202 pinctrl_usbotg: usbotggrp { 203 fsl,pins = < 204 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 205 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 206 >; 207 }; 208 209 pinctrl_usdhc1: usdhc1grp { 210 fsl,pins = < 211 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 212 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 213 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 214 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 215 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 216 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 217 /* SD1 card detect input */ 218 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 219 /* SD1 write protect input */ 220 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 221 >; 222 }; 223 224 pinctrl_usdhc2: usdhc2grp { 225 fsl,pins = < 226 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 227 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 228 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 229 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 230 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 231 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 232 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 233 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 234 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 235 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 236 >; 237 }; 238}; 239