1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright 2019 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/input/linux-event-codes.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9 10/ { 11 /* these are used by bootloader for disabling nodes */ 12 aliases { 13 led0 = &led0; 14 led1 = &led1; 15 nand = &gpmi; 16 usb0 = &usbh1; 17 usb1 = &usbotg; 18 }; 19 20 chosen { 21 stdout-path = &uart2; 22 }; 23 24 gpio-keys { 25 compatible = "gpio-keys"; 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 user-pb { 30 label = "user_pb"; 31 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 32 linux,code = <BTN_0>; 33 }; 34 35 user-pb1x { 36 label = "user_pb1x"; 37 linux,code = <BTN_1>; 38 interrupt-parent = <&gsc>; 39 interrupts = <0>; 40 }; 41 42 key-erased { 43 label = "key-erased"; 44 linux,code = <BTN_2>; 45 interrupt-parent = <&gsc>; 46 interrupts = <1>; 47 }; 48 49 eeprom-wp { 50 label = "eeprom_wp"; 51 linux,code = <BTN_3>; 52 interrupt-parent = <&gsc>; 53 interrupts = <2>; 54 }; 55 56 tamper { 57 label = "tamper"; 58 linux,code = <BTN_4>; 59 interrupt-parent = <&gsc>; 60 interrupts = <5>; 61 }; 62 63 switch-hold { 64 label = "switch_hold"; 65 linux,code = <BTN_5>; 66 interrupt-parent = <&gsc>; 67 interrupts = <7>; 68 }; 69 }; 70 71 leds { 72 compatible = "gpio-leds"; 73 pinctrl-names = "default"; 74 pinctrl-0 = <&pinctrl_gpio_leds>; 75 76 led0: user1 { 77 label = "user1"; 78 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 79 default-state = "on"; 80 linux,default-trigger = "heartbeat"; 81 }; 82 83 led1: user2 { 84 label = "user2"; 85 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 86 default-state = "off"; 87 }; 88 }; 89 90 memory@10000000 { 91 device_type = "memory"; 92 reg = <0x10000000 0x20000000>; 93 }; 94 95 pps { 96 compatible = "pps-gpio"; 97 pinctrl-names = "default"; 98 pinctrl-0 = <&pinctrl_pps>; 99 gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; 100 status = "okay"; 101 }; 102 103 reg_3p3v: regulator-3p3v { 104 compatible = "regulator-fixed"; 105 regulator-name = "3P3V"; 106 regulator-min-microvolt = <3300000>; 107 regulator-max-microvolt = <3300000>; 108 regulator-always-on; 109 }; 110 111 reg_5p0v: regulator-5p0v { 112 compatible = "regulator-fixed"; 113 regulator-name = "5P0V"; 114 regulator-min-microvolt = <5000000>; 115 regulator-max-microvolt = <5000000>; 116 regulator-always-on; 117 }; 118}; 119 120&fec { 121 pinctrl-names = "default"; 122 pinctrl-0 = <&pinctrl_enet>; 123 phy-mode = "rgmii-id"; 124 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; 125 phy-reset-duration = <10>; 126 phy-reset-post-delay = <100>; 127 status = "okay"; 128}; 129 130&gpmi { 131 pinctrl-names = "default"; 132 pinctrl-0 = <&pinctrl_gpmi_nand>; 133 status = "okay"; 134}; 135 136&i2c1 { 137 clock-frequency = <100000>; 138 pinctrl-names = "default"; 139 pinctrl-0 = <&pinctrl_i2c1>; 140 status = "okay"; 141 142 gsc: gsc@20 { 143 compatible = "gw,gsc"; 144 reg = <0x20>; 145 interrupt-parent = <&gpio1>; 146 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 147 interrupt-controller; 148 #interrupt-cells = <1>; 149 #size-cells = <0>; 150 151 adc { 152 compatible = "gw,gsc-adc"; 153 #address-cells = <1>; 154 #size-cells = <0>; 155 156 channel@6 { 157 gw,mode = <0>; 158 reg = <0x06>; 159 label = "temp"; 160 }; 161 162 channel@8 { 163 gw,mode = <3>; 164 reg = <0x08>; 165 label = "vdd_bat"; 166 }; 167 168 channel@82 { 169 gw,mode = <2>; 170 reg = <0x82>; 171 label = "vdd_vin"; 172 gw,voltage-divider-ohms = <22100 1000>; 173 gw,voltage-offset-microvolt = <800000>; 174 }; 175 176 channel@84 { 177 gw,mode = <2>; 178 reg = <0x84>; 179 label = "vdd_5p0"; 180 gw,voltage-divider-ohms = <22100 10000>; 181 }; 182 183 channel@86 { 184 gw,mode = <2>; 185 reg = <0x86>; 186 label = "vdd_3p3"; 187 gw,voltage-divider-ohms = <10000 10000>; 188 }; 189 190 channel@88 { 191 gw,mode = <2>; 192 reg = <0x88>; 193 label = "vdd_2p5"; 194 gw,voltage-divider-ohms = <10000 10000>; 195 }; 196 197 channel@8c { 198 gw,mode = <2>; 199 reg = <0x8c>; 200 label = "vdd_arm"; 201 }; 202 203 channel@8e { 204 gw,mode = <2>; 205 reg = <0x8e>; 206 label = "vdd_soc"; 207 }; 208 209 channel@90 { 210 gw,mode = <2>; 211 reg = <0x90>; 212 label = "vdd_1p5"; 213 }; 214 215 channel@92 { 216 gw,mode = <2>; 217 reg = <0x92>; 218 label = "vdd_1p0"; 219 }; 220 221 channel@98 { 222 gw,mode = <2>; 223 reg = <0x98>; 224 label = "vdd_3p0"; 225 }; 226 227 channel@9a { 228 gw,mode = <2>; 229 reg = <0x9a>; 230 label = "vdd_an1"; 231 gw,voltage-divider-ohms = <10000 10000>; 232 }; 233 234 channel@a2 { 235 gw,mode = <2>; 236 reg = <0xa2>; 237 label = "vdd_gsc"; 238 gw,voltage-divider-ohms = <10000 10000>; 239 }; 240 }; 241 }; 242 243 gsc_gpio: gpio@23 { 244 compatible = "nxp,pca9555"; 245 reg = <0x23>; 246 gpio-controller; 247 #gpio-cells = <2>; 248 interrupt-parent = <&gsc>; 249 interrupts = <4>; 250 }; 251 252 eeprom@50 { 253 compatible = "atmel,24c02"; 254 reg = <0x50>; 255 pagesize = <16>; 256 }; 257 258 eeprom@51 { 259 compatible = "atmel,24c02"; 260 reg = <0x51>; 261 pagesize = <16>; 262 }; 263 264 eeprom@52 { 265 compatible = "atmel,24c02"; 266 reg = <0x52>; 267 pagesize = <16>; 268 }; 269 270 eeprom@53 { 271 compatible = "atmel,24c02"; 272 reg = <0x53>; 273 pagesize = <16>; 274 }; 275 276 rtc@68 { 277 compatible = "dallas,ds1672"; 278 reg = <0x68>; 279 }; 280}; 281 282&i2c2 { 283 clock-frequency = <100000>; 284 pinctrl-names = "default"; 285 pinctrl-0 = <&pinctrl_i2c2>; 286 status = "okay"; 287}; 288 289&i2c3 { 290 clock-frequency = <100000>; 291 pinctrl-names = "default"; 292 pinctrl-0 = <&pinctrl_i2c3>; 293 status = "okay"; 294}; 295 296&pcie { 297 pinctrl-names = "default"; 298 pinctrl-0 = <&pinctrl_pcie>; 299 reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; 300 status = "okay"; 301}; 302 303&pwm2 { 304 pinctrl-names = "default"; 305 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 306 status = "disabled"; 307}; 308 309&pwm3 { 310 pinctrl-names = "default"; 311 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 312 status = "disabled"; 313}; 314 315&pwm4 { 316 pinctrl-names = "default"; 317 pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ 318 status = "disabled"; 319}; 320 321&uart1 { 322 pinctrl-names = "default"; 323 pinctrl-0 = <&pinctrl_uart1>; 324 status = "okay"; 325}; 326 327&uart2 { 328 pinctrl-names = "default"; 329 pinctrl-0 = <&pinctrl_uart2>; 330 status = "okay"; 331}; 332 333&uart3 { 334 pinctrl-names = "default"; 335 pinctrl-0 = <&pinctrl_uart3>; 336 status = "okay"; 337}; 338 339&uart5 { 340 pinctrl-names = "default"; 341 pinctrl-0 = <&pinctrl_uart5>; 342 status = "okay"; 343}; 344 345&usbotg { 346 pinctrl-names = "default"; 347 pinctrl-0 = <&pinctrl_usbotg>; 348 disable-over-current; 349 dr_mode = "host"; 350 status = "okay"; 351}; 352 353&usbh1 { 354 status = "okay"; 355}; 356 357&wdog1 { 358 pinctrl-names = "default"; 359 pinctrl-0 = <&pinctrl_wdog>; 360 fsl,ext-reset-output; 361}; 362 363&iomuxc { 364 pinctrl_enet: enetgrp { 365 fsl,pins = < 366 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 367 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 368 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 369 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 370 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 371 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 372 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 373 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 374 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 375 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 376 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 377 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 378 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 379 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 380 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 381 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 382 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 383 >; 384 }; 385 386 pinctrl_gpio_leds: gpioledsgrp { 387 fsl,pins = < 388 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 389 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 390 >; 391 }; 392 393 pinctrl_gpmi_nand: gpminandgrp { 394 fsl,pins = < 395 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 396 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 397 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 398 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 399 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 400 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 401 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 402 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 403 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 404 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 405 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 406 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 407 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 408 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 409 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 410 >; 411 }; 412 413 pinctrl_i2c1: i2c1grp { 414 fsl,pins = < 415 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 416 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 417 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 418 >; 419 }; 420 421 pinctrl_i2c2: i2c2grp { 422 fsl,pins = < 423 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 424 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 425 >; 426 }; 427 428 pinctrl_i2c3: i2c3grp { 429 fsl,pins = < 430 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 431 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 432 >; 433 }; 434 435 pinctrl_pcie: pciegrp { 436 fsl,pins = < 437 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 438 >; 439 }; 440 441 pinctrl_pps: ppsgrp { 442 fsl,pins = < 443 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b1 444 >; 445 }; 446 447 pinctrl_pwm2: pwm2grp { 448 fsl,pins = < 449 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 450 >; 451 }; 452 453 pinctrl_pwm3: pwm3grp { 454 fsl,pins = < 455 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 456 >; 457 }; 458 459 pinctrl_pwm4: pwm4grp { 460 fsl,pins = < 461 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 462 >; 463 }; 464 465 pinctrl_uart1: uart1grp { 466 fsl,pins = < 467 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 468 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 469 >; 470 }; 471 472 pinctrl_uart2: uart2grp { 473 fsl,pins = < 474 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 475 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 476 >; 477 }; 478 479 pinctrl_uart3: uart3grp { 480 fsl,pins = < 481 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 482 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 483 >; 484 }; 485 486 pinctrl_uart5: uart5grp { 487 fsl,pins = < 488 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 489 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 490 >; 491 }; 492 493 pinctrl_usbotg: usbotggrp { 494 fsl,pins = < 495 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 496 >; 497 }; 498 499 pinctrl_wdog: wdoggrp { 500 fsl,pins = < 501 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 502 >; 503 }; 504}; 505