1/* 2 * Copyright (C) 2013,2014 Russell King 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * version 2 as published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * Or, alternatively, 19 * 20 * b) Permission is hereby granted, free of charge, to any person 21 * obtaining a copy of this software and associated documentation 22 * files (the "Software"), to deal in the Software without 23 * restriction, including without limitation the rights to use, 24 * copy, modify, merge, publish, distribute, sublicense, and/or 25 * sell copies of the Software, and to permit persons to whom the 26 * Software is furnished to do so, subject to the following 27 * conditions: 28 * 29 * The above copyright notice and this permission notice shall be 30 * included in all copies or substantial portions of the Software. 31 * 32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 39 * OTHER DEALINGS IN THE SOFTWARE. 40 */ 41#include <dt-bindings/gpio/gpio.h> 42 43/ { 44 vcc_3v3: regulator-vcc-3v3 { 45 compatible = "regulator-fixed"; 46 regulator-always-on; 47 regulator-name = "vcc_3v3"; 48 regulator-min-microvolt = <3300000>; 49 regulator-max-microvolt = <3300000>; 50 }; 51}; 52 53&fec { 54 pinctrl-names = "default"; 55 pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; 56 phy-handle = <&phy>; 57 phy-mode = "rgmii-id"; 58 phy-reset-duration = <2>; 59 phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; 60 status = "okay"; 61 62 mdio { 63 #address-cells = <1>; 64 #size-cells = <0>; 65 66 phy: ethernet-phy@0 { 67 reg = <0>; 68 qca,clk-out-frequency = <125000000>; 69 }; 70 }; 71}; 72 73&iomuxc { 74 microsom { 75 pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 { 76 fsl,pins = < 77 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 78 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 79 /* AR8035 reset */ 80 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0 81 /* AR8035 interrupt */ 82 MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 83 /* GPIO16 -> AR8035 25MHz */ 84 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0 85 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x13030 86 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 87 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 88 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 89 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 90 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 91 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ 92 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 93 /* AR8035 pin strapping: IO voltage: pull up */ 94 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 95 /* AR8035 pin strapping: PHYADDR#0: pull down */ 96 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 97 /* AR8035 pin strapping: PHYADDR#1: pull down */ 98 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 99 /* AR8035 pin strapping: MODE#1: pull up */ 100 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 101 /* AR8035 pin strapping: MODE#3: pull up */ 102 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 103 /* AR8035 pin strapping: MODE#0: pull down */ 104 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 105 106 /* 107 * As the RMII pins are also connected to RGMII 108 * so that an AR8030 can be placed, set these 109 * to high-z with the same pulls as above. 110 * Use the GPIO settings to avoid changing the 111 * input select registers. 112 */ 113 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x03000 114 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x03000 115 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x03000 116 >; 117 }; 118 119 pinctrl_microsom_uart1: microsom-uart1 { 120 fsl,pins = < 121 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 122 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 123 >; 124 }; 125 }; 126}; 127 128&uart1 { 129 pinctrl-names = "default"; 130 pinctrl-0 = <&pinctrl_microsom_uart1>; 131 status = "okay"; 132}; 133