1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2//
3// Copyright 2017 NXP
4
5/dts-v1/;
6
7#include "imx7d.dtsi"
8#include "imx7d-pico-u-boot.dtsi"
9
10/ {
11	/* Will be filled by the bootloader */
12	memory@80000000 {
13		device_type = "memory";
14		reg = <0x80000000 0>;
15	};
16
17	reg_wlreg_on: regulator-wlreg_on {
18		compatible = "regulator-fixed";
19		pinctrl-names = "default";
20		pinctrl-0 = <&pinctrl_reg_wlreg_on>;
21		regulator-name = "wlreg_on";
22		regulator-min-microvolt = <3300000>;
23		regulator-max-microvolt = <3300000>;
24		gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
25		enable-active-high;
26	};
27
28	reg_2p5v: regulator-2p5v {
29		compatible = "regulator-fixed";
30		regulator-name = "2P5V";
31		regulator-min-microvolt = <2500000>;
32		regulator-max-microvolt = <2500000>;
33		regulator-always-on;
34	};
35
36	reg_3p3v: regulator-3p3v {
37		compatible = "regulator-fixed";
38		regulator-name = "3P3V";
39		regulator-min-microvolt = <3300000>;
40		regulator-max-microvolt = <3300000>;
41		regulator-always-on;
42	};
43
44	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
45		pinctrl-names = "default";
46		pinctrl-0 = <&pinctrl_usbotg1_pwr>;
47		compatible = "regulator-fixed";
48		regulator-name = "usb_otg1_vbus";
49		regulator-min-microvolt = <5000000>;
50		regulator-max-microvolt = <5000000>;
51		gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
52	};
53
54	reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
55		compatible = "regulator-fixed";
56		regulator-name = "usb_otg2_vbus";
57		regulator-min-microvolt = <5000000>;
58		regulator-max-microvolt = <5000000>;
59	};
60
61	reg_vref_1v8: regulator-vref-1v8 {
62		compatible = "regulator-fixed";
63		regulator-name = "vref-1v8";
64		regulator-min-microvolt = <1800000>;
65		regulator-max-microvolt = <1800000>;
66	};
67
68	usdhc2_pwrseq: usdhc2_pwrseq {
69		compatible = "mmc-pwrseq-simple";
70		clocks = <&clks IMX7D_CLKO2_ROOT_DIV>;
71		clock-names = "ext_clock";
72	};
73};
74
75&clks {
76	assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
77			  <&clks IMX7D_CLKO2_ROOT_DIV>;
78	assigned-clock-parents = <&clks IMX7D_CKIL>;
79	assigned-clock-rates = <0>, <32768>;
80};
81
82&ecspi3 {
83	cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
84	pinctrl-names = "default";
85	pinctrl-0 = <&pinctrl_ecspi3>;
86	status = "okay";
87};
88
89&fec1 {
90	pinctrl-names = "default";
91	pinctrl-0 = <&pinctrl_enet1>;
92	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
93			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
94	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
95	assigned-clock-rates = <0>, <100000000>;
96	phy-mode = "rgmii-id";
97	phy-handle = <&ethphy0>;
98	fsl,magic-packet;
99	phy-reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
100	status = "okay";
101
102	mdio {
103		#address-cells = <1>;
104		#size-cells = <0>;
105
106		ethphy0: ethernet-phy@1 {
107			compatible = "ethernet-phy-ieee802.3-c22";
108			reg = <1>;
109			status = "okay";
110		};
111	};
112};
113
114&flexcan1 {
115	pinctrl-names = "default";
116	pinctrl-0 = <&pinctrl_can1>;
117	status = "okay";
118};
119
120&flexcan2 {
121	pinctrl-names = "default";
122	pinctrl-0 = <&pinctrl_can2>;
123	status = "okay";
124};
125
126&i2c1 {
127	clock-frequency = <100000>;
128	pinctrl-names = "default";
129	pinctrl-0 = <&pinctrl_i2c1>;
130	status = "okay";
131};
132
133&i2c2 {
134	pinctrl-names = "default";
135	pinctrl-0 = <&pinctrl_i2c2>;
136	status = "okay";
137};
138
139&i2c4 {
140	pinctrl-names = "default";
141	pinctrl-0 = <&pinctrl_i2c4>;
142	status = "okay";
143
144	pmic: pfuze3000@8 {
145		compatible = "fsl,pfuze3000";
146		reg = <0x08>;
147
148		regulators {
149			sw1a_reg: sw1a {
150				regulator-min-microvolt = <700000>;
151				regulator-max-microvolt = <3300000>;
152				regulator-boot-on;
153				regulator-always-on;
154				regulator-ramp-delay = <6250>;
155			};
156			/* use sw1c_reg to align with pfuze100/pfuze200 */
157			sw1c_reg: sw1b {
158				regulator-min-microvolt = <700000>;
159				regulator-max-microvolt = <1475000>;
160				regulator-boot-on;
161				regulator-always-on;
162				regulator-ramp-delay = <6250>;
163			};
164
165			sw2_reg: sw2 {
166				regulator-min-microvolt = <1800000>;
167				regulator-max-microvolt = <1850000>;
168				regulator-boot-on;
169				regulator-always-on;
170			};
171
172			sw3a_reg: sw3 {
173				regulator-min-microvolt = <900000>;
174				regulator-max-microvolt = <1650000>;
175				regulator-boot-on;
176				regulator-always-on;
177			};
178
179			swbst_reg: swbst {
180				regulator-min-microvolt = <5000000>;
181				regulator-max-microvolt = <5150000>;
182			};
183
184			snvs_reg: vsnvs {
185				regulator-min-microvolt = <1000000>;
186				regulator-max-microvolt = <3000000>;
187				regulator-boot-on;
188				regulator-always-on;
189			};
190
191			vref_reg: vrefddr {
192				regulator-boot-on;
193				regulator-always-on;
194			};
195
196			vgen1_reg: vldo1 {
197				regulator-min-microvolt = <1800000>;
198				regulator-max-microvolt = <3300000>;
199				regulator-always-on;
200			};
201
202			vgen2_reg: vldo2 {
203				regulator-min-microvolt = <800000>;
204				regulator-max-microvolt = <1550000>;
205			};
206
207			vgen3_reg: vccsd {
208				regulator-min-microvolt = <2850000>;
209				regulator-max-microvolt = <3300000>;
210				regulator-always-on;
211			};
212
213			vgen4_reg: v33 {
214				regulator-min-microvolt = <2850000>;
215				regulator-max-microvolt = <3300000>;
216				regulator-always-on;
217			};
218
219			vgen5_reg: vldo3 {
220				regulator-min-microvolt = <1800000>;
221				regulator-max-microvolt = <3300000>;
222				regulator-always-on;
223			};
224
225			vgen6_reg: vldo4 {
226				regulator-min-microvolt = <1800000>;
227				regulator-max-microvolt = <3300000>;
228				regulator-always-on;
229			};
230		};
231	};
232};
233
234&sai1 {
235	pinctrl-names = "default";
236	pinctrl-0 = <&pinctrl_sai1>;
237	assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
238			  <&clks IMX7D_SAI1_ROOT_CLK>;
239	assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
240	assigned-clock-rates = <0>, <24576000>;
241	status = "okay";
242};
243
244
245&pwm1 {
246	pinctrl-names = "default";
247	pinctrl-0 = <&pinctrl_pwm1>;
248	status = "okay";
249};
250
251&pwm2 {
252	pinctrl-names = "default";
253	pinctrl-0 = <&pinctrl_pwm2>;
254	status = "okay";
255};
256
257&pwm3 {
258	pinctrl-names = "default";
259	pinctrl-0 = <&pinctrl_pwm3>;
260	status = "okay";
261};
262
263&pwm4 { /* Backlight */
264	status = "okay";
265};
266
267&uart5 {
268	pinctrl-names = "default";
269	pinctrl-0 = <&pinctrl_uart5>;
270	assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
271	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
272	status = "okay";
273};
274
275&uart6 {
276	pinctrl-names = "default";
277	pinctrl-0 = <&pinctrl_uart6>;
278	assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
279	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
280	uart-has-rtscts;
281	status = "okay";
282};
283
284&uart7 { /* Bluetooth */
285	pinctrl-names = "default";
286	pinctrl-0 = <&pinctrl_uart7>;
287	assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
288	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
289	uart-has-rtscts;
290	status = "okay";
291};
292
293&usbotg1 {
294	vbus-supply = <&reg_usb_otg1_vbus>;
295	status = "okay";
296};
297
298&usbotg2 {
299	vbus-supply = <&reg_usb_otg2_vbus>;
300	dr_mode = "host";
301	status = "okay";
302};
303
304&usdhc1 {
305	pinctrl-names = "default", "state_100mhz", "state_200mhz";
306	pinctrl-0 = <&pinctrl_usdhc1>;
307	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
308	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
309	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
310	bus-width = <4>;
311	tuning-step = <2>;
312	vmmc-supply = <&reg_3p3v>;
313	wakeup-source;
314	no-1-8-v;
315	keep-power-in-suspend;
316	status = "okay";
317};
318
319&usdhc2 { /* Wifi SDIO */
320	pinctrl-names = "default";
321	pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi_clk>;
322	no-1-8-v;
323	non-removable;
324	keep-power-in-suspend;
325	wakeup-source;
326	vmmc-supply = <&reg_wlreg_on>;
327	mmc-pwrseq = <&usdhc2_pwrseq>;
328	status = "okay";
329};
330
331&usdhc3 {
332	pinctrl-names = "default", "state_100mhz", "state_200mhz";
333	pinctrl-0 = <&pinctrl_usdhc3>;
334	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
335	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
336	assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
337	assigned-clock-rates = <400000000>;
338	bus-width = <8>;
339	no-1-8-v;
340	fsl,tuning-step = <2>;
341	non-removable;
342	status = "okay";
343};
344
345&wdog1 {
346	pinctrl-names = "default";
347	pinctrl-0 = <&pinctrl_wdog>;
348	fsl,ext-reset-output;
349	status = "okay";
350};
351
352&iomuxc {
353	pinctrl_ecspi3: ecspi3grp {
354		fsl,pins = <
355			MX7D_PAD_I2C1_SCL__ECSPI3_MISO		0x2
356			MX7D_PAD_I2C1_SDA__ECSPI3_MOSI		0x2
357			MX7D_PAD_I2C2_SCL__ECSPI3_SCLK		0x2
358			MX7D_PAD_I2C2_SDA__GPIO4_IO11		0x14
359		>;
360	};
361
362	pinctrl_i2c1: i2c1grp {
363		fsl,pins = <
364			MX7D_PAD_UART1_TX_DATA__I2C1_SDA	0x4000007f
365			MX7D_PAD_UART1_RX_DATA__I2C1_SCL	0x4000007f
366		>;
367	};
368
369	pinctrl_i2c2: i2c2grp {
370		fsl,pins = <
371			MX7D_PAD_UART2_TX_DATA__I2C2_SDA	0x4000007f
372			MX7D_PAD_UART2_RX_DATA__I2C2_SCL	0x4000007f
373		>;
374	};
375
376	pinctrl_enet1: enet1grp {
377		fsl,pins = <
378			MX7D_PAD_SD2_CD_B__ENET1_MDIO			0x3
379			MX7D_PAD_SD2_WP__ENET1_MDC			0x3
380			MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC	0x1
381			MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0	0x1
382			MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1	0x1
383			MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2	0x1
384			MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3	0x1
385			MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x1
386			MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC	0x1
387			MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0	0x1
388			MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1	0x1
389			MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2	0x1
390			MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3	0x1
391			MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x1
392			MX7D_PAD_SD3_RESET_B__GPIO6_IO11                0x1  /* Ethernet reset */
393		>;
394	};
395
396	pinctrl_can1: can1frp {
397		fsl,pins = <
398			MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX	0x59
399			MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX	0x59
400		>;
401	};
402
403	pinctrl_can2: can2frp {
404		fsl,pins = <
405			MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX	0x59
406			MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX	0x59
407		>;
408	};
409
410	pinctrl_i2c4: i2c4grp {
411		fsl,pins = <
412			MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA		0x4000007f
413			MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL		0x4000007f
414		>;
415	};
416
417	pinctrl_pwm1: pwm1 {
418		fsl,pins = <
419			MX7D_PAD_GPIO1_IO08__PWM1_OUT   0x7f
420		>;
421	};
422
423	pinctrl_pwm2: pwm2 {
424		fsl,pins = <
425			MX7D_PAD_GPIO1_IO09__PWM2_OUT   0x7f
426		>;
427	};
428
429	pinctrl_pwm3: pwm3 {
430		fsl,pins = <
431			MX7D_PAD_GPIO1_IO10__PWM3_OUT   0x7f
432		>;
433	};
434
435	pinctrl_reg_wlreg_on: regregongrp {
436		fsl,pins = <
437			MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16	0x59
438		>;
439	};
440
441	pinctrl_sai1: sai1grp {
442		fsl,pins = <
443			MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK	0x1f
444			MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC	0x1f
445			MX7D_PAD_ENET1_COL__SAI1_TX_DATA0	0x30
446			MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0	0x1f
447		>;
448	};
449
450	pinctrl_uart5: uart5grp {
451		fsl,pins = <
452			MX7D_PAD_I2C4_SDA__UART5_DCE_TX		0x79
453			MX7D_PAD_I2C4_SCL__UART5_DCE_RX		0x79
454		>;
455	};
456
457	pinctrl_uart6: uart6grp {
458		fsl,pins = <
459			MX7D_PAD_EPDC_DATA08__UART6_DCE_RX	0x79
460			MX7D_PAD_EPDC_DATA09__UART6_DCE_TX	0x79
461			MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS	0x79
462			MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS	0x79
463		>;
464	};
465
466	pinctrl_uart7: uart7grp {
467		fsl,pins = <
468			MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX	0x79
469			MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX	0x79
470			MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS	0x79
471			MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS	0x79
472		>;
473	};
474
475	pinctrl_usbotg1_pwr: usbotg_pwr {
476		fsl,pins = <
477			MX7D_PAD_UART3_TX_DATA__GPIO4_IO5	0x14
478		>;
479	};
480
481	pinctrl_usdhc1: usdhc1grp {
482		fsl,pins = <
483			MX7D_PAD_SD1_CMD__SD1_CMD		0x59
484			MX7D_PAD_SD1_CLK__SD1_CLK		0x19
485			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x59
486			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x59
487			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x59
488			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x59
489			MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x15
490		>;
491	};
492
493	pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
494		fsl,pins = <
495			MX7D_PAD_SD1_CMD__SD1_CMD		0x5a
496			MX7D_PAD_SD1_CLK__SD1_CLK		0x1a
497			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5a
498			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5a
499			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5a
500			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5a
501			MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x15
502		>;
503	};
504
505	pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
506		fsl,pins = <
507			MX7D_PAD_SD1_CMD__SD1_CMD		0x5b
508			MX7D_PAD_SD1_CLK__SD1_CLK		0x1b
509			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5b
510			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5b
511			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5b
512			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5b
513			MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x15
514		>;
515	};
516
517	pinctrl_usdhc2: usdhc2grp {
518		fsl,pins = <
519			MX7D_PAD_SD2_CMD__SD2_CMD		0x59
520			MX7D_PAD_SD2_CLK__SD2_CLK		0x19
521			MX7D_PAD_SD2_DATA0__SD2_DATA0		0x59
522			MX7D_PAD_SD2_DATA1__SD2_DATA1		0x59
523			MX7D_PAD_SD2_DATA2__SD2_DATA2		0x59
524			MX7D_PAD_SD2_DATA3__SD2_DATA3		0x59
525		>;
526	};
527
528	pinctrl_usdhc3: usdhc3grp {
529		fsl,pins = <
530			MX7D_PAD_SD3_CMD__SD3_CMD		0x59
531			MX7D_PAD_SD3_CLK__SD3_CLK		0x19
532			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x59
533			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x59
534			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x59
535			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x59
536			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x59
537			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x59
538			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x59
539			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x59
540		>;
541	};
542
543	pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
544		fsl,pins = <
545			MX7D_PAD_SD3_CMD__SD3_CMD		0x5a
546			MX7D_PAD_SD3_CLK__SD3_CLK		0x1a
547			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5a
548			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5a
549			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5a
550			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5a
551			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5a
552			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5a
553			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5a
554			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5a
555		>;
556	};
557
558	pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
559		fsl,pins = <
560			MX7D_PAD_SD3_CMD__SD3_CMD		0x5b
561			MX7D_PAD_SD3_CLK__SD3_CLK		0x1b
562			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5b
563			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5b
564			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5b
565			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5b
566			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5b
567			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5b
568			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5b
569			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5b
570		>;
571	};
572};
573
574&iomuxc_lpsr {
575	pinctrl_wifi_clk: wificlkgrp {
576		fsl,pins = <
577			MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2	0x7d
578		>;
579	};
580
581	pinctrl_wdog: wdoggrp {
582		fsl,pins = <
583			MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B	0x74
584		>;
585	};
586};