1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2019 BayLibre, SAS 4 * Author: Fabien Parent <fparent@baylibre.com> 5 */ 6 7#include <dt-bindings/clock/mt8516-clk.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11 12/ { 13 compatible = "mediatek,mt8516"; 14 interrupt-parent = <&sysirq>; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 enable-method = "mediatek,mt8516-smp"; 22 23 cpu@0 { 24 device_type = "cpu"; 25 compatible = "arm,cortex-a35"; 26 reg = <0x0>; 27 clock-frequency = <1300000000>; 28 }; 29 30 cpu@1 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a35"; 33 reg = <0x1>; 34 clock-frequency = <1300000000>; 35 }; 36 37 cpu@2 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a35"; 40 reg = <0x2>; 41 clock-frequency = <1300000000>; 42 }; 43 44 cpu@3 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a35"; 47 reg = <0x3>; 48 clock-frequency = <1300000000>; 49 }; 50 }; 51 52 topckgen: clock-controller@10000000 { 53 compatible = "mediatek,mt8516-topckgen"; 54 reg = <0x10000000 0x1000>; 55 #clock-cells = <1>; 56 }; 57 58 topckgen_cg: clock-controller-cg@10000000 { 59 compatible = "mediatek,mt8516-topckgen-cg"; 60 reg = <0x10000000 0x1000>; 61 #clock-cells = <1>; 62 }; 63 64 infracfg: clock-controller@10001000 { 65 compatible = "mediatek,mt8516-infracfg"; 66 reg = <0x10001000 0x1000>; 67 #clock-cells = <1>; 68 }; 69 70 apmixedsys: clock-controller@10018000 { 71 compatible = "mediatek,mt8516-apmixedsys"; 72 reg = <0x10018000 0x710>; 73 #clock-cells = <1>; 74 }; 75 76 gic: interrupt-controller@10310000 { 77 compatible = "arm,gic-400"; 78 interrupt-controller; 79 #interrupt-cells = <3>; 80 interrupt-parent = <&gic>; 81 reg = <0x10310000 0x1000>, 82 <0x10320000 0x1000>, 83 <0x10340000 0x2000>, 84 <0x10360000 0x2000>; 85 interrupts = <GIC_PPI 9 86 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 87 }; 88 89 sysirq: interrupt-controller@10200620 { 90 compatible = "mediatek,sysirq"; 91 interrupt-controller; 92 #interrupt-cells = <3>; 93 interrupt-parent = <&gic>; 94 reg = <0x10200620 0x20>; 95 }; 96 97 watchdog: watchdog@10007000 { 98 compatible = "mediatek,wdt"; 99 reg = <0x10007000 0x1000>; 100 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_FALLING>; 101 #reset-cells = <1>; 102 status = "disabled"; 103 }; 104 105 pinctrl: pinctrl@10005000 { 106 compatible = "mediatek,mt8516-pinctrl"; 107 reg = <0x10005000 0x1000>; 108 109 gpio: gpio-controller { 110 gpio-controller; 111 #gpio-cells = <2>; 112 }; 113 }; 114 115 mmc0: mmc@11120000 { 116 compatible = "mediatek,mt8516-mmc"; 117 reg = <0x11120000 0x1000>; 118 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 119 clocks = <&topckgen_cg CLK_TOP_MSDC0>, 120 <&topckgen CLK_TOP_AHB_INFRA_SEL>, 121 <&topckgen_cg CLK_TOP_MSDC0_INFRA>; 122 clock-names = "source", "hclk", "source_cg"; 123 status = "disabled"; 124 }; 125 126 usb0: usb@11100000 { 127 compatible = "mediatek,mt8516-musb", 128 "mediatek,mt8518-musb"; 129 reg = <0x11100000 0x1000>; 130 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 131 interrupt-names = "mc"; 132 clocks = <&topckgen CLK_TOP_USB_PHY48M>, 133 <&topckgen_cg CLK_TOP_USBIF>, 134 <&topckgen_cg CLK_TOP_USB>, 135 <&topckgen_cg CLK_TOP_USB_1P>; 136 clock-names = "usbpll", "usbmcu", "usb", "icusb"; 137 status = "disabled"; 138 }; 139 140 uart0: serial@11005000 { 141 compatible = "mediatek,hsuart"; 142 reg = <0x11005000 0x1000>; 143 reg-shift = <2>; 144 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 145 clocks = <&topckgen CLK_TOP_UART0_SEL>, 146 <&topckgen_cg CLK_TOP_UART0>; 147 clock-names = "baud","bus"; 148 status = "disabled"; 149 }; 150}; 151