1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2019 Sartura Ltd.
4 *
5 * Author: Robert Marko <robert.marko@sartura.hr>
6 */
7
8 /dts-v1/;
9
10#include "skeleton.dtsi"
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
13#include <dt-bindings/clock/qcom,ipq4019-gcc.h>
14#include <dt-bindings/reset/qcom,ipq4019-reset.h>
15
16/ {
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	model = "Qualcomm Technologies, Inc. IPQ4019";
21	compatible = "qcom,ipq4019";
22
23	aliases {
24		serial0 = &blsp1_uart1;
25		spi0 = &blsp1_spi1;
26	};
27
28	reserved-memory {
29		#address-cells = <0x1>;
30		#size-cells = <0x1>;
31		ranges;
32
33		smem_mem: smem_region: smem@87e00000 {
34			reg = <0x87e00000 0x080000>;
35			no-map;
36		};
37
38		tz@87e80000 {
39			reg = <0x87e80000 0x180000>;
40			no-map;
41		};
42	};
43
44	smem {
45		compatible = "qcom,smem";
46		memory-region = <&smem_mem>;
47	};
48
49	soc: soc {
50		#address-cells = <1>;
51		#size-cells = <1>;
52		ranges;
53		compatible = "simple-bus";
54
55		gcc: clock-controller@1800000 {
56			compatible = "qcom,gcc-ipq4019";
57			reg = <0x1800000 0x60000>;
58			#clock-cells = <1>;
59			#reset-cells = <1>;
60			u-boot,dm-pre-reloc;
61		};
62
63		rng: rng@22000 {
64			compatible = "qcom,prng";
65			reg = <0x22000 0x140>;
66			clocks = <&gcc GCC_PRNG_AHB_CLK>;
67			status = "disabled";
68		};
69
70		reset: gcc-reset@1800000 {
71			compatible = "qcom,gcc-reset-ipq4019";
72			reg = <0x1800000 0x60000>;
73			#clock-cells = <1>;
74			#reset-cells = <1>;
75			u-boot,dm-pre-reloc;
76		};
77
78		pinctrl: qcom,tlmm@1000000 {
79			compatible = "qcom,tlmm-ipq4019";
80			reg = <0x1000000 0x300000>;
81			u-boot,dm-pre-reloc;
82		};
83
84		blsp1_uart1: serial@78af000 {
85			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
86			reg = <0x78af000 0x200>;
87			clock = <&gcc GCC_BLSP1_UART1_APPS_CLK>;
88			bit-rate = <0xFF>;
89			status = "disabled";
90			u-boot,dm-pre-reloc;
91		};
92
93		soc_gpios: pinctrl@1000000 {
94			compatible = "qcom,ipq4019-pinctrl";
95			reg = <0x1000000 0x300000>;
96			gpio-controller;
97			gpio-count = <100>;
98			gpio-bank-name="soc";
99			#gpio-cells = <2>;
100			u-boot,dm-pre-reloc;
101		};
102
103		blsp1_spi1: spi@78b5000 {
104			compatible = "qcom,spi-qup-v2.2.1";
105			reg = <0x78b5000 0x600>;
106			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
107			#address-cells = <1>;
108			#size-cells = <0>;
109			status = "disabled";
110			u-boot,dm-pre-reloc;
111		};
112
113		mdio: mdio@90000 {
114			#address-cells = <1>;
115			#size-cells = <0>;
116			compatible = "qcom,ipq4019-mdio";
117			reg = <0x90000 0x64>;
118			status = "disabled";
119
120			ethphy0: ethernet-phy@0 {
121				reg = <0>;
122			};
123
124			ethphy1: ethernet-phy@1 {
125				reg = <1>;
126			};
127
128			ethphy2: ethernet-phy@2 {
129				reg = <2>;
130			};
131
132			ethphy3: ethernet-phy@3 {
133				reg = <3>;
134			};
135
136			ethphy4: ethernet-phy@4 {
137				reg = <4>;
138			};
139		};
140
141		usb3_ss_phy: ssphy@9a000 {
142			compatible = "qcom,usb-ss-ipq4019-phy";
143			#phy-cells = <0>;
144			reg = <0x9a000 0x800>;
145			reg-names = "phy_base";
146			resets = <&reset USB3_UNIPHY_PHY_ARES>;
147			reset-names = "por_rst";
148			status = "disabled";
149		};
150
151		usb3_hs_phy: hsphy@a6000 {
152			compatible = "qcom,usb-hs-ipq4019-phy";
153			#phy-cells = <0>;
154			reg = <0xa6000 0x40>;
155			reg-names = "phy_base";
156			resets = <&reset USB3_HSPHY_POR_ARES>, <&reset USB3_HSPHY_S_ARES>;
157			reset-names = "por_rst", "srif_rst";
158			status = "disabled";
159		};
160
161		usb3: usb3@8af8800 {
162			compatible = "qcom,dwc3";
163			reg = <0x8af8800 0x100>;
164			#address-cells = <1>;
165			#size-cells = <1>;
166			clocks = <&gcc GCC_USB3_MASTER_CLK>,
167				 <&gcc GCC_USB3_SLEEP_CLK>,
168				 <&gcc GCC_USB3_MOCK_UTMI_CLK>;
169			clock-names = "master", "sleep", "mock_utmi";
170			ranges;
171			status = "disabled";
172
173			dwc3@8a00000 {
174				compatible = "snps,dwc3";
175				reg = <0x8a00000 0xf8000>;
176				phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
177				phy-names = "usb2-phy", "usb3-phy";
178				dr_mode = "host";
179				maximum-speed = "super-speed";
180				snps,dis_u2_susphy_quirk;
181			};
182		};
183
184		usb2_hs_phy: hsphy@a8000 {
185			compatible = "qcom,usb-hs-ipq4019-phy";
186			#phy-cells = <0>;
187			reg = <0xa8000 0x40>;
188			reg-names = "phy_base";
189			resets = <&reset USB2_HSPHY_POR_ARES>, <&reset USB2_HSPHY_S_ARES>;
190			reset-names = "por_rst", "srif_rst";
191			status = "disabled";
192		};
193
194		usb2: usb2@60f8800 {
195			compatible = "qcom,dwc3";
196			reg = <0x60f8800 0x100>;
197			#address-cells = <1>;
198			#size-cells = <1>;
199			clocks = <&gcc GCC_USB2_MASTER_CLK>,
200				 <&gcc GCC_USB2_SLEEP_CLK>,
201				 <&gcc GCC_USB2_MOCK_UTMI_CLK>;
202			clock-names = "master", "sleep", "mock_utmi";
203			ranges;
204			status = "disabled";
205
206			dwc3@6000000 {
207				compatible = "snps,dwc3";
208				reg = <0x6000000 0xf8000>;
209				phys = <&usb2_hs_phy>;
210				phy-names = "usb2-phy";
211				dr_mode = "host";
212				maximum-speed = "high-speed";
213				snps,dis_u2_susphy_quirk;
214			};
215		};
216	};
217};
218