1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Device Tree Source for UniPhier PXs2 SoC
4//
5// Copyright (C) 2015-2016 Socionext Inc.
6//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7
8#include <dt-bindings/gpio/uniphier-gpio.h>
9#include <dt-bindings/thermal/thermal.h>
10
11/ {
12	compatible = "socionext,uniphier-pxs2";
13	#address-cells = <1>;
14	#size-cells = <1>;
15
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19
20		cpu0: cpu@0 {
21			device_type = "cpu";
22			compatible = "arm,cortex-a9";
23			reg = <0>;
24			clocks = <&sys_clk 32>;
25			enable-method = "psci";
26			next-level-cache = <&l2>;
27			operating-points-v2 = <&cpu_opp>;
28			#cooling-cells = <2>;
29		};
30
31		cpu1: cpu@1 {
32			device_type = "cpu";
33			compatible = "arm,cortex-a9";
34			reg = <1>;
35			clocks = <&sys_clk 32>;
36			enable-method = "psci";
37			next-level-cache = <&l2>;
38			operating-points-v2 = <&cpu_opp>;
39			#cooling-cells = <2>;
40		};
41
42		cpu2: cpu@2 {
43			device_type = "cpu";
44			compatible = "arm,cortex-a9";
45			reg = <2>;
46			clocks = <&sys_clk 32>;
47			enable-method = "psci";
48			next-level-cache = <&l2>;
49			operating-points-v2 = <&cpu_opp>;
50			#cooling-cells = <2>;
51		};
52
53		cpu3: cpu@3 {
54			device_type = "cpu";
55			compatible = "arm,cortex-a9";
56			reg = <3>;
57			clocks = <&sys_clk 32>;
58			enable-method = "psci";
59			next-level-cache = <&l2>;
60			operating-points-v2 = <&cpu_opp>;
61			#cooling-cells = <2>;
62		};
63	};
64
65	cpu_opp: opp-table {
66		compatible = "operating-points-v2";
67		opp-shared;
68
69		opp-100000000 {
70			opp-hz = /bits/ 64 <100000000>;
71			clock-latency-ns = <300>;
72		};
73		opp-150000000 {
74			opp-hz = /bits/ 64 <150000000>;
75			clock-latency-ns = <300>;
76		};
77		opp-200000000 {
78			opp-hz = /bits/ 64 <200000000>;
79			clock-latency-ns = <300>;
80		};
81		opp-300000000 {
82			opp-hz = /bits/ 64 <300000000>;
83			clock-latency-ns = <300>;
84		};
85		opp-400000000 {
86			opp-hz = /bits/ 64 <400000000>;
87			clock-latency-ns = <300>;
88		};
89		opp-600000000 {
90			opp-hz = /bits/ 64 <600000000>;
91			clock-latency-ns = <300>;
92		};
93		opp-800000000 {
94			opp-hz = /bits/ 64 <800000000>;
95			clock-latency-ns = <300>;
96		};
97		opp-1200000000 {
98			opp-hz = /bits/ 64 <1200000000>;
99			clock-latency-ns = <300>;
100		};
101	};
102
103	psci {
104		compatible = "arm,psci-0.2";
105		method = "smc";
106	};
107
108	clocks {
109		refclk: ref {
110			compatible = "fixed-clock";
111			#clock-cells = <0>;
112			clock-frequency = <25000000>;
113		};
114
115		arm_timer_clk: arm-timer {
116			#clock-cells = <0>;
117			compatible = "fixed-clock";
118			clock-frequency = <50000000>;
119		};
120	};
121
122	thermal-zones {
123		cpu-thermal {
124			polling-delay-passive = <250>;	/* 250ms */
125			polling-delay = <1000>;		/* 1000ms */
126			thermal-sensors = <&pvtctl>;
127
128			trips {
129				cpu_crit: cpu-crit {
130					temperature = <95000>;	/* 95C */
131					hysteresis = <2000>;
132					type = "critical";
133				};
134				cpu_alert: cpu-alert {
135					temperature = <85000>;	/* 85C */
136					hysteresis = <2000>;
137					type = "passive";
138				};
139			};
140
141			cooling-maps {
142				map {
143					trip = <&cpu_alert>;
144					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
145							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
146							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
147							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
148				};
149			};
150		};
151	};
152
153	soc {
154		compatible = "simple-bus";
155		#address-cells = <1>;
156		#size-cells = <1>;
157		ranges;
158		interrupt-parent = <&intc>;
159
160		l2: cache-controller@500c0000 {
161			compatible = "socionext,uniphier-system-cache";
162			reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
163			      <0x506c0000 0x400>;
164			interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
165			cache-unified;
166			cache-size = <(1280 * 1024)>;
167			cache-sets = <512>;
168			cache-line-size = <128>;
169			cache-level = <2>;
170		};
171
172		spi0: spi@54006000 {
173			compatible = "socionext,uniphier-scssi";
174			status = "disabled";
175			reg = <0x54006000 0x100>;
176			#address-cells = <1>;
177			#size-cells = <0>;
178			interrupts = <0 39 4>;
179			pinctrl-names = "default";
180			pinctrl-0 = <&pinctrl_spi0>;
181			clocks = <&peri_clk 11>;
182			resets = <&peri_rst 11>;
183		};
184
185		spi1: spi@54006100 {
186			compatible = "socionext,uniphier-scssi";
187			status = "disabled";
188			reg = <0x54006100 0x100>;
189			#address-cells = <1>;
190			#size-cells = <0>;
191			interrupts = <0 216 4>;
192			pinctrl-names = "default";
193			pinctrl-0 = <&pinctrl_spi1>;
194			clocks = <&peri_clk 12>;
195			resets = <&peri_rst 12>;
196		};
197
198		serial0: serial@54006800 {
199			compatible = "socionext,uniphier-uart";
200			status = "disabled";
201			reg = <0x54006800 0x40>;
202			interrupts = <0 33 4>;
203			pinctrl-names = "default";
204			pinctrl-0 = <&pinctrl_uart0>;
205			clocks = <&peri_clk 0>;
206			resets = <&peri_rst 0>;
207		};
208
209		serial1: serial@54006900 {
210			compatible = "socionext,uniphier-uart";
211			status = "disabled";
212			reg = <0x54006900 0x40>;
213			interrupts = <0 35 4>;
214			pinctrl-names = "default";
215			pinctrl-0 = <&pinctrl_uart1>;
216			clocks = <&peri_clk 1>;
217			resets = <&peri_rst 1>;
218		};
219
220		serial2: serial@54006a00 {
221			compatible = "socionext,uniphier-uart";
222			status = "disabled";
223			reg = <0x54006a00 0x40>;
224			interrupts = <0 37 4>;
225			pinctrl-names = "default";
226			pinctrl-0 = <&pinctrl_uart2>;
227			clocks = <&peri_clk 2>;
228			resets = <&peri_rst 2>;
229		};
230
231		serial3: serial@54006b00 {
232			compatible = "socionext,uniphier-uart";
233			status = "disabled";
234			reg = <0x54006b00 0x40>;
235			interrupts = <0 177 4>;
236			pinctrl-names = "default";
237			pinctrl-0 = <&pinctrl_uart3>;
238			clocks = <&peri_clk 3>;
239			resets = <&peri_rst 3>;
240		};
241
242		gpio: gpio@55000000 {
243			compatible = "socionext,uniphier-gpio";
244			reg = <0x55000000 0x200>;
245			interrupt-parent = <&aidet>;
246			interrupt-controller;
247			#interrupt-cells = <2>;
248			gpio-controller;
249			#gpio-cells = <2>;
250			gpio-ranges = <&pinctrl 0 0 0>,
251				      <&pinctrl 96 0 0>;
252			gpio-ranges-group-names = "gpio_range0",
253						  "gpio_range1";
254			ngpios = <232>;
255			socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
256						     <21 217 3>;
257		};
258
259		audio@56000000 {
260			compatible = "socionext,uniphier-pxs2-aio";
261			reg = <0x56000000 0x80000>;
262			interrupts = <0 144 4>;
263			pinctrl-names = "default";
264			pinctrl-0 = <&pinctrl_ain1>,
265				    <&pinctrl_ain2>,
266				    <&pinctrl_ainiec1>,
267				    <&pinctrl_aout2>,
268				    <&pinctrl_aout3>,
269				    <&pinctrl_aoutiec1>,
270				    <&pinctrl_aoutiec2>;
271			clock-names = "aio";
272			clocks = <&sys_clk 40>;
273			reset-names = "aio";
274			resets = <&sys_rst 40>;
275			#sound-dai-cells = <1>;
276			socionext,syscon = <&soc_glue>;
277
278			i2s_port0: port@0 {
279				i2s_hdmi: endpoint {
280				};
281			};
282
283			i2s_port1: port@1 {
284				i2s_line: endpoint {
285				};
286			};
287
288			i2s_port2: port@2 {
289				i2s_aux: endpoint {
290				};
291			};
292
293			spdif_port0: port@3 {
294				spdif_hiecout1: endpoint {
295				};
296			};
297
298			spdif_port1: port@4 {
299				spdif_iecout1: endpoint {
300				};
301			};
302
303			comp_spdif_port0: port@5 {
304				comp_spdif_hiecout1: endpoint {
305				};
306			};
307
308			comp_spdif_port1: port@6 {
309				comp_spdif_iecout1: endpoint {
310				};
311			};
312		};
313
314		i2c0: i2c@58780000 {
315			compatible = "socionext,uniphier-fi2c";
316			status = "disabled";
317			reg = <0x58780000 0x80>;
318			#address-cells = <1>;
319			#size-cells = <0>;
320			interrupts = <0 41 4>;
321			pinctrl-names = "default";
322			pinctrl-0 = <&pinctrl_i2c0>;
323			clocks = <&peri_clk 4>;
324			resets = <&peri_rst 4>;
325			clock-frequency = <100000>;
326		};
327
328		i2c1: i2c@58781000 {
329			compatible = "socionext,uniphier-fi2c";
330			status = "disabled";
331			reg = <0x58781000 0x80>;
332			#address-cells = <1>;
333			#size-cells = <0>;
334			interrupts = <0 42 4>;
335			pinctrl-names = "default";
336			pinctrl-0 = <&pinctrl_i2c1>;
337			clocks = <&peri_clk 5>;
338			resets = <&peri_rst 5>;
339			clock-frequency = <100000>;
340		};
341
342		i2c2: i2c@58782000 {
343			compatible = "socionext,uniphier-fi2c";
344			status = "disabled";
345			reg = <0x58782000 0x80>;
346			#address-cells = <1>;
347			#size-cells = <0>;
348			interrupts = <0 43 4>;
349			pinctrl-names = "default";
350			pinctrl-0 = <&pinctrl_i2c2>;
351			clocks = <&peri_clk 6>;
352			resets = <&peri_rst 6>;
353			clock-frequency = <100000>;
354		};
355
356		i2c3: i2c@58783000 {
357			compatible = "socionext,uniphier-fi2c";
358			status = "disabled";
359			reg = <0x58783000 0x80>;
360			#address-cells = <1>;
361			#size-cells = <0>;
362			interrupts = <0 44 4>;
363			pinctrl-names = "default";
364			pinctrl-0 = <&pinctrl_i2c3>;
365			clocks = <&peri_clk 7>;
366			resets = <&peri_rst 7>;
367			clock-frequency = <100000>;
368		};
369
370		/* chip-internal connection for DMD */
371		i2c4: i2c@58784000 {
372			compatible = "socionext,uniphier-fi2c";
373			reg = <0x58784000 0x80>;
374			#address-cells = <1>;
375			#size-cells = <0>;
376			interrupts = <0 45 4>;
377			clocks = <&peri_clk 8>;
378			resets = <&peri_rst 8>;
379			clock-frequency = <400000>;
380		};
381
382		/* chip-internal connection for STM */
383		i2c5: i2c@58785000 {
384			compatible = "socionext,uniphier-fi2c";
385			reg = <0x58785000 0x80>;
386			#address-cells = <1>;
387			#size-cells = <0>;
388			interrupts = <0 25 4>;
389			clocks = <&peri_clk 9>;
390			resets = <&peri_rst 9>;
391			clock-frequency = <400000>;
392		};
393
394		/* chip-internal connection for HDMI */
395		i2c6: i2c@58786000 {
396			compatible = "socionext,uniphier-fi2c";
397			reg = <0x58786000 0x80>;
398			#address-cells = <1>;
399			#size-cells = <0>;
400			interrupts = <0 26 4>;
401			clocks = <&peri_clk 10>;
402			resets = <&peri_rst 10>;
403			clock-frequency = <400000>;
404		};
405
406		system_bus: system-bus@58c00000 {
407			compatible = "socionext,uniphier-system-bus";
408			status = "disabled";
409			reg = <0x58c00000 0x400>;
410			#address-cells = <2>;
411			#size-cells = <1>;
412			pinctrl-names = "default";
413			pinctrl-0 = <&pinctrl_system_bus>;
414		};
415
416		smpctrl@59801000 {
417			compatible = "socionext,uniphier-smpctrl";
418			reg = <0x59801000 0x400>;
419		};
420
421		sdctrl@59810000 {
422			compatible = "socionext,uniphier-pxs2-sdctrl",
423				     "simple-mfd", "syscon";
424			reg = <0x59810000 0x400>;
425
426			sd_clk: clock {
427				compatible = "socionext,uniphier-pxs2-sd-clock";
428				#clock-cells = <1>;
429			};
430
431			sd_rst: reset {
432				compatible = "socionext,uniphier-pxs2-sd-reset";
433				#reset-cells = <1>;
434			};
435		};
436
437		perictrl@59820000 {
438			compatible = "socionext,uniphier-pxs2-perictrl",
439				     "simple-mfd", "syscon";
440			reg = <0x59820000 0x200>;
441
442			peri_clk: clock {
443				compatible = "socionext,uniphier-pxs2-peri-clock";
444				#clock-cells = <1>;
445			};
446
447			peri_rst: reset {
448				compatible = "socionext,uniphier-pxs2-peri-reset";
449				#reset-cells = <1>;
450			};
451		};
452
453		emmc: mmc@5a000000 {
454			compatible = "socionext,uniphier-sd-v3.1.1";
455			status = "disabled";
456			reg = <0x5a000000 0x800>;
457			interrupts = <0 78 4>;
458			pinctrl-names = "default";
459			pinctrl-0 = <&pinctrl_emmc>;
460			clocks = <&sd_clk 1>;
461			reset-names = "host", "hw";
462			resets = <&sd_rst 1>, <&sd_rst 6>;
463			bus-width = <8>;
464			cap-mmc-highspeed;
465			cap-mmc-hw-reset;
466			non-removable;
467		};
468
469		sd: mmc@5a400000 {
470			compatible = "socionext,uniphier-sd-v3.1.1";
471			status = "disabled";
472			reg = <0x5a400000 0x800>;
473			interrupts = <0 76 4>;
474			pinctrl-names = "default", "uhs";
475			pinctrl-0 = <&pinctrl_sd>;
476			pinctrl-1 = <&pinctrl_sd_uhs>;
477			clocks = <&sd_clk 0>;
478			reset-names = "host";
479			resets = <&sd_rst 0>;
480			bus-width = <4>;
481			cap-sd-highspeed;
482			sd-uhs-sdr12;
483			sd-uhs-sdr25;
484			sd-uhs-sdr50;
485		};
486
487		soc_glue: soc-glue@5f800000 {
488			compatible = "socionext,uniphier-pxs2-soc-glue",
489				     "simple-mfd", "syscon";
490			reg = <0x5f800000 0x2000>;
491
492			pinctrl: pinctrl {
493				compatible = "socionext,uniphier-pxs2-pinctrl";
494			};
495		};
496
497		soc-glue@5f900000 {
498			compatible = "socionext,uniphier-pxs2-soc-glue-debug",
499				     "simple-mfd";
500			#address-cells = <1>;
501			#size-cells = <1>;
502			ranges = <0 0x5f900000 0x2000>;
503
504			efuse@100 {
505				compatible = "socionext,uniphier-efuse";
506				reg = <0x100 0x28>;
507			};
508
509			efuse@200 {
510				compatible = "socionext,uniphier-efuse";
511				reg = <0x200 0x58>;
512			};
513		};
514
515		xdmac: dma-controller@5fc10000 {
516			compatible = "socionext,uniphier-xdmac";
517			reg = <0x5fc10000 0x5300>;
518			interrupts = <0 188 4>;
519			dma-channels = <16>;
520			#dma-cells = <2>;
521		};
522
523		aidet: interrupt-controller@5fc20000 {
524			compatible = "socionext,uniphier-pxs2-aidet";
525			reg = <0x5fc20000 0x200>;
526			interrupt-controller;
527			#interrupt-cells = <2>;
528		};
529
530		timer@60000200 {
531			compatible = "arm,cortex-a9-global-timer";
532			reg = <0x60000200 0x20>;
533			interrupts = <1 11 0xf04>;
534			clocks = <&arm_timer_clk>;
535		};
536
537		timer@60000600 {
538			compatible = "arm,cortex-a9-twd-timer";
539			reg = <0x60000600 0x20>;
540			interrupts = <1 13 0xf04>;
541			clocks = <&arm_timer_clk>;
542		};
543
544		intc: interrupt-controller@60001000 {
545			compatible = "arm,cortex-a9-gic";
546			reg = <0x60001000 0x1000>,
547			      <0x60000100 0x100>;
548			#interrupt-cells = <3>;
549			interrupt-controller;
550		};
551
552		sysctrl@61840000 {
553			compatible = "socionext,uniphier-pxs2-sysctrl",
554				     "simple-mfd", "syscon";
555			reg = <0x61840000 0x10000>;
556
557			sys_clk: clock {
558				compatible = "socionext,uniphier-pxs2-clock";
559				#clock-cells = <1>;
560			};
561
562			sys_rst: reset {
563				compatible = "socionext,uniphier-pxs2-reset";
564				#reset-cells = <1>;
565			};
566
567			pvtctl: pvtctl {
568				compatible = "socionext,uniphier-pxs2-thermal";
569				interrupts = <0 3 4>;
570				#thermal-sensor-cells = <0>;
571				socionext,tmod-calibration = <0x0f86 0x6844>;
572			};
573		};
574
575		eth: ethernet@65000000 {
576			compatible = "socionext,uniphier-pxs2-ave4";
577			status = "disabled";
578			reg = <0x65000000 0x8500>;
579			interrupts = <0 66 4>;
580			pinctrl-names = "default";
581			pinctrl-0 = <&pinctrl_ether_rgmii>;
582			clock-names = "ether";
583			clocks = <&sys_clk 6>;
584			reset-names = "ether";
585			resets = <&sys_rst 6>;
586			phy-mode = "rgmii";
587			local-mac-address = [00 00 00 00 00 00];
588			socionext,syscon-phy-mode = <&soc_glue 0>;
589
590			mdio: mdio {
591				#address-cells = <1>;
592				#size-cells = <0>;
593			};
594		};
595
596		_usb0: usb@65a00000 {
597			compatible = "socionext,uniphier-dwc3", "snps,dwc3";
598			status = "disabled";
599			reg = <0x65a00000 0xcd00>;
600			interrupt-names = "host", "peripheral";
601			interrupts = <0 134 4>, <0 135 4>;
602			pinctrl-names = "default";
603			pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
604			clock-names = "ref", "bus_early", "suspend";
605			clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
606			resets = <&usb0_rst 15>;
607			phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
608			       <&usb0_ssphy0>, <&usb0_ssphy1>;
609			dr_mode = "host";
610		};
611
612		usb-glue@65b00000 {
613			compatible = "socionext,uniphier-pxs2-dwc3-glue",
614				     "simple-mfd";
615			#address-cells = <1>;
616			#size-cells = <1>;
617			ranges = <0 0x65b00000 0x400>;
618
619			usb0_rst: reset@0 {
620				compatible = "socionext,uniphier-pxs2-usb3-reset";
621				reg = <0x0 0x4>;
622				#reset-cells = <1>;
623				clock-names = "link";
624				clocks = <&sys_clk 14>;
625				reset-names = "link";
626				resets = <&sys_rst 14>;
627			};
628
629			usb0_vbus0: regulator@100 {
630				compatible = "socionext,uniphier-pxs2-usb3-regulator";
631				reg = <0x100 0x10>;
632				clock-names = "link";
633				clocks = <&sys_clk 14>;
634				reset-names = "link";
635				resets = <&sys_rst 14>;
636			};
637
638			usb0_vbus1: regulator@110 {
639				compatible = "socionext,uniphier-pxs2-usb3-regulator";
640				reg = <0x110 0x10>;
641				clock-names = "link";
642				clocks = <&sys_clk 14>;
643				reset-names = "link";
644				resets = <&sys_rst 14>;
645			};
646
647			usb0_hsphy0: hs-phy@200 {
648				compatible = "socionext,uniphier-pxs2-usb3-hsphy";
649				reg = <0x200 0x10>;
650				#phy-cells = <0>;
651				clock-names = "link", "phy";
652				clocks = <&sys_clk 14>, <&sys_clk 16>;
653				reset-names = "link", "phy";
654				resets = <&sys_rst 14>, <&sys_rst 16>;
655				vbus-supply = <&usb0_vbus0>;
656			};
657
658			usb0_hsphy1: hs-phy@210 {
659				compatible = "socionext,uniphier-pxs2-usb3-hsphy";
660				reg = <0x210 0x10>;
661				#phy-cells = <0>;
662				clock-names = "link", "phy";
663				clocks = <&sys_clk 14>, <&sys_clk 16>;
664				reset-names = "link", "phy";
665				resets = <&sys_rst 14>, <&sys_rst 16>;
666				vbus-supply = <&usb0_vbus1>;
667			};
668
669			usb0_ssphy0: ss-phy@300 {
670				compatible = "socionext,uniphier-pxs2-usb3-ssphy";
671				reg = <0x300 0x10>;
672				#phy-cells = <0>;
673				clock-names = "link", "phy";
674				clocks = <&sys_clk 14>, <&sys_clk 17>;
675				reset-names = "link", "phy";
676				resets = <&sys_rst 14>, <&sys_rst 17>;
677				vbus-supply = <&usb0_vbus0>;
678			};
679
680			usb0_ssphy1: ss-phy@310 {
681				compatible = "socionext,uniphier-pxs2-usb3-ssphy";
682				reg = <0x310 0x10>;
683				#phy-cells = <0>;
684				clock-names = "link", "phy";
685				clocks = <&sys_clk 14>, <&sys_clk 18>;
686				reset-names = "link", "phy";
687				resets = <&sys_rst 14>, <&sys_rst 18>;
688				vbus-supply = <&usb0_vbus1>;
689			};
690		};
691
692		/* FIXME: U-Boot own node */
693		usb0: usb@65b00000 {
694			compatible = "socionext,uniphier-pxs2-dwc3";
695			status = "disabled";
696			reg = <0x65b00000 0x1000>;
697			#address-cells = <1>;
698			#size-cells = <1>;
699			ranges;
700			pinctrl-names = "default";
701			pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
702			dwc3@65a00000 {
703				compatible = "snps,dwc3";
704				reg = <0x65a00000 0x10000>;
705				interrupts = <0 134 4>;
706				dr_mode = "host";
707				tx-fifo-resize;
708			};
709		};
710
711		_usb1: usb@65c00000 {
712			compatible = "socionext,uniphier-dwc3", "snps,dwc3";
713			status = "disabled";
714			reg = <0x65c00000 0xcd00>;
715			interrupt-names = "host", "peripheral";
716			interrupts = <0 137 4>, <0 138 4>;
717			pinctrl-names = "default";
718			pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
719			clock-names = "ref", "bus_early", "suspend";
720			clocks = <&sys_clk 15>, <&sys_clk 15>, <&sys_clk 15>;
721			resets = <&usb1_rst 15>;
722			phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>;
723			dr_mode = "host";
724		};
725
726		usb-glue@65d00000 {
727			compatible = "socionext,uniphier-pxs2-dwc3-glue",
728				     "simple-mfd";
729			#address-cells = <1>;
730			#size-cells = <1>;
731			ranges = <0 0x65d00000 0x400>;
732
733			usb1_rst: reset@0 {
734				compatible = "socionext,uniphier-pxs2-usb3-reset";
735				reg = <0x0 0x4>;
736				#reset-cells = <1>;
737				clock-names = "link";
738				clocks = <&sys_clk 15>;
739				reset-names = "link";
740				resets = <&sys_rst 15>;
741			};
742
743			usb1_vbus0: regulator@100 {
744				compatible = "socionext,uniphier-pxs2-usb3-regulator";
745				reg = <0x100 0x10>;
746				clock-names = "link";
747				clocks = <&sys_clk 15>;
748				reset-names = "link";
749				resets = <&sys_rst 15>;
750			};
751
752			usb1_vbus1: regulator@110 {
753				compatible = "socionext,uniphier-pxs2-usb3-regulator";
754				reg = <0x110 0x10>;
755				clock-names = "link";
756				clocks = <&sys_clk 15>;
757				reset-names = "link";
758				resets = <&sys_rst 15>;
759			};
760
761			usb1_hsphy0: hs-phy@200 {
762				compatible = "socionext,uniphier-pxs2-usb3-hsphy";
763				reg = <0x200 0x10>;
764				#phy-cells = <0>;
765				clock-names = "link", "phy";
766				clocks = <&sys_clk 15>, <&sys_clk 20>;
767				reset-names = "link", "phy";
768				resets = <&sys_rst 15>, <&sys_rst 20>;
769				vbus-supply = <&usb1_vbus0>;
770			};
771
772			usb1_hsphy1: hs-phy@210 {
773				compatible = "socionext,uniphier-pxs2-usb3-hsphy";
774				reg = <0x210 0x10>;
775				#phy-cells = <0>;
776				clock-names = "link", "phy";
777				clocks = <&sys_clk 15>, <&sys_clk 20>;
778				reset-names = "link", "phy";
779				resets = <&sys_rst 15>, <&sys_rst 20>;
780				vbus-supply = <&usb1_vbus1>;
781			};
782
783			usb1_ssphy0: ss-phy@300 {
784				compatible = "socionext,uniphier-pxs2-usb3-ssphy";
785				reg = <0x300 0x10>;
786				#phy-cells = <0>;
787				clock-names = "link", "phy";
788				clocks = <&sys_clk 15>, <&sys_clk 21>;
789				reset-names = "link", "phy";
790				resets = <&sys_rst 15>, <&sys_rst 21>;
791				vbus-supply = <&usb1_vbus0>;
792			};
793		};
794
795		/* FIXME: U-Boot own node */
796		usb1: usb@65d00000 {
797			compatible = "socionext,uniphier-pxs2-dwc3";
798			status = "disabled";
799			reg = <0x65d00000 0x1000>;
800			#address-cells = <1>;
801			#size-cells = <1>;
802			ranges;
803			pinctrl-names = "default";
804			pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
805			dwc3@65c00000 {
806				compatible = "snps,dwc3";
807				reg = <0x65c00000 0x10000>;
808				interrupts = <0 137 4>;
809				dr_mode = "host";
810				tx-fifo-resize;
811			};
812		};
813
814		nand: nand-controller@68000000 {
815			compatible = "socionext,uniphier-denali-nand-v5b";
816			status = "disabled";
817			reg-names = "nand_data", "denali_reg";
818			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
819			interrupts = <0 65 4>;
820			pinctrl-names = "default";
821			pinctrl-0 = <&pinctrl_nand2cs>;
822			clock-names = "nand", "nand_x", "ecc";
823			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
824			reset-names = "nand", "reg";
825			resets = <&sys_rst 2>, <&sys_rst 2>;
826		};
827	};
828};
829
830#include "uniphier-pinctrl.dtsi"
831