1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Clock specification for Xilinx ZynqMP
4 *
5 * (C) Copyright 2017 - 2020, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
11/ {
12	fclk0: fclk0 {
13		status = "okay";
14		compatible = "xlnx,fclk";
15		clocks = <&zynqmp_clk PL0_REF>;
16	};
17
18	fclk1: fclk1 {
19		status = "okay";
20		compatible = "xlnx,fclk";
21		clocks = <&zynqmp_clk PL1_REF>;
22	};
23
24	fclk2: fclk2 {
25		status = "okay";
26		compatible = "xlnx,fclk";
27		clocks = <&zynqmp_clk PL2_REF>;
28	};
29
30	fclk3: fclk3 {
31		status = "okay";
32		compatible = "xlnx,fclk";
33		clocks = <&zynqmp_clk PL3_REF>;
34	};
35
36	pss_ref_clk: pss_ref_clk {
37		u-boot,dm-pre-reloc;
38		compatible = "fixed-clock";
39		#clock-cells = <0>;
40		clock-frequency = <33333333>;
41	};
42
43	video_clk: video_clk {
44		u-boot,dm-pre-reloc;
45		compatible = "fixed-clock";
46		#clock-cells = <0>;
47		clock-frequency = <27000000>;
48	};
49
50	pss_alt_ref_clk: pss_alt_ref_clk {
51		u-boot,dm-pre-reloc;
52		compatible = "fixed-clock";
53		#clock-cells = <0>;
54		clock-frequency = <0>;
55	};
56
57	gt_crx_ref_clk: gt_crx_ref_clk {
58		u-boot,dm-pre-reloc;
59		compatible = "fixed-clock";
60		#clock-cells = <0>;
61		clock-frequency = <108000000>;
62	};
63
64	aux_ref_clk: aux_ref_clk {
65		u-boot,dm-pre-reloc;
66		compatible = "fixed-clock";
67		#clock-cells = <0>;
68		clock-frequency = <27000000>;
69	};
70
71	dp_aclk: dp_aclk {
72		compatible = "fixed-clock";
73		#clock-cells = <0>;
74		clock-frequency = <100000000>;
75		clock-accuracy = <100>;
76	};
77};
78
79&zynqmp_firmware {
80	zynqmp_clk: clock-controller {
81		u-boot,dm-pre-reloc;
82		#clock-cells = <1>;
83		compatible = "xlnx,zynqmp-clk";
84		clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
85			 <&aux_ref_clk>, <&gt_crx_ref_clk>;
86		clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
87			      "aux_ref_clk", "gt_crx_ref_clk";
88	};
89};
90
91&can0 {
92	clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
93};
94
95&can1 {
96	clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
97};
98
99&cpu0 {
100	clocks = <&zynqmp_clk ACPU>;
101};
102
103&fpd_dma_chan1 {
104	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
105};
106
107&fpd_dma_chan2 {
108	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
109};
110
111&fpd_dma_chan3 {
112	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
113};
114
115&fpd_dma_chan4 {
116	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
117};
118
119&fpd_dma_chan5 {
120	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
121};
122
123&fpd_dma_chan6 {
124	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
125};
126
127&fpd_dma_chan7 {
128	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
129};
130
131&fpd_dma_chan8 {
132	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
133};
134
135&gpu {
136	clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>, <&zynqmp_clk GPU_PP1_REF>;
137};
138
139&lpd_dma_chan1 {
140	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
141};
142
143&lpd_dma_chan2 {
144	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
145};
146
147&lpd_dma_chan3 {
148	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
149};
150
151&lpd_dma_chan4 {
152	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
153};
154
155&lpd_dma_chan5 {
156	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
157};
158
159&lpd_dma_chan6 {
160	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
161};
162
163&lpd_dma_chan7 {
164	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
165};
166
167&lpd_dma_chan8 {
168	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
169};
170
171&nand0 {
172	clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;
173};
174
175&gem0 {
176	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
177		 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
178		 <&zynqmp_clk GEM_TSU>;
179	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
180};
181
182&gem1 {
183	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
184		 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
185		 <&zynqmp_clk GEM_TSU>;
186	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
187};
188
189&gem2 {
190	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
191		 <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
192		 <&zynqmp_clk GEM_TSU>;
193	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
194};
195
196&gem3 {
197	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
198		 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
199		 <&zynqmp_clk GEM_TSU>;
200	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
201};
202
203&gpio {
204	clocks = <&zynqmp_clk LPD_LSBUS>;
205};
206
207&i2c0 {
208	clocks = <&zynqmp_clk I2C0_REF>;
209};
210
211&i2c1 {
212	clocks = <&zynqmp_clk I2C1_REF>;
213};
214
215&pcie {
216	clocks = <&zynqmp_clk PCIE_REF>;
217};
218
219&qspi {
220	clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
221};
222
223&sata {
224	clocks = <&zynqmp_clk SATA_REF>;
225};
226
227&sdhci0 {
228	clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
229};
230
231&sdhci1 {
232	clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
233};
234
235&spi0 {
236	clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
237};
238
239&spi1 {
240	clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
241};
242
243&ttc0 {
244	clocks = <&zynqmp_clk LPD_LSBUS>;
245};
246
247&ttc1 {
248	clocks = <&zynqmp_clk LPD_LSBUS>;
249};
250
251&ttc2 {
252	clocks = <&zynqmp_clk LPD_LSBUS>;
253};
254
255&ttc3 {
256	clocks = <&zynqmp_clk LPD_LSBUS>;
257};
258
259&uart0 {
260	clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
261};
262
263&uart1 {
264	clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
265};
266
267&usb0 {
268	clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
269};
270
271&usb1 {
272	clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
273};
274
275&watchdog0 {
276	clocks = <&zynqmp_clk WDT>;
277};
278
279&lpd_watchdog {
280	clocks = <&zynqmp_clk LPD_WDT>;
281};
282
283&xilinx_ams {
284	clocks = <&zynqmp_clk AMS_REF>;
285};
286
287&zynqmp_pcap {
288	clocks = <&zynqmp_clk PCAP>;
289};
290
291&zynqmp_dpdma {
292	clocks = <&zynqmp_clk DPDMA_REF>;
293};
294
295&zynqmp_dpsub {
296	clocks = <&zynqmp_clk TOPSW_LSBUS>,
297		 <&zynqmp_clk DP_AUDIO_REF>,
298		 <&zynqmp_clk DP_VIDEO_REF>;
299};
300