1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for Xilinx Versal a2197 RevA System Controller 4 * 5 * (C) Copyright 2019 - 2021, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9/dts-v1/; 10 11#include "zynqmp.dtsi" 12#include "zynqmp-clk-ccf.dtsi" 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/phy/phy.h> 15 16/ { 17 model = "Versal System Controller on a2197 Eval board RevA"; /* VCK190/VMK180 */ 18 compatible = "xlnx,zynqmp-e-a2197-00-revA", "xlnx,zynqmp-a2197-revA", 19 "xlnx,zynqmp-a2197", "xlnx,zynqmp"; 20 21 aliases { 22 ethernet0 = &gem0; 23 gpio0 = &gpio; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 mmc0 = &sdhci1; 27 rtc0 = &rtc; 28 serial0 = &uart0; 29 serial1 = &dcc; 30 }; 31 32 chosen { 33 bootargs = "earlycon"; 34 stdout-path = "serial0:115200n8"; 35 xlnx,eeprom = <&eeprom>; 36 }; 37 38 memory@0 { 39 device_type = "memory"; 40 reg = <0x0 0x0 0x0 0x80000000>; 41 }; 42 43 ina226-vccint { 44 compatible = "iio-hwmon"; 45 io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; 46 }; 47 ina226-vcc-soc { 48 compatible = "iio-hwmon"; 49 io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>; 50 }; 51 ina226-vcc-pmc { 52 compatible = "iio-hwmon"; 53 io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>; 54 }; 55 ina226-vcc-ram { 56 compatible = "iio-hwmon"; 57 io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; 58 }; 59 ina226-vcc-pslp { 60 compatible = "iio-hwmon"; 61 io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>; 62 }; 63 ina226-vcc-psfp { 64 compatible = "iio-hwmon"; 65 io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>; 66 }; 67 ina226-vccaux { 68 compatible = "iio-hwmon"; 69 io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>; 70 }; 71 ina226-vccaux-pmc { 72 compatible = "iio-hwmon"; 73 io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>; 74 }; 75 ina226-vcco-500 { 76 compatible = "iio-hwmon"; 77 io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>; 78 }; 79 ina226-vcco-501 { 80 compatible = "iio-hwmon"; 81 io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>; 82 }; 83 ina226-vcco-502 { 84 compatible = "iio-hwmon"; 85 io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>; 86 }; 87 ina226-vcco-503 { 88 compatible = "iio-hwmon"; 89 io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>; 90 }; 91 ina226-vcc-1v8 { 92 compatible = "iio-hwmon"; 93 io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>; 94 }; 95 ina226-vcc-3v3 { 96 compatible = "iio-hwmon"; 97 io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>; 98 }; 99 ina226-vcc-1v2-ddr4 { 100 compatible = "iio-hwmon"; 101 io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>; 102 }; 103 ina226-vcc-1v1-lp4 { 104 compatible = "iio-hwmon"; 105 io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; 106 }; 107 ina226-vadj-fmc { 108 compatible = "iio-hwmon"; 109 io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; 110 }; 111 ina226-mgtyavcc { 112 compatible = "iio-hwmon"; 113 io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>; 114 }; 115 ina226-mgtyavtt { 116 compatible = "iio-hwmon"; 117 io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>; 118 }; 119 ina226-mgtyvccaux { 120 compatible = "iio-hwmon"; 121 io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>; 122 }; 123}; 124 125&uart0 { /* uart0 MIO38-39 */ 126 status = "okay"; 127 u-boot,dm-pre-reloc; 128}; 129 130&sdhci1 { /* sd1 MIO45-51 cd in place */ 131 status = "okay"; 132 no-1-8-v; 133 disable-wp; 134 xlnx,mio-bank = <1>; 135}; 136 137&gem0 { 138 status = "okay"; 139 phy-handle = <&phy0>; 140 phy-mode = "sgmii"; 141 is-internal-pcspma; 142 phy0: ethernet-phy@0 { /* u131 M88E1512 */ 143 reg = <0>; 144 }; 145}; 146 147&gpio { 148 status = "okay"; 149 gpio-line-names = "", "", "", "", "", /* 0 - 4 */ 150 "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ 151 "DC_SYS_CTRL3", "ZU4_TRIGGER", "SYSCTLR_PB", "", "", /* 10 - 14 */ 152 "", "", "", "", "", /* 15 - 19 */ 153 "", "", "", "", "", /* 20 - 24 */ 154 "", "", "", "", "", /* 25 - 29 */ 155 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ 156 "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ 157 "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ 158 "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ 159 "SD1_CMD", "SD1_CLK", "", "", "", /* 50 - 54 */ 160 "", "", "", "", "", /* 55 - 59 */ 161 "", "", "", "", "", /* 60 - 64 */ 162 "", "", "", "", "", /* 65 - 69 */ 163 "", "", "", "", "", /* 70 - 74 */ 164 "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ 165 "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ 166 "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "", /* 80 - 84 */ 167 "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */ 168 "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ 169 "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */ 170 "", "", "", "", "", /* 100 - 104 */ 171 "", "", "", "", "", /* 105 - 109 */ 172 "", "", "", "", "", /* 110 - 114 */ 173 "", "", "", "", "", /* 115 - 119 */ 174 "", "", "", "", "", /* 120 - 124 */ 175 "", "", "", "", "", /* 125 - 129 */ 176 "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "", "", "", /* 130 - 134 */ 177 "", "", "", "", "", /* 135 - 139 */ 178 "PMBUS_ALERT", "", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ 179 "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ 180 "", "", "", "", "", /* 150 - 154 */ 181 "", "", "", "", "", /* 155 - 159 */ 182 "", "", "", "", "", /* 160 - 164 */ 183 "", "", "", "", "", /* 165 - 169 */ 184 "", "", "", ""; /* 170 - 174 */ 185}; 186 187&i2c0 { /* MIO 34-35 - can't stay here */ 188 status = "okay"; 189 clock-frequency = <400000>; 190 i2c-mux@74 { /* u33 */ 191 compatible = "nxp,pca9548"; 192 #address-cells = <1>; 193 #size-cells = <0>; 194 reg = <0x74>; 195 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ 196 i2c@0 { /* PMBUS */ 197 #address-cells = <1>; 198 #size-cells = <0>; 199 reg = <0>; 200 /* u152 IR35215 0x16/0x46 vcc_soc */ 201 /* u179 ir38164 0x19/0x49 vcco_500 */ 202 /* u181 ir38164 0x1a/0x4a vcco_501 */ 203 /* u183 ir38164 0x1b/0x4b vcco_502 */ 204 /* u185 ir38164 0x1e/0x4e vadj_fmc */ 205 /* u187 ir38164 0x1F/0x4f mgtyavcc */ 206 /* u189 ir38164 0x20/0x50 mgtyavtt */ 207 /* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */ 208 /* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */ 209 210 irps5401_47: irps5401@47 { /* IRPS5401 - u160 */ 211 compatible = "infineon,irps5401"; 212 reg = <0x47>; /* pmbus / i2c 0x17 */ 213 }; 214 irps5401_4c: irps5401@4c { /* IRPS5401 - u167 */ 215 compatible = "infineon,irps5401"; 216 reg = <0x4c>; /* pmbus / i2c 0x1c */ 217 }; 218 irps5401_4d: irps5401@4d { /* IRPS5401 - u175 */ 219 compatible = "infineon,irps5401"; 220 reg = <0x4d>; /* pmbus / i2c 0x1d */ 221 }; 222 }; 223 i2c@1 { /* PMBUS1_INA226 */ 224 #address-cells = <1>; 225 #size-cells = <0>; 226 reg = <1>; 227 /* FIXME check alerts coming to SC */ 228 vccint: ina226@40 { /* u65 */ 229 compatible = "ti,ina226"; 230 #io-channel-cells = <1>; 231 label = "ina226-vccint"; 232 reg = <0x40>; 233 shunt-resistor = <500>; /* R440 */ 234 /* 0.80V @ 32A 1 of 6 Phases*/ 235 }; 236 vcc_soc: ina226@41 { /* u161 */ 237 compatible = "ti,ina226"; 238 #io-channel-cells = <1>; 239 label = "ina226-vcc-soc"; 240 reg = <0x41>; 241 shunt-resistor = <500>; /* R1702 */ 242 /* 0.80V @ 18A */ 243 }; 244 vcc_pmc: ina226@42 { /* u163 */ 245 compatible = "ti,ina226"; 246 #io-channel-cells = <1>; 247 label = "ina226-vcc-pmc"; 248 reg = <0x42>; 249 shunt-resistor = <5000>; /* R1214 */ 250 /* 0.78V @ 500mA */ 251 }; 252 vcc_ram: ina226@43 { /* u162 */ 253 compatible = "ti,ina226"; 254 #io-channel-cells = <1>; 255 label = "ina226-vcc-ram"; 256 reg = <0x43>; 257 shunt-resistor = <5000>; /* r1221 */ 258 /* 0.78V @ 4A */ 259 }; 260 vcc_pslp: ina226@44 { /* u165 */ 261 compatible = "ti,ina226"; 262 #io-channel-cells = <1>; 263 label = "ina226-vcc-pslp"; 264 reg = <0x44>; 265 shunt-resistor = <5000>; /* R1216 */ 266 /* 0.78V @ 1A */ 267 }; 268 vcc_psfp: ina226@45 { /* u164 */ 269 compatible = "ti,ina226"; 270 #io-channel-cells = <1>; 271 label = "ina226-vcc-psfp"; 272 reg = <0x45>; 273 shunt-resistor = <5000>; /* R1219 */ 274 /* 0.78V @ 2A */ 275 }; 276 }; 277 i2c@2 { /* PCIE_CLK */ 278 #address-cells = <1>; 279 #size-cells = <0>; 280 reg = <2>; 281 clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 */ 282 #clock-cells = <1>; /* author David Cater <david.cater@idt.com>*/ 283 compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ 284 reg = <0xd8>; 285 /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ 286 /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ 287 }; 288 }; 289 i2c@3 { /* PMBUS2_INA226 */ 290 #address-cells = <1>; 291 #size-cells = <0>; 292 reg = <3>; 293 /* FIXME check alerts coming to SC */ 294 vccaux: ina226@40 { /* u166 */ 295 compatible = "ti,ina226"; 296 #io-channel-cells = <1>; 297 label = "ina226-vccaux"; 298 reg = <0x40>; 299 shunt-resistor = <5000>; /* R382 */ 300 /* 1.5V @ 3A */ 301 }; 302 vccaux_pmc: ina226@41 { /* u168 */ 303 compatible = "ti,ina226"; 304 #io-channel-cells = <1>; 305 label = "ina226-vccaux-pmc"; 306 reg = <0x41>; 307 shunt-resistor = <5000>; /* R1246 */ 308 /* 1.5V @ 500mA */ 309 }; 310 vcco_500: ina226@42 { /* u178 */ 311 compatible = "ti,ina226"; 312 #io-channel-cells = <1>; 313 label = "ina226-vcco-500"; 314 reg = <0x42>; 315 shunt-resistor = <2000>; /* R1300 */ 316 /* 3.3V @ 5A */ 317 }; 318 vcco_501: ina226@43 { /* u180 */ 319 compatible = "ti,ina226"; 320 #io-channel-cells = <1>; 321 label = "ina226-vcco-501"; 322 reg = <0x43>; 323 shunt-resistor = <2000>; /* R1313 */ 324 /* 3.3V @ 5A */ 325 }; 326 vcco_502: ina226@44 { /* u182 */ 327 compatible = "ti,ina226"; 328 #io-channel-cells = <1>; 329 label = "ina226-vcco-502"; 330 reg = <0x44>; 331 shunt-resistor = <2000>; /* R1330 */ 332 /* 3.3V @ 5A */ 333 }; 334 vcco_503: ina226@45 { /* u172 */ 335 compatible = "ti,ina226"; 336 #io-channel-cells = <1>; 337 label = "ina226-vcco-503"; 338 reg = <0x45>; 339 shunt-resistor = <5000>; /* R1229 */ 340 /* 1.8V @ 2A */ 341 }; 342 vcc_1v8: ina226@46 { /* u173 */ 343 compatible = "ti,ina226"; 344 #io-channel-cells = <1>; 345 label = "ina226-vcc-1v8"; 346 reg = <0x46>; 347 shunt-resistor = <5000>; /* R400 */ 348 /* 1.8V @ 6A */ 349 }; 350 vcc_3v3: ina226@47 { /* u174 */ 351 compatible = "ti,ina226"; 352 #io-channel-cells = <1>; 353 label = "ina226-vcc-3v3"; 354 reg = <0x47>; 355 shunt-resistor = <5000>; /* R1232 */ 356 /* 3.3V @ 500mA */ 357 }; 358 vcc_1v2_ddr4: ina226@48 { /* u176 */ 359 compatible = "ti,ina226"; 360 #io-channel-cells = <1>; 361 label = "ina226-vcc-1v2-ddr4"; 362 reg = <0x48>; 363 shunt-resistor = <5000>; /* R1275 */ 364 /* 1.2V @ 4A */ 365 }; 366 vcc1v1_lp4: ina226@49 { /* u177 */ 367 compatible = "ti,ina226"; 368 #io-channel-cells = <1>; 369 label = "ina226-vcc1v1-lp4"; 370 reg = <0x49>; 371 shunt-resistor = <5000>; /* R1286 */ 372 /* 1.1V @ 4A */ 373 }; 374 vadj_fmc: ina226@4a { /* u184 */ 375 compatible = "ti,ina226"; 376 #io-channel-cells = <1>; 377 label = "ina226-vadj-fmc"; 378 reg = <0x4a>; 379 shunt-resistor = <2000>; /* R1350 */ 380 /* 1.5V @ 10A */ 381 }; 382 mgtyavcc: ina226@4b { /* u186 */ 383 compatible = "ti,ina226"; 384 #io-channel-cells = <1>; 385 label = "ina226-mgtyavcc"; 386 reg = <0x4b>; 387 shunt-resistor = <2000>; /* R1367 */ 388 /* 0.88V @ 6A */ 389 }; 390 mgtyavtt: ina226@4c { /* u188 */ 391 compatible = "ti,ina226"; 392 #io-channel-cells = <1>; 393 label = "ina226-mgtyavtt"; 394 reg = <0x4c>; 395 shunt-resistor = <2000>; /* R1384 */ 396 /* 1.2V @ 10A */ 397 }; 398 mgtyvccaux: ina226@4d { /* u234 */ 399 compatible = "ti,ina226"; 400 #io-channel-cells = <1>; 401 label = "ina226-mgtyvccaux"; 402 reg = <0x4d>; 403 shunt-resistor = <5000>; /* r1679 */ 404 /* 1.5V @ 500mA */ 405 }; 406 }; 407 i2c@4 { /* LP_I2C_SM */ 408 #address-cells = <1>; 409 #size-cells = <0>; 410 reg = <4>; 411 /* FIXME wires ready but chip is missing */ 412 }; 413 i2c@5 { /* zSFP_SI570 */ 414 #address-cells = <1>; 415 #size-cells = <0>; 416 reg = <5>; 417 si570_zsfp: clock-generator@5d { /* u192 */ 418 #clock-cells = <0>; 419 compatible = "silabs,si570"; 420 reg = <0x5d>; 421 temperature-stability = <50>; 422 factory-fout = <156250000>; 423 clock-frequency = <156250000>; 424 clock-output-names = "si570_zsfp_clk"; 425 }; 426 }; 427 i2c@6 { /* USER_SI570_1 */ 428 #address-cells = <1>; 429 #size-cells = <0>; 430 reg = <6>; 431 si570_user1: clock-generator@5d { /* u205 */ 432 #clock-cells = <0>; 433 compatible = "silabs,si570"; 434 reg = <0x5f>; 435 temperature-stability = <50>; 436 factory-fout = <100000000>; 437 clock-frequency = <100000000>; 438 clock-output-names = "si570_user1"; 439 }; 440 441 }; 442 i2c@7 { /* USER_SI570_2 */ 443 #address-cells = <1>; 444 #size-cells = <0>; 445 reg = <7>; 446 /* FIXME wires ready but chip is missing */ 447 }; 448 }; 449}; 450 451&i2c1 { /* i2c1 MIO 36-37 */ 452 status = "okay"; 453 clock-frequency = <400000>; 454 455 i2c-mux@74 { /* u35 */ 456 compatible = "nxp,pca9548"; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 reg = <0x74>; 460 i2c-mux-idle-disconnect; 461 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ 462 dc_i2c: i2c@0 { /* DC_I2C */ 463 #address-cells = <1>; 464 #size-cells = <0>; 465 reg = <0>; 466 /* Use for storing information about SC board */ 467 eeprom: eeprom@54 { /* u34 - m24128 16kB */ 468 compatible = "st,24c128", "atmel,24c128"; 469 reg = <0x54>; /* 0x5c too */ 470 }; 471 si570_ref_clk: clock-generator@5d { /* u32 */ 472 #clock-cells = <0>; 473 compatible = "silabs,si570"; 474 reg = <0x5d>; 475 temperature-stability = <50>; 476 factory-fout = <33333333>; 477 clock-frequency = <33333333>; 478 clock-output-names = "ref_clk"; 479 silabs,skip-recall; 480 }; 481 /* and connector J212D */ 482 }; 483 fmc1: i2c@1 { /* FMCP1_IIC */ 484 #address-cells = <1>; 485 #size-cells = <0>; 486 reg = <1>; 487 /* FIXME connection to Samtec J51C */ 488 /* expected eeprom 0x50 FMC cards */ 489 }; 490 fmc2: i2c@2 { /* FMCP2_IIC */ 491 #address-cells = <1>; 492 #size-cells = <0>; 493 reg = <2>; 494 /* FIXME connection to Samtec J53C */ 495 /* expected eeprom 0x50 FMC cards */ 496 }; 497 i2c@3 { /* DDR4_DIMM1 */ 498 #address-cells = <1>; 499 #size-cells = <0>; 500 reg = <3>; 501 si570_ddr_dimm1: clock-generator@60 { /* u2 */ 502 #clock-cells = <0>; 503 compatible = "silabs,si570"; 504 reg = <0x60>; 505 temperature-stability = <50>; 506 factory-fout = <200000000>; 507 clock-frequency = <200000000>; 508 clock-output-names = "si570_ddrdimm1_clk"; 509 silabs,skip-recall; 510 }; 511 }; 512 i2c@4 { /* LPDDR4_SI570_CLK2 */ 513 #address-cells = <1>; 514 #size-cells = <0>; 515 reg = <4>; 516 si570_lpddr4clk2: clock-generator@60 { /* u3 */ 517 #clock-cells = <0>; 518 compatible = "silabs,si570"; 519 reg = <0x60>; 520 temperature-stability = <50>; 521 factory-fout = <200000000>; 522 clock-frequency = <200000000>; 523 clock-output-names = "si570_lpddr4_clk2"; 524 }; 525 }; 526 i2c@5 { /* LPDDR4_SI570_CLK1 */ 527 #address-cells = <1>; 528 #size-cells = <0>; 529 reg = <5>; 530 si570_lpddr4clk1: clock-generator@60 { /* u4 */ 531 #clock-cells = <0>; 532 compatible = "silabs,si570"; 533 reg = <0x60>; 534 temperature-stability = <50>; 535 factory-fout = <200000000>; 536 clock-frequency = <200000000>; 537 clock-output-names = "si570_lpddr4_clk1"; 538 }; 539 }; 540 i2c@6 { /* HSDP_SI570 */ 541 #address-cells = <1>; 542 #size-cells = <0>; 543 reg = <6>; 544 si570_hsdp: clock-generator@5d { /* u5 */ 545 #clock-cells = <0>; 546 compatible = "silabs,si570"; 547 reg = <0x5d>; 548 temperature-stability = <50>; 549 factory-fout = <156250000>; 550 clock-frequency = <156250000>; 551 clock-output-names = "si570_hsdp_clk"; 552 }; 553 }; 554 i2c@7 { /* 8A34001 - U219B and J310 connector */ 555 #address-cells = <1>; 556 #size-cells = <0>; 557 reg = <7>; 558 }; 559 }; 560 i2c-mux@75 { /* u214 */ 561 compatible = "nxp,pca9548"; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 reg = <0x75>; 565 i2c-mux-idle-disconnect; 566 i2c@0 { /* SFP0_IIC */ 567 #address-cells = <1>; 568 #size-cells = <0>; 569 reg = <0>; 570 /* SFP0 */ 571 }; 572 i2c@1 { /* SFP1_IIC */ 573 #address-cells = <1>; 574 #size-cells = <0>; 575 reg = <1>; 576 /* SFP1 */ 577 }; 578 i2c@2 { /* QSFP1_I2C */ 579 #address-cells = <1>; 580 #size-cells = <0>; 581 reg = <2>; 582 /* QSFP1 */ 583 }; 584 /* 3 - 7 unused */ 585 }; 586}; 587 588&xilinx_ams { 589 status = "okay"; 590}; 591 592&ams_ps { 593 status = "okay"; 594}; 595 596&ams_pl { 597 status = "okay"; 598}; 599