1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU104
4 *
5 * (C) Copyright 2017 - 2020, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
16#include <dt-bindings/phy/phy.h>
17
18/ {
19	model = "ZynqMP ZCU104 RevC";
20	compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
21
22	aliases {
23		ethernet0 = &gem3;
24		gpio0 = &gpio;
25		i2c0 = &i2c1;
26		mmc0 = &sdhci1;
27		rtc0 = &rtc;
28		serial0 = &uart0;
29		serial1 = &uart1;
30		serial2 = &dcc;
31		spi0 = &qspi;
32		usb0 = &usb0;
33	};
34
35	chosen {
36		bootargs = "earlycon";
37		stdout-path = "serial0:115200n8";
38		xlnx,eeprom = &eeprom;
39	};
40
41	memory@0 {
42		device_type = "memory";
43		reg = <0x0 0x0 0x0 0x80000000>;
44	};
45
46	ina226 {
47		compatible = "iio-hwmon";
48		io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
49	};
50
51	clock_8t49n287_5: clk125 {
52		compatible = "fixed-clock";
53		#clock-cells = <0>;
54		clock-frequency = <125000000>;
55	};
56
57	clock_8t49n287_2: clk26 {
58		compatible = "fixed-clock";
59		#clock-cells = <0>;
60		clock-frequency = <26000000>;
61	};
62
63	clock_8t49n287_3: clk27 {
64		compatible = "fixed-clock";
65		#clock-cells = <0>;
66		clock-frequency = <27000000>;
67	};
68};
69
70&can1 {
71	status = "okay";
72	pinctrl-names = "default";
73	pinctrl-0 = <&pinctrl_can1_default>;
74};
75
76&dcc {
77	status = "okay";
78};
79
80&fpd_dma_chan1 {
81	status = "okay";
82};
83
84&fpd_dma_chan2 {
85	status = "okay";
86};
87
88&fpd_dma_chan3 {
89	status = "okay";
90};
91
92&fpd_dma_chan4 {
93	status = "okay";
94};
95
96&fpd_dma_chan5 {
97	status = "okay";
98};
99
100&fpd_dma_chan6 {
101	status = "okay";
102};
103
104&fpd_dma_chan7 {
105	status = "okay";
106};
107
108&fpd_dma_chan8 {
109	status = "okay";
110};
111
112&gem3 {
113	status = "okay";
114	phy-handle = <&phy0>;
115	phy-mode = "rgmii-id";
116	pinctrl-names = "default";
117	pinctrl-0 = <&pinctrl_gem3_default>;
118	phy0: ethernet-phy@c {
119		reg = <0xc>;
120		ti,rx-internal-delay = <0x8>;
121		ti,tx-internal-delay = <0xa>;
122		ti,fifo-depth = <0x1>;
123		ti,dp83867-rxctrl-strap-quirk;
124	};
125};
126
127&gpio {
128	status = "okay";
129};
130
131&gpu {
132	status = "okay";
133};
134
135&i2c1 {
136	status = "okay";
137	clock-frequency = <400000>;
138	pinctrl-names = "default", "gpio";
139	pinctrl-0 = <&pinctrl_i2c1_default>;
140	pinctrl-1 = <&pinctrl_i2c1_gpio>;
141	scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
142	sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
143
144	tca6416_u97: gpio@20 {
145		compatible = "ti,tca6416";
146		reg = <0x20>;
147		gpio-controller;
148		#gpio-cells = <2>;
149		/*
150		 * IRQ not connected
151		 * Lines:
152		 * 0 - IRPS5401_ALERT_B
153		 * 1 - HDMI_8T49N241_INT_ALM
154		 * 2 - MAX6643_OT_B
155		 * 3 - MAX6643_FANFAIL_B
156		 * 5 - IIC_MUX_RESET_B
157		 * 6 - GEM3_EXP_RESET_B
158		 * 7 - FMC_LPC_PRSNT_M2C_B
159		 * 4, 10 - 17 - not connected
160		 */
161	};
162
163	/* Another connection to this bus via PL i2c via PCA9306 - u45 */
164	i2c-mux@74 { /* u34 */
165		compatible = "nxp,pca9548";
166		#address-cells = <1>;
167		#size-cells = <0>;
168		reg = <0x74>;
169		i2c@0 {
170			#address-cells = <1>;
171			#size-cells = <0>;
172			reg = <0>;
173			/*
174			 * IIC_EEPROM 1kB memory which uses 256B blocks
175			 * where every block has different address.
176			 *    0 - 256B address 0x54
177			 * 256B - 512B address 0x55
178			 * 512B - 768B address 0x56
179			 * 768B - 1024B address 0x57
180			 */
181			eeprom: eeprom@54 { /* u23 */
182				compatible = "atmel,24c08";
183				reg = <0x54>;
184				#address-cells = <1>;
185				#size-cells = <1>;
186			};
187		};
188
189		i2c@1 {
190			#address-cells = <1>;
191			#size-cells = <0>;
192			reg = <1>;
193			clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
194				compatible = "idt,8t49n287";
195				reg = <0x6c>;
196			};
197		};
198
199		i2c@2 {
200			#address-cells = <1>;
201			#size-cells = <0>;
202			reg = <2>;
203			irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
204				compatible = "infineon,irps5401";
205				reg = <0x43>; /* pmbus / i2c 0x13 */
206			};
207			irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
208				compatible = "infineon,irps5401";
209				reg = <0x44>; /* pmbus / i2c 0x14 */
210			};
211		};
212
213		i2c@3 {
214			#address-cells = <1>;
215			#size-cells = <0>;
216			reg = <3>;
217			u183: ina226@40 { /* u183 */
218				compatible = "ti,ina226";
219				#io-channel-cells = <1>;
220				reg = <0x40>;
221				shunt-resistor = <5000>;
222			};
223		};
224
225		i2c@5 {
226			#address-cells = <1>;
227			#size-cells = <0>;
228			reg = <5>;
229		};
230
231		i2c@7 {
232			#address-cells = <1>;
233			#size-cells = <0>;
234			reg = <7>;
235		};
236
237		/* 4, 6 not connected */
238	};
239};
240
241&pinctrl0 {
242	status = "okay";
243
244	pinctrl_can1_default: can1-default {
245		mux {
246			function = "can1";
247			groups = "can1_6_grp";
248		};
249
250		conf {
251			groups = "can1_6_grp";
252			slew-rate = <SLEW_RATE_SLOW>;
253			power-source = <IO_STANDARD_LVCMOS18>;
254			drive-strength = <12>;
255		};
256
257		conf-rx {
258			pins = "MIO25";
259			bias-high-impedance;
260		};
261
262		conf-tx {
263			pins = "MIO24";
264			bias-disable;
265		};
266	};
267
268	pinctrl_i2c1_default: i2c1-default {
269		mux {
270			groups = "i2c1_4_grp";
271			function = "i2c1";
272		};
273
274		conf {
275			groups = "i2c1_4_grp";
276			bias-pull-up;
277			slew-rate = <SLEW_RATE_SLOW>;
278			power-source = <IO_STANDARD_LVCMOS18>;
279			drive-strength = <12>;
280		};
281	};
282
283	pinctrl_i2c1_gpio: i2c1-gpio {
284		mux {
285			groups = "gpio0_16_grp", "gpio0_17_grp";
286			function = "gpio0";
287		};
288
289		conf {
290			groups = "gpio0_16_grp", "gpio0_17_grp";
291			slew-rate = <SLEW_RATE_SLOW>;
292			power-source = <IO_STANDARD_LVCMOS18>;
293			drive-strength = <12>;
294		};
295	};
296
297	pinctrl_gem3_default: gem3-default {
298		mux {
299			function = "ethernet3";
300			groups = "ethernet3_0_grp";
301		};
302
303		conf {
304			groups = "ethernet3_0_grp";
305			slew-rate = <SLEW_RATE_SLOW>;
306			power-source = <IO_STANDARD_LVCMOS18>;
307			drive-strength = <12>;
308		};
309
310		conf-rx {
311			pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
312									"MIO75";
313			bias-high-impedance;
314			low-power-disable;
315		};
316
317		conf-tx {
318			pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
319									"MIO69";
320			bias-disable;
321			low-power-enable;
322		};
323
324		mux-mdio {
325			function = "mdio3";
326			groups = "mdio3_0_grp";
327		};
328
329		conf-mdio {
330			groups = "mdio3_0_grp";
331			slew-rate = <SLEW_RATE_SLOW>;
332			power-source = <IO_STANDARD_LVCMOS18>;
333			bias-disable;
334		};
335	};
336
337	pinctrl_sdhci1_default: sdhci1-default {
338		mux {
339			groups = "sdio1_0_grp";
340			function = "sdio1";
341		};
342
343		conf {
344			groups = "sdio1_0_grp";
345			slew-rate = <SLEW_RATE_SLOW>;
346			power-source = <IO_STANDARD_LVCMOS18>;
347			bias-disable;
348			drive-strength = <12>;
349		};
350
351		mux-cd {
352			groups = "sdio1_cd_0_grp";
353			function = "sdio1_cd";
354		};
355
356		conf-cd {
357			groups = "sdio1_cd_0_grp";
358			bias-high-impedance;
359			bias-pull-up;
360			slew-rate = <SLEW_RATE_SLOW>;
361			power-source = <IO_STANDARD_LVCMOS18>;
362		};
363	};
364
365	pinctrl_uart0_default: uart0-default {
366		mux {
367			groups = "uart0_4_grp";
368			function = "uart0";
369		};
370
371		conf {
372			groups = "uart0_4_grp";
373			slew-rate = <SLEW_RATE_SLOW>;
374			power-source = <IO_STANDARD_LVCMOS18>;
375			drive-strength = <12>;
376		};
377
378		conf-rx {
379			pins = "MIO18";
380			bias-high-impedance;
381		};
382
383		conf-tx {
384			pins = "MIO19";
385			bias-disable;
386		};
387	};
388
389	pinctrl_uart1_default: uart1-default {
390		mux {
391			groups = "uart1_5_grp";
392			function = "uart1";
393		};
394
395		conf {
396			groups = "uart1_5_grp";
397			slew-rate = <SLEW_RATE_SLOW>;
398			power-source = <IO_STANDARD_LVCMOS18>;
399			drive-strength = <12>;
400		};
401
402		conf-rx {
403			pins = "MIO21";
404			bias-high-impedance;
405		};
406
407		conf-tx {
408			pins = "MIO20";
409			bias-disable;
410		};
411	};
412
413	pinctrl_usb0_default: usb0-default {
414		mux {
415			groups = "usb0_0_grp";
416			function = "usb0";
417		};
418
419		conf {
420			groups = "usb0_0_grp";
421			slew-rate = <SLEW_RATE_SLOW>;
422			power-source = <IO_STANDARD_LVCMOS18>;
423			drive-strength = <12>;
424		};
425
426		conf-rx {
427			pins = "MIO52", "MIO53", "MIO55";
428			bias-high-impedance;
429		};
430
431		conf-tx {
432			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
433			       "MIO60", "MIO61", "MIO62", "MIO63";
434			bias-disable;
435		};
436	};
437};
438
439&qspi {
440	status = "okay";
441	flash@0 {
442		compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
443		#address-cells = <1>;
444		#size-cells = <1>;
445		reg = <0x0>;
446		spi-tx-bus-width = <1>;
447		spi-rx-bus-width = <4>;
448		spi-max-frequency = <108000000>; /* Based on DC1 spec */
449		partition@0 { /* for testing purpose */
450			label = "qspi-fsbl-uboot";
451			reg = <0x0 0x100000>;
452		};
453		partition@100000 { /* for testing purpose */
454			label = "qspi-linux";
455			reg = <0x100000 0x500000>;
456		};
457		partition@600000 { /* for testing purpose */
458			label = "qspi-device-tree";
459			reg = <0x600000 0x20000>;
460		};
461		partition@620000 { /* for testing purpose */
462			label = "qspi-rootfs";
463			reg = <0x620000 0x5E0000>;
464		};
465	};
466};
467
468&rtc {
469	status = "okay";
470};
471
472&psgtr {
473	status = "okay";
474	/* nc, sata, usb3, dp */
475	clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
476	clock-names = "ref1", "ref2", "ref3";
477};
478
479&sata {
480	status = "okay";
481	/* SATA OOB timing settings */
482	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
483	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
484	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
485	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
486	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
487	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
488	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
489	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
490	phy-names = "sata-phy";
491	phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
492};
493
494/* SD1 with level shifter */
495&sdhci1 {
496	status = "okay";
497	no-1-8-v;
498	pinctrl-names = "default";
499	pinctrl-0 = <&pinctrl_sdhci1_default>;
500	xlnx,mio-bank = <1>;
501	disable-wp;
502};
503
504&uart0 {
505	status = "okay";
506	pinctrl-names = "default";
507	pinctrl-0 = <&pinctrl_uart0_default>;
508};
509
510&uart1 {
511	status = "okay";
512	pinctrl-names = "default";
513	pinctrl-0 = <&pinctrl_uart1_default>;
514};
515
516/* ULPI SMSC USB3320 */
517&usb0 {
518	status = "okay";
519	pinctrl-names = "default";
520	pinctrl-0 = <&pinctrl_usb0_default>;
521};
522
523&dwc3_0 {
524	status = "okay";
525	dr_mode = "host";
526	snps,usb3_lpm_capable;
527	phy-names = "usb3-phy";
528	phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
529	maximum-speed = "super-speed";
530};
531
532&watchdog0 {
533	status = "okay";
534};
535
536&xilinx_ams {
537	status = "okay";
538};
539
540&ams_ps {
541	status = "okay";
542};
543
544&ams_pl {
545	status = "okay";
546};
547
548&zynqmp_dpdma {
549	status = "okay";
550};
551
552&zynqmp_dpsub {
553	status = "okay";
554	phy-names = "dp-phy0", "dp-phy1";
555	phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
556	       <&psgtr 0 PHY_TYPE_DP 1 3>;
557};
558