1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2003
4 * Josef Baumgartner <josef.baumgartner@telex.de>
5 *
6 * MCF5282 additionals
7 * (C) Copyright 2005
8 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
9 * (c) Copyright 2010
10 * Arcturus Networks Inc. <www.arcturusnetworks.com>
11 *
12 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
13 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
14 * Hayden Fraser (Hayden.Fraser@freescale.com)
15 *
16 * MCF5275 additions
17 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
18 */
19
20 #include <common.h>
21 #include <cpu_func.h>
22 #include <init.h>
23 #include <watchdog.h>
24 #include <asm/immap.h>
25 #include <asm/io.h>
26
27 #if defined(CONFIG_CMD_NET)
28 #include <config.h>
29 #include <net.h>
30 #include <asm/fec.h>
31 #endif
32
33 #ifndef CONFIG_M5272
34 /* Only 5272 Flexbus chipselect is different from the rest */
init_fbcs(void)35 void init_fbcs(void)
36 {
37 fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
38
39 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
40 && defined(CONFIG_SYS_CS0_CTRL))
41 out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
42 out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
43 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
44 #else
45 #warning "Chip Select 0 are not initialized/used"
46 #endif
47 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
48 && defined(CONFIG_SYS_CS1_CTRL))
49 out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
50 out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
51 out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
52 #endif
53 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
54 && defined(CONFIG_SYS_CS2_CTRL))
55 out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
56 out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
57 out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
58 #endif
59 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
60 && defined(CONFIG_SYS_CS3_CTRL))
61 out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
62 out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
63 out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
64 #endif
65 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
66 && defined(CONFIG_SYS_CS4_CTRL))
67 out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
68 out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
69 out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
70 #endif
71 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
72 && defined(CONFIG_SYS_CS5_CTRL))
73 out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
74 out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
75 out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
76 #endif
77 #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
78 && defined(CONFIG_SYS_CS6_CTRL))
79 out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
80 out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
81 out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
82 #endif
83 #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
84 && defined(CONFIG_SYS_CS7_CTRL))
85 out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
86 out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
87 out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
88 #endif
89 }
90 #endif
91
92 #if defined(CONFIG_M5208)
cpu_init_f(void)93 void cpu_init_f(void)
94 {
95 scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
96
97 #ifndef CONFIG_WATCHDOG
98 wdog_t *wdg = (wdog_t *) MMAP_WDOG;
99
100 /* Disable the watchdog if we aren't using it */
101 out_be16(&wdg->cr, 0);
102 #endif
103
104 out_be32(&scm1->mpr, 0x77777777);
105 out_be32(&scm1->pacra, 0);
106 out_be32(&scm1->pacrb, 0);
107 out_be32(&scm1->pacrc, 0);
108 out_be32(&scm1->pacrd, 0);
109 out_be32(&scm1->pacre, 0);
110 out_be32(&scm1->pacrf, 0);
111
112 /* FlexBus Chipselect */
113 init_fbcs();
114
115 icache_enable();
116 }
117
118 /* initialize higher level parts of CPU like timers */
cpu_init_r(void)119 int cpu_init_r(void)
120 {
121 return (0);
122 }
123
uart_port_conf(int port)124 void uart_port_conf(int port)
125 {
126 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
127
128 /* Setup Ports: */
129 switch (port) {
130 case 0:
131 clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK);
132 setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
133 break;
134 case 1:
135 clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK);
136 setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
137 break;
138 case 2:
139 #ifdef CONFIG_SYS_UART2_PRI_GPIO
140 clrbits_8(&gpio->par_timer,
141 ~(GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK));
142 setbits_8(&gpio->par_timer,
143 GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
144 #endif
145 #ifdef CONFIG_SYS_UART2_ALT1_GPIO
146 clrbits_8(&gpio->par_feci2c,
147 ~(GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK));
148 setbits_8(&gpio->par_feci2c,
149 GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
150 #endif
151 #ifdef CONFIG_SYS_UART2_ALT1_GPIO
152 clrbits_8(&gpio->par_feci2c,
153 ~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK));
154 setbits_8(&gpio->par_feci2c,
155 GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
156 #endif
157 break;
158 }
159 }
160
161 #if defined(CONFIG_CMD_NET)
fecpin_setclear(fec_info_t * info,int setclear)162 int fecpin_setclear(fec_info_t *info, int setclear)
163 {
164 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
165
166 if (setclear) {
167 setbits_8(&gpio->par_fec,
168 GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
169 setbits_8(&gpio->par_feci2c,
170 GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO);
171 } else {
172 clrbits_8(&gpio->par_fec,
173 ~(GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK));
174 clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII_UNMASK);
175 }
176 return 0;
177 }
178 #endif /* CONFIG_CMD_NET */
179 #endif /* CONFIG_M5208 */
180
181 #if defined(CONFIG_M5253)
182 /*
183 * Breath some life into the CPU...
184 *
185 * Set up the memory map,
186 * initialize a bunch of registers,
187 * initialize the UPM's
188 */
cpu_init_f(void)189 void cpu_init_f(void)
190 {
191 mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */
192 mbar_writeByte(MCFSIM_SYPCR, 0x00);
193 mbar_writeByte(MCFSIM_SWIVR, 0x0f);
194 mbar_writeByte(MCFSIM_SWSR, 0x00);
195 mbar_writeByte(MCFSIM_SWDICR, 0x00);
196 mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
197 mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
198 mbar_writeByte(MCFSIM_I2CICR, 0x00);
199 mbar_writeByte(MCFSIM_UART1ICR, 0x00);
200 mbar_writeByte(MCFSIM_UART2ICR, 0x00);
201 mbar_writeByte(MCFSIM_ICR6, 0x00);
202 mbar_writeByte(MCFSIM_ICR7, 0x00);
203 mbar_writeByte(MCFSIM_ICR8, 0x00);
204 mbar_writeByte(MCFSIM_ICR9, 0x00);
205 mbar_writeByte(MCFSIM_QSPIICR, 0x00);
206
207 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
208 mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
209 mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
210
211 /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
212
213 /* FlexBus Chipselect */
214 init_fbcs();
215
216 #ifdef CONFIG_SYS_I2C_FSL
217 CONFIG_SYS_I2C_PINMUX_REG =
218 CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
219 CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
220 #ifdef CONFIG_SYS_I2C2_OFFSET
221 CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
222 CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET;
223 #endif
224 #endif
225
226 /* enable instruction cache now */
227 icache_enable();
228 }
229
230 /*initialize higher level parts of CPU like timers */
cpu_init_r(void)231 int cpu_init_r(void)
232 {
233 return (0);
234 }
235
uart_port_conf(int port)236 void uart_port_conf(int port)
237 {
238 u32 *par = (u32 *) MMAP_PAR;
239
240 /* Setup Ports: */
241 switch (port) {
242 case 1:
243 clrbits_be32(par, 0x00180000);
244 setbits_be32(par, 0x00180000);
245 break;
246 case 2:
247 clrbits_be32(par, 0x00000003);
248 clrbits_be32(par, 0xFFFFFFFC);
249 break;
250 }
251 }
252 #endif /* #if defined(CONFIG_M5253) */
253
254 #if defined(CONFIG_M5271)
cpu_init_f(void)255 void cpu_init_f(void)
256 {
257 #ifndef CONFIG_WATCHDOG
258 /* Disable the watchdog if we aren't using it */
259 mbar_writeShort(MCF_WTM_WCR, 0);
260 #endif
261
262 /* FlexBus Chipselect */
263 init_fbcs();
264
265 #ifdef CONFIG_SYS_MCF_SYNCR
266 /* Set clockspeed according to board header file */
267 mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR);
268 #else
269 /* Set clockspeed to 100MHz */
270 mbar_writeLong(MCF_FMPLL_SYNCR,
271 MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
272 #endif
273 while (!(mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK)) ;
274 }
275
276 /*
277 * initialize higher level parts of CPU like timers
278 */
cpu_init_r(void)279 int cpu_init_r(void)
280 {
281 return (0);
282 }
283
uart_port_conf(int port)284 void uart_port_conf(int port)
285 {
286 u16 temp;
287
288 /* Setup Ports: */
289 switch (port) {
290 case 0:
291 temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xFFF3;
292 temp |= (MCF_GPIO_PAR_UART_U0TXD | MCF_GPIO_PAR_UART_U0RXD);
293 mbar_writeShort(MCF_GPIO_PAR_UART, temp);
294 break;
295 case 1:
296 temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xF0FF;
297 temp |= (MCF_GPIO_PAR_UART_U1RXD_UART1 | MCF_GPIO_PAR_UART_U1TXD_UART1);
298 mbar_writeShort(MCF_GPIO_PAR_UART, temp);
299 break;
300 case 2:
301 temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xCFFF;
302 temp |= (0x3000);
303 mbar_writeShort(MCF_GPIO_PAR_UART, temp);
304 break;
305 }
306 }
307
308 #if defined(CONFIG_CMD_NET)
fecpin_setclear(fec_info_t * info,int setclear)309 int fecpin_setclear(fec_info_t *info, int setclear)
310 {
311 if (setclear) {
312 /* Enable Ethernet pins */
313 mbar_writeByte(MCF_GPIO_PAR_FECI2C,
314 (mbar_readByte(MCF_GPIO_PAR_FECI2C) | 0xF0));
315 } else {
316 }
317
318 return 0;
319 }
320 #endif /* CONFIG_CMD_NET */
321
322 #endif /* CONFIG_M5271 */
323
324 #if defined(CONFIG_M5272)
325 /*
326 * Breath some life into the CPU...
327 *
328 * Set up the memory map,
329 * initialize a bunch of registers,
330 * initialize the UPM's
331 */
cpu_init_f(void)332 void cpu_init_f(void)
333 {
334 /* if we come from RAM we assume the CPU is
335 * already initialized.
336 */
337 #ifndef CONFIG_MONITOR_IS_IN_RAM
338 sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
339 gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
340 csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
341
342 out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR);
343 out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR);
344
345 /* Setup Ports: */
346 out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT);
347 out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR);
348 out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT);
349 out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT);
350 out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR);
351 out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT);
352 out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT);
353
354 /* Memory Controller: */
355 out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM);
356 out_be32(&csctrl->cs_or0, CONFIG_SYS_OR0_PRELIM);
357
358 #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
359 out_be32(&csctrl->cs_br1, CONFIG_SYS_BR1_PRELIM);
360 out_be32(&csctrl->cs_or1, CONFIG_SYS_OR1_PRELIM);
361 #endif
362
363 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
364 out_be32(&csctrl->cs_br2, CONFIG_SYS_BR2_PRELIM);
365 out_be32(&csctrl->cs_or2, CONFIG_SYS_OR2_PRELIM);
366 #endif
367
368 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
369 out_be32(&csctrl->cs_br3, CONFIG_SYS_BR3_PRELIM);
370 out_be32(&csctrl->cs_or3, CONFIG_SYS_OR3_PRELIM);
371 #endif
372
373 #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
374 out_be32(&csctrl->cs_br4, CONFIG_SYS_BR4_PRELIM);
375 out_be32(&csctrl->cs_or4, CONFIG_SYS_OR4_PRELIM);
376 #endif
377
378 #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
379 out_be32(&csctrl->cs_br5, CONFIG_SYS_BR5_PRELIM);
380 out_be32(&csctrl->cs_or5, CONFIG_SYS_OR5_PRELIM);
381 #endif
382
383 #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
384 out_be32(&csctrl->cs_br6, CONFIG_SYS_BR6_PRELIM);
385 out_be32(&csctrl->cs_or6, CONFIG_SYS_OR6_PRELIM);
386 #endif
387
388 #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
389 out_be32(&csctrl->cs_br7, CONFIG_SYS_BR7_PRELIM);
390 out_be32(&csctrl->cs_or7, CONFIG_SYS_OR7_PRELIM);
391 #endif
392
393 #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
394
395 /* enable instruction cache now */
396 icache_enable();
397
398 }
399
400 /*
401 * initialize higher level parts of CPU like timers
402 */
cpu_init_r(void)403 int cpu_init_r(void)
404 {
405 return (0);
406 }
407
uart_port_conf(int port)408 void uart_port_conf(int port)
409 {
410 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
411
412 /* Setup Ports: */
413 switch (port) {
414 case 0:
415 clrbits_be32(&gpio->gpio_pbcnt,
416 GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
417 setbits_be32(&gpio->gpio_pbcnt,
418 GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
419 break;
420 case 1:
421 clrbits_be32(&gpio->gpio_pdcnt,
422 GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
423 setbits_be32(&gpio->gpio_pdcnt,
424 GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
425 break;
426 }
427 }
428
429 #if defined(CONFIG_CMD_NET)
fecpin_setclear(fec_info_t * info,int setclear)430 int fecpin_setclear(fec_info_t *info, int setclear)
431 {
432 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
433
434 if (setclear) {
435 setbits_be32(&gpio->gpio_pbcnt,
436 GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
437 GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
438 GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
439 GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3);
440 } else {
441 }
442 return 0;
443 }
444 #endif /* CONFIG_CMD_NET */
445 #endif /* #if defined(CONFIG_M5272) */
446
447 #if defined(CONFIG_M5275)
448
449 /*
450 * Breathe some life into the CPU...
451 *
452 * Set up the memory map,
453 * initialize a bunch of registers,
454 * initialize the UPM's
455 */
cpu_init_f(void)456 void cpu_init_f(void)
457 {
458 /*
459 * if we come from RAM we assume the CPU is
460 * already initialized.
461 */
462
463 #ifndef CONFIG_MONITOR_IS_IN_RAM
464 wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
465 gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
466
467 /* Kill watchdog so we can initialize the PLL */
468 out_be16(&wdog_reg->wcr, 0);
469
470 /* FlexBus Chipselect */
471 init_fbcs();
472 #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
473
474 #ifdef CONFIG_SYS_I2C_FSL
475 CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
476 CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
477 #endif
478
479 /* enable instruction cache now */
480 icache_enable();
481 }
482
483 /*
484 * initialize higher level parts of CPU like timers
485 */
cpu_init_r(void)486 int cpu_init_r(void)
487 {
488 return (0);
489 }
490
uart_port_conf(int port)491 void uart_port_conf(int port)
492 {
493 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
494
495 /* Setup Ports: */
496 switch (port) {
497 case 0:
498 clrbits_be16(&gpio->par_uart, UART0_ENABLE_MASK);
499 setbits_be16(&gpio->par_uart, UART0_ENABLE_MASK);
500 break;
501 case 1:
502 clrbits_be16(&gpio->par_uart, UART1_ENABLE_MASK);
503 setbits_be16(&gpio->par_uart, UART1_ENABLE_MASK);
504 break;
505 case 2:
506 clrbits_be16(&gpio->par_uart, UART2_ENABLE_MASK);
507 setbits_be16(&gpio->par_uart, UART2_ENABLE_MASK);
508 break;
509 }
510 }
511
512 #if defined(CONFIG_CMD_NET)
fecpin_setclear(fec_info_t * info,int setclear)513 int fecpin_setclear(fec_info_t *info, int setclear)
514 {
515 gpio_t *gpio = (gpio_t *)MMAP_GPIO;
516 u32 fec0_base;
517
518 if (fec_get_base_addr(0, &fec0_base))
519 return -1;
520
521 if (setclear) {
522 /* Enable Ethernet pins */
523 if (info->iobase == fec0_base) {
524 setbits_be16(&gpio->par_feci2c, 0x0f00);
525 setbits_8(&gpio->par_fec0hl, 0xc0);
526 } else {
527 setbits_be16(&gpio->par_feci2c, 0x00a0);
528 setbits_8(&gpio->par_fec1hl, 0xc0);
529 }
530 } else {
531 if (info->iobase == fec0_base) {
532 clrbits_be16(&gpio->par_feci2c, 0x0f00);
533 clrbits_8(&gpio->par_fec0hl, 0xc0);
534 } else {
535 clrbits_be16(&gpio->par_feci2c, 0x00a0);
536 clrbits_8(&gpio->par_fec1hl, 0xc0);
537 }
538 }
539
540 return 0;
541 }
542 #endif /* CONFIG_CMD_NET */
543 #endif /* #if defined(CONFIG_M5275) */
544
545 #if defined(CONFIG_M5282)
546 /*
547 * Breath some life into the CPU...
548 *
549 * Set up the memory map,
550 * initialize a bunch of registers,
551 * initialize the UPM's
552 */
cpu_init_f(void)553 void cpu_init_f(void)
554 {
555 #ifndef CONFIG_WATCHDOG
556 /* disable watchdog if we aren't using it */
557 MCFWTM_WCR = 0;
558 #endif
559
560 #ifndef CONFIG_MONITOR_IS_IN_RAM
561 /* Set speed /PLL */
562 MCFCLOCK_SYNCR =
563 MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
564 MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
565 while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
566
567 MCFGPIO_PBCDPAR = 0xc0;
568
569 /* Set up the GPIO ports */
570 #ifdef CONFIG_SYS_PEPAR
571 MCFGPIO_PEPAR = CONFIG_SYS_PEPAR;
572 #endif
573 #ifdef CONFIG_SYS_PFPAR
574 MCFGPIO_PFPAR = CONFIG_SYS_PFPAR;
575 #endif
576 #ifdef CONFIG_SYS_PJPAR
577 MCFGPIO_PJPAR = CONFIG_SYS_PJPAR;
578 #endif
579 #ifdef CONFIG_SYS_PSDPAR
580 MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR;
581 #endif
582 #ifdef CONFIG_SYS_PASPAR
583 MCFGPIO_PASPAR = CONFIG_SYS_PASPAR;
584 #endif
585 #ifdef CONFIG_SYS_PEHLPAR
586 MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
587 #endif
588 #ifdef CONFIG_SYS_PQSPAR
589 MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR;
590 #endif
591 #ifdef CONFIG_SYS_PTCPAR
592 MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR;
593 #endif
594 #if defined(CONFIG_SYS_PORTTC)
595 MCFGPIO_PORTTC = CONFIG_SYS_PORTTC;
596 #endif
597 #if defined(CONFIG_SYS_DDRTC)
598 MCFGPIO_DDRTC = CONFIG_SYS_DDRTC;
599 #endif
600 #ifdef CONFIG_SYS_PTDPAR
601 MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
602 #endif
603 #ifdef CONFIG_SYS_PUAPAR
604 MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
605 #endif
606
607 #if defined(CONFIG_SYS_DDRD)
608 MCFGPIO_DDRD = CONFIG_SYS_DDRD;
609 #endif
610 #ifdef CONFIG_SYS_DDRUA
611 MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
612 #endif
613
614 /* FlexBus Chipselect */
615 init_fbcs();
616
617 #endif /* CONFIG_MONITOR_IS_IN_RAM */
618
619 /* defer enabling cache until boot (see do_go) */
620 /* icache_enable(); */
621 }
622
623 /*
624 * initialize higher level parts of CPU like timers
625 */
cpu_init_r(void)626 int cpu_init_r(void)
627 {
628 return (0);
629 }
630
uart_port_conf(int port)631 void uart_port_conf(int port)
632 {
633 /* Setup Ports: */
634 switch (port) {
635 case 0:
636 MCFGPIO_PUAPAR &= 0xFc;
637 MCFGPIO_PUAPAR |= 0x03;
638 break;
639 case 1:
640 MCFGPIO_PUAPAR &= 0xF3;
641 MCFGPIO_PUAPAR |= 0x0C;
642 break;
643 case 2:
644 MCFGPIO_PASPAR &= 0xFF0F;
645 MCFGPIO_PASPAR |= 0x00A0;
646 break;
647 }
648 }
649
650 #if defined(CONFIG_CMD_NET)
fecpin_setclear(fec_info_t * info,int setclear)651 int fecpin_setclear(fec_info_t *info, int setclear)
652 {
653 if (setclear) {
654 MCFGPIO_PASPAR |= 0x0F00;
655 MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
656 } else {
657 MCFGPIO_PASPAR &= 0xF0FF;
658 MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
659 }
660 return 0;
661 }
662 #endif /* CONFIG_CMD_NET */
663 #endif
664
665 #if defined(CONFIG_M5249)
666 /*
667 * Breath some life into the CPU...
668 *
669 * Set up the memory map,
670 * initialize a bunch of registers,
671 * initialize the UPM's
672 */
cpu_init_f(void)673 void cpu_init_f(void)
674 {
675 /*
676 * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
677 * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
678 * which is their primary function.
679 * ~Jeremy
680 */
681 mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC);
682 mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC);
683 mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN);
684 mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN);
685 mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT);
686 mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT);
687
688 /*
689 * dBug Compliance:
690 * You can verify these values by using dBug's 'ird'
691 * (Internal Register Display) command
692 * ~Jeremy
693 *
694 */
695 mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */
696 mbar_writeByte(MCFSIM_SYPCR, 0x00);
697 mbar_writeByte(MCFSIM_SWIVR, 0x0f);
698 mbar_writeByte(MCFSIM_SWSR, 0x00);
699 mbar_writeLong(MCFSIM_IMR, 0xfffffbff);
700 mbar_writeByte(MCFSIM_SWDICR, 0x00);
701 mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
702 mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
703 mbar_writeByte(MCFSIM_I2CICR, 0x00);
704 mbar_writeByte(MCFSIM_UART1ICR, 0x00);
705 mbar_writeByte(MCFSIM_UART2ICR, 0x00);
706 mbar_writeByte(MCFSIM_ICR6, 0x00);
707 mbar_writeByte(MCFSIM_ICR7, 0x00);
708 mbar_writeByte(MCFSIM_ICR8, 0x00);
709 mbar_writeByte(MCFSIM_ICR9, 0x00);
710 mbar_writeByte(MCFSIM_QSPIICR, 0x00);
711
712 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
713 mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
714 mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
715 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
716
717 /* Setup interrupt priorities for gpio7 */
718 /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
719
720 /* IDE Config registers */
721 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
722 mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
723
724 /* FlexBus Chipselect */
725 init_fbcs();
726
727 /* enable instruction cache now */
728 icache_enable();
729 }
730
731 /*
732 * initialize higher level parts of CPU like timers
733 */
cpu_init_r(void)734 int cpu_init_r(void)
735 {
736 return (0);
737 }
738
uart_port_conf(int port)739 void uart_port_conf(int port)
740 {
741 }
742 #endif /* #if defined(CONFIG_M5249) */
743