1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019 Marvell International Ltd.
4 */
5
6#include "cn9130.dtsi" /* include SoC device tree */
7
8/ {
9	model = "CN9130-CRB";
10	compatible = "marvell,cn9130-crb",
11		"marvell,cn9130",
12		"marvell,armada-ap806-quad",
13		"marvell,armada-ap806";
14	chosen {
15		stdout-path = "serial0:115200n8";
16	};
17
18	aliases {
19		i2c0 = &cp0_i2c0;
20		spi0 = &cp0_spi1;
21		gpio0 = &ap_gpio0;
22		gpio1 = &cp0_gpio0;
23		gpio2 = &cp0_gpio1;
24	};
25
26	memory@00000000 {
27		device_type = "memory";
28		reg = <0x0 0x0 0x0 0x80000000>;
29	};
30
31	cp0 {
32		config-space {
33			sdhci@780000 {
34				vqmmc-supply = <&cp0_reg_sd_vccq>;
35				vmmc-supply = <&cp0_reg_sd_vcc>;
36			};
37			cp0_reg_sd_vccq: cp0_sd_vccq@0 {
38				compatible = "regulator-gpio";
39				regulator-name = "cp0_sd_vccq";
40				regulator-min-microvolt = <1800000>;
41				regulator-max-microvolt = <3300000>;
42				gpios = <&cp0_gpio1 18 GPIO_ACTIVE_HIGH>;
43				states = <1800000 0x1
44					  3300000 0x0>;
45			};
46			cp0_reg_sd_vcc: cp0_sd_vcc@0 {
47				compatible = "regulator-fixed";
48				regulator-name = "cp0_sd_vcc";
49				regulator-min-microvolt = <3300000>;
50				regulator-max-microvolt = <3300000>;
51				gpio = <&cp0_gpio1 22 GPIO_ACTIVE_HIGH>;
52				enable-active-high;
53				regulator-always-on;
54			};
55		};
56	};
57};
58
59&uart0 {
60	status = "okay";
61};
62
63/*
64 * AP related configuration
65 */
66&ap_pinctl {
67	/* MPP Bus:
68	 * SDIO  [0-10, 12]
69	 * UART0 [11,19]
70	 */
71		/*   0 1 2 3 4 5 6 7 8 9 */
72	pin-func = < 1 1 1 1 1 1 1 1 1 1
73		     1 3 1 0 0 0 0 0 0 3 >;
74};
75
76/* on-board eMMC - U6 */
77&ap_sdhci0 {
78	pinctrl-names = "default";
79	pinctrl-0 = <&ap_emmc_pins>;
80	bus-width = <8>;
81	status = "okay";
82};
83
84/*
85 * CP related configuration
86 */
87&cp0_pinctl {
88	/* MPP Bus:
89	 *	[0-11]	RGMII1
90	 *	[12] GPIO
91	 *	[13-16] SPI1
92	 *	[17-32] GPIO
93	 *	[33]	SD_PWR_OFF
94	 *	[34]	CP_PCIE0_CLKREQn
95	 *	[35-38]	I2C1 I2C0
96	 *	[39]	GPIO
97	 *	[40-43]	SMI/XSMI
98	 *	[44-46]	GPIO
99	 *	[47]	UART1_TX
100	 *	[48]	GPIO
101	 *	[49]	SD_HST_18_EN
102	 *	[50]	GPIO
103	 *	[51]	SD_PWR_0
104	 *	[52]	PCIE_RSTn
105	 *	[53]	UART1_RX
106	 *	[54]	GPIO
107	 *	[55]	SD_DT
108	 *	[56-61]	SDIO
109	 *
110	 * Note that CRB board revisions have different MPP configurations.
111	 * r1p2 has SPI flash on MPP[30:27] and r1p3.1, which is the latest
112	 * board revision, has it mapped to MPP[16:13].
113	 */
114		/*   0   1   2   3   4   5   6   7   8   9 */
115	pin-func = < 3   3   3   3   3   3   3   3   3   3
116		     3   3   0   3   3   3   3   0   0   0
117		     0   0   0   0   0   0   0   0   0   0
118		     0   0   0   6   9   2   2   2   2   0
119		     8   8   8   8   0   0   0   7   0   0xa
120		     0   0xa 9   7   0   0xb 0xe 0xe 0xe 0xe
121		     0xe 0xe 0xe>;
122
123	cp0_sdhci_cd_pins_crb: cp0-sdhci-cd-pins-crb {
124		marvell,pins = < 55 >;
125		marvell,function = <0>;
126	};
127
128	cp0_spi1_pins_crb: cp0-spi-pins-crb {
129		marvell,pins = < 13 14 15 16 >;
130		marvell,function = <3>;
131	};
132
133	cp0_smi_pins_crb: cp0-smi-pins-crb {
134		marvell,pins = < 40 41 >;
135		marvell,function = <8>;
136	};
137
138	cp0_xsmi_pins_crb: cp0-xsmi-pins-crb {
139		marvell,pins = < 42 43 >;
140		marvell,function = <8>;
141	};
142
143};
144
145/*
146 * CP0
147 */
148&cp0_i2c0 {
149	pinctrl-names = "default";
150	pinctrl-0 = <&cp0_i2c0_pins>;
151	status = "okay";
152	clock-frequency = <100000>;
153};
154
155&cp0_i2c1 {
156	pinctrl-names = "default";
157	pinctrl-0 = <&cp0_i2c1_pins>;
158	status = "okay";
159};
160
161&cp0_sdhci0 {
162	pinctrl-names = "default";
163	pinctrl-0 = <&cp0_sdhci_pins
164		     &cp0_sdhci_cd_pins_crb>;
165	bus-width = <4>;
166	vqmmc-supply = <&cp0_reg_sd_vccq>;
167	vmmc-supply = <&cp0_reg_sd_vcc>;
168	status = "okay";
169};
170
171&cp0_spi1 {
172	pinctrl-names = "default";
173	pinctrl-0 = <&cp0_spi1_pins_crb>;
174	reg = <0x700680 0x50>,		/* control */
175	      <0x2000000 0x1000000>,	/* CS0 */
176	      <0 0xffffffff>,		/* CS1 */
177	      <0 0xffffffff>,		/* CS2 */
178	      <0 0xffffffff>;		/* CS3 */
179	status = "okay";
180
181	spi-flash@0 {
182		#address-cells = <0x1>;
183		#size-cells = <0x1>;
184		compatible = "jedec,spi-nor", "spi-flash";
185		reg = <0x0>;
186		/* On-board MUX does not allow higher frequencies */
187		spi-max-frequency = <40000000>;
188
189		partitions {
190			compatible = "fixed-partitions";
191			#address-cells = <1>;
192			#size-cells = <1>;
193
194			partition@0 {
195				label = "U-Boot";
196				reg = <0x0 0x200000>;
197			};
198
199			partition@400000 {
200				label = "Filesystem";
201				reg = <0x200000 0xe00000>;
202			};
203		};
204	};
205};
206
207&cp0_utmi0 {
208	status = "okay";
209};
210
211&cp0_utmi1 {
212	status = "okay";
213};
214
215&cp0_mdio {
216	pinctrl-names = "default";
217	pinctrl-0 = <&cp0_smi_pins_crb>;
218	status = "okay";
219	phy0: ethernet-phy@0 {
220		reg = <0>;
221	};
222	switch6: ethernet-switch@6 {
223		reg = <6>;
224	};
225};
226
227&cp0_xmdio {
228	pinctrl-names = "default";
229	pinctrl-0 = <&cp0_xsmi_pins_crb>;
230	status = "okay";
231	nbaset_phy0: ethernet-phy@0 {
232		reg = <0>;
233	};
234};
235
236&cp0_ethernet {
237	status = "okay";
238};
239
240&cp0_eth0 {
241	status = "okay";
242	phy-mode = "sfi";
243};
244
245&cp0_eth1 {
246	status = "okay";
247	pinctrl-names = "default";
248	pinctrl-0 = <&cp0_ge1_rgmii_pins>;
249	phy = <&phy0>;
250	phy-mode = "rgmii-id";
251};
252
253&cp0_eth2 {
254	/* Disable it for now, as mainline does not support this IF yet */
255	status = "disabled";
256	phy = <&nbaset_phy0>;
257};
258