1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018-2021 Marvell International Ltd.
4 */
5
6#include "cn9130-db.dtsi"
7
8/ {
9	model = "Marvell CN9130 development board (CP NAND) setup(B)";
10};
11
12/*
13 * CP related configuration
14 */
15&cp0_pinctl {
16	/* MPP Bus:
17	 *	[0-11]	RGMII1
18	 *	[12]	GPIO GE-IN
19	 *	[13-14]	SPI1
20	 *	[15-27]	NAND
21	 *	[28]	MSS_GPIO[5] XXX:(mode nr from a3900)
22	 *	[29-30]	SATA
23	 *	[31]	MSS_GPIO[4] XXX:(mode nr from a3900)
24	 *	[32,34]	SMI
25	 *	[33]	SDIO
26	 *	[35-36]	I2C1
27	 *	[37-38]	I2C0
28	 *	[39-43]	SDIOctrl
29	 *	[44-55]	RGMII2
30	 *	[56-62]	SDIO
31	 */
32
33		/*   0   1   2   3   4   5   6   7   8   9 */
34	pin-func = < 3   3   3   3   3   3   3   3   3   3
35		     3   3   0   2   3   1   1   1   1   1
36		     1   1   1   1   1   1   1   1   3   9
37		     9   3   7   6   7   2   2   2   2   1
38		     1   1   1   1   1   1   1   1   1   1
39		     1   1   1   1   1   1   0xe 0xe 0xe 0xe
40		     0xe 0xe 0xe>;
41};
42
43/* U54 */
44&cp0_nand {
45	status = "okay";
46};
47
48/* U55 */
49&cp0_spi1 {
50	status = "disabled";
51};
52