1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * NXP LS1028A-QDS device tree fragment for RCW x3xx
4 *
5 * Copyright 2019-2021 NXP Semiconductors
6 */
7
8/*
9 * This setup is using a SCH-30841-R card with AQR412 quad PHY in slot 2.  This
10 * is used for the 4 integrated ethernet switch in a multiplexes USXGMII set-up.
11 *
12 * We're including the normal .dsti file, not the reworked card .dtsi
13 * intentionally.  We are using multiplexing of the 4 interfaces on a single
14 * lane and the rework doesn't actually disable any port.  The rework is in fact
15 * needed, otherwise the PHY won't work with the default wiring on the QDS/PHY
16 * card.
17 */
18&slot2 {
19#include "fsl-sch-30841.dtsi"
20};
21
22&mscc_felix {
23	status = "okay";
24};
25
26&mscc_felix_port0 {
27	status = "okay";
28	phy-mode = "usxgmii";
29	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@00}>;
30};
31
32&mscc_felix_port1 {
33	status = "okay";
34	phy-mode = "usxgmii";
35	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@01}>;
36};
37
38&mscc_felix_port2 {
39	status = "okay";
40	phy-mode = "usxgmii";
41	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
42};
43
44&mscc_felix_port3 {
45	status = "okay";
46	phy-mode = "usxgmii";
47	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@03}>;
48};
49