1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * NXP ls1028ARDB device tree source
4 *
5 * Copyright 2019 NXP
6 *
7 */
8
9/dts-v1/;
10
11#include "fsl-ls1028a.dtsi"
12
13/ {
14	model = "NXP Layerscape 1028a RDB Board";
15	compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
16	aliases {
17		spi0 = &fspi;
18		ethernet0 = &enetc0;
19		ethernet1 = &enetc2;
20		ethernet2 = &mscc_felix_port0;
21		ethernet3 = &mscc_felix_port1;
22		ethernet4 = &mscc_felix_port2;
23		ethernet5 = &mscc_felix_port3;
24	};
25};
26
27&dspi0 {
28	status = "okay";
29};
30
31&dspi1 {
32	status = "okay";
33};
34
35&dspi2 {
36	status = "okay";
37};
38
39&esdhc0 {
40	status = "okay";
41};
42
43&esdhc1 {
44	status = "okay";
45	mmc-hs200-1_8v;
46};
47
48&fspi {
49	status = "okay";
50
51	mt35xu02g0: flash@0 {
52		#address-cells = <1>;
53		#size-cells = <1>;
54		compatible = "jedec,spi-nor";
55		spi-max-frequency = <50000000>;
56		reg = <0>;
57		spi-rx-bus-width = <8>;
58		spi-tx-bus-width = <1>;
59	};
60};
61
62&i2c0 {
63	status = "okay";
64	u-boot,dm-pre-reloc;
65
66	 i2c-mux@77 {
67
68		compatible = "nxp,pca9547";
69		reg = <0x77>;
70		#address-cells = <1>;
71		#size-cells = <0>;
72
73		i2c@3 {
74			#address-cells = <1>;
75			#size-cells = <0>;
76			reg = <0x3>;
77
78			rtc@51 {
79				compatible = "pcf2127-rtc";
80				reg = <0x51>;
81			};
82		};
83	};
84};
85
86&i2c1 {
87	status = "okay";
88};
89
90&i2c2 {
91	status = "okay";
92};
93
94&i2c3 {
95	status = "okay";
96};
97
98&i2c4 {
99	status = "okay";
100};
101
102&i2c5 {
103	status = "okay";
104};
105
106&i2c6 {
107	status = "okay";
108};
109
110&i2c7 {
111	status = "okay";
112};
113
114&sata {
115	status = "okay";
116};
117
118&serial0 {
119	status = "okay";
120};
121
122&serial1 {
123	status = "okay";
124};
125
126&usb1 {
127	status = "okay";
128};
129
130&usb2 {
131	status = "okay";
132};
133
134&enetc0 {
135	status = "okay";
136	phy-mode = "sgmii";
137	phy-handle = <&rdb_phy0>;
138};
139
140&enetc2 {
141	status = "okay";
142};
143
144&mscc_felix {
145	status = "okay";
146};
147
148&mscc_felix_port0 {
149	label = "swp0";
150	phy-handle = <&sw_phy0>;
151	phy-mode = "qsgmii";
152	status = "okay";
153};
154
155&mscc_felix_port1 {
156	label = "swp1";
157	phy-handle = <&sw_phy1>;
158	phy-mode = "qsgmii";
159	status = "okay";
160};
161
162&mscc_felix_port2 {
163	label = "swp2";
164	phy-handle = <&sw_phy2>;
165	phy-mode = "qsgmii";
166	status = "okay";
167};
168
169&mscc_felix_port3 {
170	label = "swp3";
171	phy-handle = <&sw_phy3>;
172	phy-mode = "qsgmii";
173	status = "okay";
174};
175
176&mscc_felix_port4 {
177	ethernet = <&enetc2>;
178	status = "okay";
179};
180
181&mdio0 {
182	status = "okay";
183	rdb_phy0: phy@2 {
184		reg = <2>;
185	};
186
187	/* VSC8514 QSGMII PHY */
188	sw_phy0: phy@10 {
189		reg = <0x10>;
190	};
191
192	sw_phy1: phy@11 {
193		reg = <0x11>;
194	};
195
196	sw_phy2: phy@12 {
197		reg = <0x12>;
198	};
199
200	sw_phy3: phy@13 {
201		reg = <0x13>;
202	};
203};
204