1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2011 Freescale Semiconductor, Inc.
4// Copyright 2011 Linaro Ltd.
5
6#include "imx51-pinfunc.h"
7#include <dt-bindings/clock/imx5-clock.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/input.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11
12/ {
13	#address-cells = <1>;
14	#size-cells = <1>;
15	/*
16	 * The decompressor and also some bootloaders rely on a
17	 * pre-existing /chosen node to be available to insert the
18	 * command line and merge other ATAGS info.
19	 */
20	chosen {};
21
22	aliases {
23		ethernet0 = &fec;
24		gpio0 = &gpio1;
25		gpio1 = &gpio2;
26		gpio2 = &gpio3;
27		gpio3 = &gpio4;
28		i2c0 = &i2c1;
29		i2c1 = &i2c2;
30		mmc0 = &esdhc1;
31		mmc1 = &esdhc2;
32		mmc2 = &esdhc3;
33		mmc3 = &esdhc4;
34		serial0 = &uart1;
35		serial1 = &uart2;
36		serial2 = &uart3;
37		spi0 = &ecspi1;
38		spi1 = &ecspi2;
39		spi2 = &cspi;
40	};
41
42	tzic: tz-interrupt-controller@e0000000 {
43		compatible = "fsl,imx51-tzic", "fsl,tzic";
44		interrupt-controller;
45		#interrupt-cells = <1>;
46		reg = <0xe0000000 0x4000>;
47	};
48
49	clocks {
50		ckil {
51			compatible = "fsl,imx-ckil", "fixed-clock";
52			#clock-cells = <0>;
53			clock-frequency = <32768>;
54		};
55
56		ckih1 {
57			compatible = "fsl,imx-ckih1", "fixed-clock";
58			#clock-cells = <0>;
59			clock-frequency = <0>;
60		};
61
62		ckih2 {
63			compatible = "fsl,imx-ckih2", "fixed-clock";
64			#clock-cells = <0>;
65			clock-frequency = <0>;
66		};
67
68		osc {
69			compatible = "fsl,imx-osc", "fixed-clock";
70			#clock-cells = <0>;
71			clock-frequency = <24000000>;
72		};
73	};
74
75	cpus {
76		#address-cells = <1>;
77		#size-cells = <0>;
78		cpu: cpu@0 {
79			device_type = "cpu";
80			compatible = "arm,cortex-a8";
81			reg = <0>;
82			clock-latency = <62500>;
83			clocks = <&clks IMX5_CLK_CPU_PODF>;
84			clock-names = "cpu";
85			operating-points = <
86				166000	1000000
87				600000	1050000
88				800000	1100000
89			>;
90			voltage-tolerance = <5>;
91		};
92	};
93
94	pmu: pmu {
95		compatible = "arm,cortex-a8-pmu";
96		interrupt-parent = <&tzic>;
97		interrupts = <77>;
98	};
99
100	usbphy0: usbphy0 {
101		compatible = "usb-nop-xceiv";
102		clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
103		clock-names = "main_clk";
104		#phy-cells = <0>;
105	};
106
107	capture-subsystem {
108		compatible = "fsl,imx-capture-subsystem";
109		ports = <&ipu_csi0>, <&ipu_csi1>;
110	};
111
112	display-subsystem {
113		compatible = "fsl,imx-display-subsystem";
114		ports = <&ipu_di0>, <&ipu_di1>;
115	};
116
117	soc {
118		#address-cells = <1>;
119		#size-cells = <1>;
120		compatible = "simple-bus";
121		interrupt-parent = <&tzic>;
122		ranges;
123
124		iram: sram@1ffe0000 {
125			compatible = "mmio-sram";
126			reg = <0x1ffe0000 0x20000>;
127		};
128
129		gpu: gpu@30000000 {
130			compatible = "amd,imageon-200.1", "amd,imageon";
131			reg = <0x30000000 0x20000>;
132			reg-names = "kgsl_3d0_reg_memory";
133			interrupts = <12>;
134			interrupt-names = "kgsl_3d0_irq";
135			clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
136			clock-names = "core_clk", "mem_iface_clk";
137		};
138
139		ipu: ipu@40000000 {
140			#address-cells = <1>;
141			#size-cells = <0>;
142			compatible = "fsl,imx51-ipu";
143			reg = <0x40000000 0x20000000>;
144			interrupts = <11 10>;
145			clocks = <&clks IMX5_CLK_IPU_GATE>,
146				 <&clks IMX5_CLK_IPU_DI0_GATE>,
147				 <&clks IMX5_CLK_IPU_DI1_GATE>;
148			clock-names = "bus", "di0", "di1";
149			resets = <&src 2>;
150
151			ipu_csi0: port@0 {
152				reg = <0>;
153			};
154
155			ipu_csi1: port@1 {
156				reg = <1>;
157			};
158
159			ipu_di0: port@2 {
160				reg = <2>;
161
162				ipu_di0_disp1: endpoint {
163				};
164			};
165
166			ipu_di1: port@3 {
167				reg = <3>;
168
169				ipu_di1_disp2: endpoint {
170				};
171			};
172		};
173
174		bus@70000000 { /* AIPS1 */
175			compatible = "fsl,aips-bus", "simple-bus";
176			#address-cells = <1>;
177			#size-cells = <1>;
178			reg = <0x70000000 0x10000000>;
179			ranges;
180
181			spba@70000000 {
182				compatible = "fsl,spba-bus", "simple-bus";
183				#address-cells = <1>;
184				#size-cells = <1>;
185				reg = <0x70000000 0x40000>;
186				ranges;
187
188				esdhc1: mmc@70004000 {
189					compatible = "fsl,imx51-esdhc";
190					reg = <0x70004000 0x4000>;
191					interrupts = <1>;
192					clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
193						 <&clks IMX5_CLK_DUMMY>,
194						 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
195					clock-names = "ipg", "ahb", "per";
196					status = "disabled";
197				};
198
199				esdhc2: mmc@70008000 {
200					compatible = "fsl,imx51-esdhc";
201					reg = <0x70008000 0x4000>;
202					interrupts = <2>;
203					clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
204						 <&clks IMX5_CLK_DUMMY>,
205						 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
206					clock-names = "ipg", "ahb", "per";
207					bus-width = <4>;
208					status = "disabled";
209				};
210
211				uart3: serial@7000c000 {
212					compatible = "fsl,imx51-uart", "fsl,imx21-uart";
213					reg = <0x7000c000 0x4000>;
214					interrupts = <33>;
215					clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
216						 <&clks IMX5_CLK_UART3_PER_GATE>;
217					clock-names = "ipg", "per";
218					status = "disabled";
219				};
220
221				ecspi1: spi@70010000 {
222					#address-cells = <1>;
223					#size-cells = <0>;
224					compatible = "fsl,imx51-ecspi";
225					reg = <0x70010000 0x4000>;
226					interrupts = <36>;
227					clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
228						 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
229					clock-names = "ipg", "per";
230					status = "disabled";
231				};
232
233				ssi2: ssi@70014000 {
234					#sound-dai-cells = <0>;
235					compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
236					reg = <0x70014000 0x4000>;
237					interrupts = <30>;
238					clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
239						 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
240					clock-names = "ipg", "baud";
241					dmas = <&sdma 24 1 0>,
242					       <&sdma 25 1 0>;
243					dma-names = "rx", "tx";
244					fsl,fifo-depth = <15>;
245					status = "disabled";
246				};
247
248				esdhc3: mmc@70020000 {
249					compatible = "fsl,imx51-esdhc";
250					reg = <0x70020000 0x4000>;
251					interrupts = <3>;
252					clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
253						 <&clks IMX5_CLK_DUMMY>,
254						 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
255					clock-names = "ipg", "ahb", "per";
256					bus-width = <4>;
257					status = "disabled";
258				};
259
260				esdhc4: mmc@70024000 {
261					compatible = "fsl,imx51-esdhc";
262					reg = <0x70024000 0x4000>;
263					interrupts = <4>;
264					clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
265						 <&clks IMX5_CLK_DUMMY>,
266						 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
267					clock-names = "ipg", "ahb", "per";
268					bus-width = <4>;
269					status = "disabled";
270				};
271			};
272
273			aipstz1: bridge@73f00000 {
274				compatible = "fsl,imx51-aipstz";
275				reg = <0x73f00000 0x60>;
276			};
277
278			usbotg: usb@73f80000 {
279				compatible = "fsl,imx51-usb", "fsl,imx27-usb";
280				reg = <0x73f80000 0x0200>;
281				interrupts = <18>;
282				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
283				fsl,usbmisc = <&usbmisc 0>;
284				fsl,usbphy = <&usbphy0>;
285				status = "disabled";
286			};
287
288			usbh1: usb@73f80200 {
289				compatible = "fsl,imx51-usb", "fsl,imx27-usb";
290				reg = <0x73f80200 0x0200>;
291				interrupts = <14>;
292				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
293				fsl,usbmisc = <&usbmisc 1>;
294				dr_mode = "host";
295				status = "disabled";
296			};
297
298			usbh2: usb@73f80400 {
299				compatible = "fsl,imx51-usb", "fsl,imx27-usb";
300				reg = <0x73f80400 0x0200>;
301				interrupts = <16>;
302				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
303				fsl,usbmisc = <&usbmisc 2>;
304				dr_mode = "host";
305				status = "disabled";
306			};
307
308			usbh3: usb@73f80600 {
309				compatible = "fsl,imx51-usb", "fsl,imx27-usb";
310				reg = <0x73f80600 0x0200>;
311				interrupts = <17>;
312				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
313				fsl,usbmisc = <&usbmisc 3>;
314				dr_mode = "host";
315				status = "disabled";
316			};
317
318			usbmisc: usbmisc@73f80800 {
319				#index-cells = <1>;
320				compatible = "fsl,imx51-usbmisc";
321				reg = <0x73f80800 0x200>;
322				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
323			};
324
325			gpio1: gpio@73f84000 {
326				compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
327				reg = <0x73f84000 0x4000>;
328				interrupts = <50 51>;
329				gpio-controller;
330				#gpio-cells = <2>;
331				interrupt-controller;
332				#interrupt-cells = <2>;
333			};
334
335			gpio2: gpio@73f88000 {
336				compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
337				reg = <0x73f88000 0x4000>;
338				interrupts = <52 53>;
339				gpio-controller;
340				#gpio-cells = <2>;
341				interrupt-controller;
342				#interrupt-cells = <2>;
343			};
344
345			gpio3: gpio@73f8c000 {
346				compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
347				reg = <0x73f8c000 0x4000>;
348				interrupts = <54 55>;
349				gpio-controller;
350				#gpio-cells = <2>;
351				interrupt-controller;
352				#interrupt-cells = <2>;
353			};
354
355			gpio4: gpio@73f90000 {
356				compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
357				reg = <0x73f90000 0x4000>;
358				interrupts = <56 57>;
359				gpio-controller;
360				#gpio-cells = <2>;
361				interrupt-controller;
362				#interrupt-cells = <2>;
363			};
364
365			kpp: kpp@73f94000 {
366				compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
367				reg = <0x73f94000 0x4000>;
368				interrupts = <60>;
369				clocks = <&clks IMX5_CLK_DUMMY>;
370				status = "disabled";
371			};
372
373			wdog1: watchdog@73f98000 {
374				compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
375				reg = <0x73f98000 0x4000>;
376				interrupts = <58>;
377				clocks = <&clks IMX5_CLK_DUMMY>;
378			};
379
380			wdog2: watchdog@73f9c000 {
381				compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
382				reg = <0x73f9c000 0x4000>;
383				interrupts = <59>;
384				clocks = <&clks IMX5_CLK_DUMMY>;
385				status = "disabled";
386			};
387
388			gpt: timer@73fa0000 {
389				compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
390				reg = <0x73fa0000 0x4000>;
391				interrupts = <39>;
392				clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
393					 <&clks IMX5_CLK_GPT_HF_GATE>;
394				clock-names = "ipg", "per";
395			};
396
397			iomuxc: iomuxc@73fa8000 {
398				compatible = "fsl,imx51-iomuxc";
399				reg = <0x73fa8000 0x4000>;
400			};
401
402			pwm1: pwm@73fb4000 {
403				#pwm-cells = <3>;
404				compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
405				reg = <0x73fb4000 0x4000>;
406				clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
407					 <&clks IMX5_CLK_PWM1_HF_GATE>;
408				clock-names = "ipg", "per";
409				interrupts = <61>;
410			};
411
412			pwm2: pwm@73fb8000 {
413				#pwm-cells = <3>;
414				compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
415				reg = <0x73fb8000 0x4000>;
416				clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
417					 <&clks IMX5_CLK_PWM2_HF_GATE>;
418				clock-names = "ipg", "per";
419				interrupts = <94>;
420			};
421
422			uart1: serial@73fbc000 {
423				compatible = "fsl,imx51-uart", "fsl,imx21-uart";
424				reg = <0x73fbc000 0x4000>;
425				interrupts = <31>;
426				clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
427					 <&clks IMX5_CLK_UART1_PER_GATE>;
428				clock-names = "ipg", "per";
429				status = "disabled";
430			};
431
432			uart2: serial@73fc0000 {
433				compatible = "fsl,imx51-uart", "fsl,imx21-uart";
434				reg = <0x73fc0000 0x4000>;
435				interrupts = <32>;
436				clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
437					 <&clks IMX5_CLK_UART2_PER_GATE>;
438				clock-names = "ipg", "per";
439				status = "disabled";
440			};
441
442			src: reset-controller@73fd0000 {
443				compatible = "fsl,imx51-src";
444				reg = <0x73fd0000 0x4000>;
445				interrupts = <75>;
446				#reset-cells = <1>;
447			};
448
449			clks: ccm@73fd4000{
450				compatible = "fsl,imx51-ccm";
451				reg = <0x73fd4000 0x4000>;
452				interrupts = <0 71 0x04 0 72 0x04>;
453				#clock-cells = <1>;
454			};
455		};
456
457		bus@80000000 {	/* AIPS2 */
458			compatible = "fsl,aips-bus", "simple-bus";
459			#address-cells = <1>;
460			#size-cells = <1>;
461			reg = <0x80000000 0x10000000>;
462			ranges;
463
464			aipstz2: bridge@83f00000 {
465				compatible = "fsl,imx51-aipstz";
466				reg = <0x83f00000 0x60>;
467			};
468
469			iim: efuse@83f98000 {
470				compatible = "fsl,imx51-iim", "fsl,imx27-iim";
471				reg = <0x83f98000 0x4000>;
472				interrupts = <69>;
473				clocks = <&clks IMX5_CLK_IIM_GATE>;
474			};
475
476			tigerp: tigerp@83fa0000 {
477				compatible = "fsl,imx51-tigerp";
478				reg = <0x83fa0000 0x28>;
479			};
480
481			owire: owire@83fa4000 {
482				compatible = "fsl,imx51-owire", "fsl,imx21-owire";
483				reg = <0x83fa4000 0x4000>;
484				interrupts = <88>;
485				clocks = <&clks IMX5_CLK_OWIRE_GATE>;
486				status = "disabled";
487			};
488
489			ecspi2: spi@83fac000 {
490				#address-cells = <1>;
491				#size-cells = <0>;
492				compatible = "fsl,imx51-ecspi";
493				reg = <0x83fac000 0x4000>;
494				interrupts = <37>;
495				clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
496					 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
497				clock-names = "ipg", "per";
498				status = "disabled";
499			};
500
501			sdma: sdma@83fb0000 {
502				compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
503				reg = <0x83fb0000 0x4000>;
504				interrupts = <6>;
505				clocks = <&clks IMX5_CLK_SDMA_GATE>,
506					 <&clks IMX5_CLK_AHB>;
507				clock-names = "ipg", "ahb";
508				#dma-cells = <3>;
509				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
510			};
511
512			cspi: spi@83fc0000 {
513				#address-cells = <1>;
514				#size-cells = <0>;
515				compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
516				reg = <0x83fc0000 0x4000>;
517				interrupts = <38>;
518				clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
519					 <&clks IMX5_CLK_CSPI_IPG_GATE>;
520				clock-names = "ipg", "per";
521				status = "disabled";
522			};
523
524			i2c2: i2c@83fc4000 {
525				#address-cells = <1>;
526				#size-cells = <0>;
527				compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
528				reg = <0x83fc4000 0x4000>;
529				interrupts = <63>;
530				clocks = <&clks IMX5_CLK_I2C2_GATE>;
531				status = "disabled";
532			};
533
534			i2c1: i2c@83fc8000 {
535				#address-cells = <1>;
536				#size-cells = <0>;
537				compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
538				reg = <0x83fc8000 0x4000>;
539				interrupts = <62>;
540				clocks = <&clks IMX5_CLK_I2C1_GATE>;
541				status = "disabled";
542			};
543
544			ssi1: ssi@83fcc000 {
545				#sound-dai-cells = <0>;
546				compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
547				reg = <0x83fcc000 0x4000>;
548				interrupts = <29>;
549				clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
550					 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
551				clock-names = "ipg", "baud";
552				dmas = <&sdma 28 0 0>,
553				       <&sdma 29 0 0>;
554				dma-names = "rx", "tx";
555				fsl,fifo-depth = <15>;
556				status = "disabled";
557			};
558
559			audmux: audmux@83fd0000 {
560				compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
561				reg = <0x83fd0000 0x4000>;
562				clocks = <&clks IMX5_CLK_DUMMY>;
563				clock-names = "audmux";
564				status = "disabled";
565			};
566
567			m4if: m4if@83fd8000 {
568				compatible = "fsl,imx51-m4if";
569				reg = <0x83fd8000 0x1000>;
570			};
571
572			weim: weim@83fda000 {
573				#address-cells = <2>;
574				#size-cells = <1>;
575				compatible = "fsl,imx51-weim";
576				reg = <0x83fda000 0x1000>;
577				clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
578				ranges = <
579					0 0 0xb0000000 0x08000000
580					1 0 0xb8000000 0x08000000
581					2 0 0xc0000000 0x08000000
582					3 0 0xc8000000 0x04000000
583					4 0 0xcc000000 0x02000000
584					5 0 0xce000000 0x02000000
585				>;
586				status = "disabled";
587			};
588
589			nfc: nand@83fdb000 {
590				#address-cells = <1>;
591				#size-cells = <1>;
592				compatible = "fsl,imx51-nand";
593				reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
594				interrupts = <8>;
595				clocks = <&clks IMX5_CLK_NFC_GATE>;
596				status = "disabled";
597			};
598
599			pata: pata@83fe0000 {
600				compatible = "fsl,imx51-pata", "fsl,imx27-pata";
601				reg = <0x83fe0000 0x4000>;
602				interrupts = <70>;
603				clocks = <&clks IMX5_CLK_PATA_GATE>;
604				status = "disabled";
605			};
606
607			ssi3: ssi@83fe8000 {
608				#sound-dai-cells = <0>;
609				compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
610				reg = <0x83fe8000 0x4000>;
611				interrupts = <96>;
612				clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
613					 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
614				clock-names = "ipg", "baud";
615				dmas = <&sdma 46 0 0>,
616				       <&sdma 47 0 0>;
617				dma-names = "rx", "tx";
618				fsl,fifo-depth = <15>;
619				status = "disabled";
620			};
621
622			fec: ethernet@83fec000 {
623				compatible = "fsl,imx51-fec", "fsl,imx27-fec";
624				reg = <0x83fec000 0x4000>;
625				interrupts = <87>;
626				clocks = <&clks IMX5_CLK_FEC_GATE>,
627					 <&clks IMX5_CLK_FEC_GATE>,
628					 <&clks IMX5_CLK_FEC_GATE>;
629				clock-names = "ipg", "ahb", "ptp";
630				status = "disabled";
631			};
632
633			vpu: vpu@83ff4000 {
634				compatible = "fsl,imx51-vpu", "cnm,codahx4";
635				reg = <0x83ff4000 0x1000>;
636				interrupts = <9>;
637				clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
638					 <&clks IMX5_CLK_VPU_GATE>;
639				clock-names = "per", "ahb";
640				resets = <&src 1>;
641				iram = <&iram>;
642			};
643
644			sahara: crypto@83ff8000 {
645				compatible = "fsl,imx53-sahara", "fsl,imx51-sahara";
646				reg = <0x83ff8000 0x4000>;
647				interrupts = <19 20>;
648				clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
649					 <&clks IMX5_CLK_SAHARA_IPG_GATE>;
650				clock-names = "ipg", "ahb";
651			};
652		};
653	};
654};
655