1/* 2 * Copyright 2017 Gateworks Corporation 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public 20 * License along with this file; if not, write to the Free 21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 22 * MA 02110-1301 USA 23 * 24 * Or, alternatively, 25 * 26 * b) Permission is hereby granted, free of charge, to any person 27 * obtaining a copy of this software and associated documentation 28 * files (the "Software"), to deal in the Software without 29 * restriction, including without limitation the rights to use, 30 * copy, modify, merge, publish, distribute, sublicense, and/or 31 * sell copies of the Software, and to permit persons to whom the 32 * Software is furnished to do so, subject to the following 33 * conditions: 34 * 35 * The above copyright notice and this permission notice shall be 36 * included in all copies or substantial portions of the Software. 37 * 38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45 * OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48#include <dt-bindings/gpio/gpio.h> 49#include <dt-bindings/input/linux-event-codes.h> 50#include <dt-bindings/interrupt-controller/irq.h> 51 52/ { 53 chosen { 54 stdout-path = &uart2; 55 }; 56 57 backlight { 58 compatible = "pwm-backlight"; 59 pwms = <&pwm1 0 5000000>; 60 brightness-levels = < 61 0 1 2 3 4 5 6 7 8 9 62 10 11 12 13 14 15 16 17 18 19 63 20 21 22 23 24 25 26 27 28 29 64 30 31 32 33 34 35 36 37 38 39 65 40 41 42 43 44 45 46 47 48 49 66 50 51 52 53 54 55 56 57 58 59 67 60 61 62 63 64 65 66 67 68 69 68 70 71 72 73 74 75 76 77 78 79 69 80 81 82 83 84 85 86 87 88 89 70 90 91 92 93 94 95 96 97 98 99 71 100 72 >; 73 default-brightness-level = <100>; 74 }; 75 76 gpio-keys { 77 compatible = "gpio-keys"; 78 #address-cells = <1>; 79 #size-cells = <0>; 80 81 user-pb { 82 label = "user_pb"; 83 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 84 linux,code = <BTN_0>; 85 }; 86 87 user-pb1x { 88 label = "user_pb1x"; 89 linux,code = <BTN_1>; 90 interrupt-parent = <&gsc>; 91 interrupts = <0>; 92 }; 93 94 key-erased { 95 label = "key-erased"; 96 linux,code = <BTN_2>; 97 interrupt-parent = <&gsc>; 98 interrupts = <1>; 99 }; 100 101 eeprom-wp { 102 label = "eeprom_wp"; 103 linux,code = <BTN_3>; 104 interrupt-parent = <&gsc>; 105 interrupts = <2>; 106 }; 107 108 tamper { 109 label = "tamper"; 110 linux,code = <BTN_4>; 111 interrupt-parent = <&gsc>; 112 interrupts = <5>; 113 }; 114 115 switch-hold { 116 label = "switch_hold"; 117 linux,code = <BTN_5>; 118 interrupt-parent = <&gsc>; 119 interrupts = <7>; 120 }; 121 }; 122 123 leds { 124 compatible = "gpio-leds"; 125 pinctrl-names = "default"; 126 pinctrl-0 = <&pinctrl_gpio_leds>; 127 128 led0: user1 { 129 label = "user1"; 130 gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ 131 default-state = "off"; 132 }; 133 }; 134 135 memory@10000000 { 136 device_type = "memory"; 137 reg = <0x10000000 0x40000000>; 138 }; 139 140 reg_5p0v: regulator-5p0v { 141 compatible = "regulator-fixed"; 142 regulator-name = "5P0V"; 143 regulator-min-microvolt = <5000000>; 144 regulator-max-microvolt = <5000000>; 145 regulator-always-on; 146 }; 147 148 reg_3p3v: regulator-3p3v { 149 compatible = "regulator-fixed"; 150 regulator-name = "3P3V"; 151 regulator-min-microvolt = <3300000>; 152 regulator-max-microvolt = <3300000>; 153 regulator-always-on; 154 }; 155 156 reg_2p5v: regulator-2p5v { 157 compatible = "regulator-fixed"; 158 regulator-name = "2P5V"; 159 regulator-min-microvolt = <2500000>; 160 regulator-max-microvolt = <2500000>; 161 regulator-always-on; 162 }; 163 164 reg_usb_h1_vbus: regulator-usb-h1-vbus { 165 compatible = "regulator-fixed"; 166 regulator-name = "usb_h1_vbus"; 167 regulator-min-microvolt = <5000000>; 168 regulator-max-microvolt = <5000000>; 169 gpio = <&gpio3 30 0>; 170 enable-active-high; 171 }; 172 173 reg_usb_otg_vbus: regulator-usb-otg-vbus { 174 compatible = "regulator-fixed"; 175 regulator-name = "usb_otg_vbus"; 176 regulator-min-microvolt = <5000000>; 177 regulator-max-microvolt = <5000000>; 178 gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; 179 enable-active-high; 180 }; 181 182 reg_12p0: regulator-12p0v { 183 compatible = "regulator-fixed"; 184 regulator-name = "12P0V"; 185 regulator-min-microvolt = <12000000>; 186 regulator-max-microvolt = <12000000>; 187 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; 188 enable-active-high; 189 }; 190 191 sound { 192 compatible = "fsl,imx-audio-tlv320"; 193 model = "imx-tlv320"; 194 ssi-controller = <&ssi1>; 195 audio-codec = <&tlv320aic3105>; 196 /* routing of sink, source */ 197 audio-routing = 198 /* TLV320 LINE1L pin <-> Mic Jack connector */ 199 "LINE1L", "Mic Jack", 200 /* board Headphone Jack <-> HPOUT */ 201 "Headphone Jack", "HPLOUT", 202 "Headphone Jack", "HPROUT", 203 "Mic Jack", "Mic Bias"; 204 mux-int-port = <1>; 205 mux-ext-port = <6>; 206 }; 207}; 208 209&audmux { 210 pinctrl-names = "default"; 211 pinctrl-0 = <&pinctrl_audmux>; 212 status = "okay"; 213}; 214 215&clks { 216 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 217 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 218 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 219 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 220}; 221 222&fec { 223 pinctrl-names = "default"; 224 pinctrl-0 = <&pinctrl_enet>; 225 phy-mode = "rgmii-id"; 226 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; 227 phy-reset-duration = <10>; 228 phy-reset-post-delay = <100>; 229 status = "okay"; 230}; 231 232&i2c1 { 233 clock-frequency = <100000>; 234 pinctrl-names = "default"; 235 pinctrl-0 = <&pinctrl_i2c1>; 236 status = "okay"; 237 238 gsc: gsc@20 { 239 compatible = "gw,gsc"; 240 reg = <0x20>; 241 interrupt-parent = <&gpio1>; 242 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 243 interrupt-controller; 244 #interrupt-cells = <1>; 245 #size-cells = <0>; 246 247 adc { 248 compatible = "gw,gsc-adc"; 249 #address-cells = <1>; 250 #size-cells = <0>; 251 252 channel@0 { 253 gw,mode = <0>; 254 reg = <0x00>; 255 label = "temp"; 256 }; 257 258 channel@2 { 259 gw,mode = <1>; 260 reg = <0x02>; 261 label = "vdd_vin"; 262 }; 263 264 channel@5 { 265 gw,mode = <1>; 266 reg = <0x05>; 267 label = "vdd_3p3"; 268 }; 269 270 channel@8 { 271 gw,mode = <1>; 272 reg = <0x08>; 273 label = "vdd_bat"; 274 }; 275 276 channel@b { 277 gw,mode = <1>; 278 reg = <0x0b>; 279 label = "vdd_5p0"; 280 }; 281 282 channel@e { 283 gw,mode = <1>; 284 reg = <0xe>; 285 label = "vdd_arm"; 286 }; 287 288 channel@11 { 289 gw,mode = <1>; 290 reg = <0x11>; 291 label = "vdd_soc"; 292 }; 293 294 channel@14 { 295 gw,mode = <1>; 296 reg = <0x14>; 297 label = "vdd_3p0"; 298 }; 299 300 channel@17 { 301 gw,mode = <1>; 302 reg = <0x17>; 303 label = "vdd_1p5"; 304 }; 305 306 channel@1d { 307 gw,mode = <1>; 308 reg = <0x1d>; 309 label = "vdd_1p8"; 310 }; 311 312 channel@20 { 313 gw,mode = <1>; 314 reg = <0x20>; 315 label = "vdd_an1"; 316 }; 317 318 channel@23 { 319 gw,mode = <1>; 320 reg = <0x23>; 321 label = "vdd_2p5"; 322 }; 323 }; 324 }; 325 326 gsc_gpio: gpio@23 { 327 compatible = "nxp,pca9555"; 328 reg = <0x23>; 329 gpio-controller; 330 #gpio-cells = <2>; 331 interrupt-parent = <&gsc>; 332 interrupts = <4>; 333 }; 334 335 eeprom1: eeprom@50 { 336 compatible = "atmel,24c02"; 337 reg = <0x50>; 338 pagesize = <16>; 339 }; 340 341 eeprom2: eeprom@51 { 342 compatible = "atmel,24c02"; 343 reg = <0x51>; 344 pagesize = <16>; 345 }; 346 347 eeprom3: eeprom@52 { 348 compatible = "atmel,24c02"; 349 reg = <0x52>; 350 pagesize = <16>; 351 }; 352 353 eeprom4: eeprom@53 { 354 compatible = "atmel,24c02"; 355 reg = <0x53>; 356 pagesize = <16>; 357 }; 358 359 dts1672: rtc@68 { 360 compatible = "dallas,ds1672"; 361 reg = <0x68>; 362 }; 363}; 364 365&i2c2 { 366 clock-frequency = <400000>; 367 pinctrl-names = "default"; 368 pinctrl-0 = <&pinctrl_i2c2>; 369 status = "okay"; 370 371 ltc3676: pmic@3c { 372 compatible = "lltc,ltc3676"; 373 reg = <0x3c>; 374 interrupt-parent = <&gpio1>; 375 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 376 377 regulators { 378 /* VDD_1P8 (1+R1/R2 = 2.505): Aud/eMMC/microSD/Touch */ 379 reg_1p8v: sw1 { 380 regulator-name = "vdd1p8"; 381 regulator-min-microvolt = <1033310>; 382 regulator-max-microvolt = <2004000>; 383 lltc,fb-voltage-divider = <301000 200000>; 384 regulator-ramp-delay = <7000>; 385 regulator-boot-on; 386 regulator-always-on; 387 }; 388 389 /* VDD_DDR (1+R1/R2 = 2.105) */ 390 reg_vdd_ddr: sw2 { 391 regulator-name = "vddddr"; 392 regulator-min-microvolt = <868310>; 393 regulator-max-microvolt = <1684000>; 394 lltc,fb-voltage-divider = <221000 200000>; 395 regulator-ramp-delay = <7000>; 396 regulator-boot-on; 397 regulator-always-on; 398 }; 399 400 /* VDD_ARM (1+R1/R2 = 1.635) */ 401 reg_vdd_arm: sw3 { 402 regulator-name = "vddarm"; 403 regulator-min-microvolt = <674400>; 404 regulator-max-microvolt = <1308000>; 405 lltc,fb-voltage-divider = <127000 200000>; 406 regulator-ramp-delay = <7000>; 407 regulator-boot-on; 408 regulator-always-on; 409 linux,phandle = <®_vdd_arm>; 410 }; 411 412 /* VDD_SOC (1+R1/R2 = 1.635) */ 413 reg_vdd_soc: sw4 { 414 regulator-name = "vddsoc"; 415 regulator-min-microvolt = <674400>; 416 regulator-max-microvolt = <1308000>; 417 lltc,fb-voltage-divider = <127000 200000>; 418 regulator-ramp-delay = <7000>; 419 regulator-boot-on; 420 regulator-always-on; 421 linux,phandle = <®_vdd_soc>; 422 }; 423 424 /* VDD_1P0 (1+R1/R2 = 1.38): */ 425 reg_1p0v: ldo2 { 426 regulator-name = "vdd1p0"; 427 regulator-min-microvolt = <1002777>; 428 regulator-max-microvolt = <1002777>; 429 lltc,fb-voltage-divider = <100000 261000>; 430 regulator-boot-on; 431 regulator-always-on; 432 }; 433 434 /* VDD_HIGH (1+R1/R2 = 4.17) */ 435 reg_3p0v: ldo4 { 436 regulator-name = "vdd3p0"; 437 regulator-min-microvolt = <3023250>; 438 regulator-max-microvolt = <3023250>; 439 lltc,fb-voltage-divider = <634000 200000>; 440 regulator-boot-on; 441 regulator-always-on; 442 }; 443 }; 444 }; 445}; 446 447&i2c3 { 448 clock-frequency = <400000>; 449 pinctrl-names = "default"; 450 pinctrl-0 = <&pinctrl_i2c3>; 451 status = "okay"; 452 453 tlv320aic3105: codec@18 { 454 compatible = "ti,tlv320aic3x"; 455 reg = <0x18>; 456 reset-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; 457 clocks = <&clks IMX6QDL_CLK_CKO>; 458 ai3x-micbias-vg = <2>; /* MICBIAS_2_5V */ 459 /* Regulators */ 460 DRVDD-supply = <®_3p3v>; 461 AVDD-supply = <®_3p3v>; 462 IOVDD-supply = <®_3p3v>; 463 DVDD-supply = <®_1p8v>; 464 }; 465 466 accelerometer@1d { 467 compatible = "fsl,mma8451"; 468 reg = <0x1d>; 469 interrupt-parent = <&gpio7>; 470 interrupts = <11 IRQ_TYPE_EDGE_RISING>; 471 interrupt-names = "INT2"; 472 }; 473 474 /* headphone detect */ 475 ts3a227e@3b { 476 compatible = "ti,ts3a227e"; 477 reg = <0x3b>; 478 interrupt-parent = <&gpio5>; 479 interrupts = <15 IRQ_TYPE_LEVEL_LOW>; 480 ti,micbias = <4>; /* 2.5V micbias */ 481 }; 482}; 483 484&ldb { 485 status = "okay"; 486 487 lvds-channel@0 { 488 fsl,data-mapping = "spwg"; 489 fsl,data-width = <18>; 490 status = "okay"; 491 492 display-timings { 493 native-mode = <&timing0>; 494 timing0: g101evn010 { 495 clock-frequency = <68930000>; 496 hactive = <1280>; 497 vactive = <800>; 498 hback-porch = <220>; 499 hfront-porch = <40>; 500 vback-porch = <21>; 501 vfront-porch = <7>; 502 hsync-len = <60>; 503 vsync-len = <10>; 504 }; 505 }; 506 }; 507}; 508 509&pwm1 { 510 #pwm-cells = <2>; 511 pinctrl-names = "default"; 512 pinctrl-0 = <&pinctrl_pwm1>; 513 status = "okay"; 514}; 515 516&ssi1 { 517 status = "okay"; 518}; 519 520&uart1 { 521 pinctrl-names = "default"; 522 pinctrl-0 = <&pinctrl_uart1>; 523 status = "okay"; 524}; 525 526&uart2 { 527 pinctrl-names = "default"; 528 pinctrl-0 = <&pinctrl_uart2>; 529 status = "okay"; 530}; 531 532&usbotg { 533 vbus-supply = <®_usb_otg_vbus>; 534 pinctrl-names = "default"; 535 pinctrl-0 = <&pinctrl_usbotg>; 536 disable-over-current; 537 dr_mode = "host"; 538 status = "okay"; 539}; 540 541&usbh1 { 542 vbus-supply = <®_usb_h1_vbus>; 543 status = "okay"; 544}; 545 546&usdhc1 { 547 pinctrl-names = "default"; 548 pinctrl-0 = <&pinctrl_usdhc1_200mhz>; 549 vmmc-supply = <®_3p3v>; 550 non-removable; 551 bus-width = <4>; 552 status = "okay"; 553}; 554 555&usdhc2 { 556 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 557 pinctrl-0 = <&pinctrl_usdhc2>; 558 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 559 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 560 cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; 561 vmmc-supply = <®_3p3v>; 562 max-frequency = <100000000>; 563 status = "okay"; 564}; 565 566&usdhc3 { 567 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 568 pinctrl-0 = <&pinctrl_usdhc3>; 569 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 570 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 571 non-removable; 572 vmmc-supply = <®_3p3v>; 573 keep-power-in-suspend; 574 status = "okay"; 575}; 576 577&wdog1 { 578 pinctrl-names = "default"; 579 pinctrl-0 = <&pinctrl_wdog>; 580 fsl,ext-reset-output; 581}; 582 583&iomuxc { 584 pinctrl_audmux: audmuxgrp { 585 fsl,pins = < 586 MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0 587 MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 588 MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 589 MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 590 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* MCK */ 591 >; 592 }; 593 594 pinctrl_enet: enetgrp { 595 fsl,pins = < 596 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 597 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 598 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 599 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 600 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 601 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 602 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 603 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 604 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 605 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 606 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 607 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 608 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 609 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 610 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 611 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ 612 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 /* PHY_EN */ 613 >; 614 }; 615 616 pinctrl_gpio_leds: gpioledsgrp { 617 fsl,pins = < 618 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 619 >; 620 }; 621 622 pinctrl_i2c1: i2c1grp { 623 fsl,pins = < 624 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 625 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 626 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ 627 >; 628 }; 629 630 pinctrl_i2c2: i2c2grp { 631 fsl,pins = < 632 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 633 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 634 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 635 >; 636 }; 637 638 pinctrl_i2c3: i2c3grp { 639 fsl,pins = < 640 /* I2C3 */ 641 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 642 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 643 644 /* Headphone Detect */ 645 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x0001b0b0 /* HPDET_IRQ# */ 646 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x0001b0b0 /* HPDET_MIC# */ 647 648 /* Codec */ 649 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x0001b0b0 /* CODEC_RST# */ 650 651 /* Touch Controller */ 652 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* TOUCH_IRQ# */ 653 MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b0b0 /* TOUCH_RST */ 654 655 /* Stow Sensor */ 656 MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x0001b0b0 /* ACCEL_IRQ2 */ 657 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b0b0 /* ACCEL_IRQ1 */ 658 >; 659 }; 660 661 pinctrl_pwm1: pwm1grp { 662 fsl,pins = < 663 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 664 >; 665 }; 666 667 pinctrl_uart1: uart1grp { 668 fsl,pins = < 669 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 670 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 671 MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b1 /* TXEN */ 672 >; 673 }; 674 675 pinctrl_uart2: uart2grp { 676 fsl,pins = < 677 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 678 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 679 >; 680 }; 681 682 pinctrl_usbotg: usbotggrp { 683 fsl,pins = < 684 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 685 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x4001b0b0 /* PWR_EN */ 686 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ 687 >; 688 }; 689 690 pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 691 fsl,pins = < 692 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x4001b0b0 /* EMMY_EN */ 693 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x4001b0b0 /* EMMY_CFG1# */ 694 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x4001b0b0 /* EMMY_CFG2# */ 695 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0001b0b0 /* EMMY_BTWAKE# */ 696 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0001b0b0 /* EMMY_WFWAKE# */ 697 698 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 699 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x100f9 700 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 701 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 702 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 703 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 704 >; 705 }; 706 707 pinctrl_usdhc2: usdhc2grp { 708 fsl,pins = < 709 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 710 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 711 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 712 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 713 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 714 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 715 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x17059 /* CD */ 716 MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x17059 717 >; 718 }; 719 720 pinctrl_usdhc2_100mhz: usdhc2grp100mhz { 721 fsl,pins = < 722 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 723 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 724 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 725 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 726 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 727 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 728 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170b9 /* CD */ 729 MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170b9 730 >; 731 }; 732 733 pinctrl_usdhc2_200mhz: usdhc2grp200mhz { 734 fsl,pins = < 735 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 736 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 737 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 738 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 739 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 740 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 741 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170f9 /* CD */ 742 MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170f9 743 >; 744 }; 745 746 pinctrl_usdhc3: usdhc3grp { 747 fsl,pins = < 748 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 749 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 750 MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059 751 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 752 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 753 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 754 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 755 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 756 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 757 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 758 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 759 >; 760 }; 761 762 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 763 fsl,pins = < 764 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 765 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 766 MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9 767 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 768 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 769 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 770 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 771 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 772 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 773 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 774 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 775 >; 776 }; 777 778 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 779 fsl,pins = < 780 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 781 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 782 MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9 783 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 784 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 785 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 786 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 787 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 788 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 789 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 790 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 791 >; 792 }; 793 794 pinctrl_wdog: wdoggrp { 795 fsl,pins = < 796 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 797 >; 798 }; 799}; 800