1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2016 PHYTEC Messtechnik GmbH
4 * Author: Christian Hemp <c.hemp@phytec.de>
5 */
6
7/ {
8	model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite";
9	compatible = "phytec,imx6ul-pbacd-10", "phytec,imx6ul-pcl063", "fsl,imx6ul";
10
11	aliases {
12		rtc0 = &i2c_rtc;
13		rtc1 = &snvs_rtc;
14	};
15
16	reg_sound_1v8: regulator-1v8 {
17		compatible = "regulator-fixed";
18		regulator-name = "i2s-audio-1v8";
19		regulator-min-microvolt = <1800000>;
20		regulator-max-microvolt = <1800000>;
21		status = "disabled";
22	};
23
24	reg_sound_3v3: regulator-3v3 {
25		compatible = "regulator-fixed";
26		regulator-name = "i2s-audio-3v3";
27		regulator-min-microvolt = <3300000>;
28		regulator-max-microvolt = <3300000>;
29		status = "disabled";
30	};
31
32	reg_can1_en: regulator-can1 {
33		compatible = "regulator-fixed";
34		pinctrl-names = "default";
35		pinctrl-0 = <&princtrl_flexcan1_en>;
36		regulator-name = "Can";
37		regulator-min-microvolt = <3300000>;
38		regulator-max-microvolt = <3300000>;
39		gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
40		enable-active-high;
41		status = "disabled";
42	};
43
44	reg_adc1_vref_3v3: regulator-vref-3v3 {
45		compatible = "regulator-fixed";
46		regulator-name = "vref-3v3";
47		regulator-min-microvolt = <3300000>;
48		regulator-max-microvolt = <3300000>;
49	};
50
51	sound: sound {
52		compatible = "simple-audio-card";
53		simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007";
54		simple-audio-card,format = "i2s";
55		simple-audio-card,bitclock-master = <&dailink_master>;
56		simple-audio-card,frame-master = <&dailink_master>;
57		simple-audio-card,widgets =
58			"Line", "Line In",
59			"Line", "Line Out",
60			"Speaker", "Speaker";
61		simple-audio-card,routing =
62			"Line Out", "LLOUT",
63			"Line Out", "RLOUT",
64			"Speaker", "SPOP",
65			"Speaker", "SPOM",
66			"LINE1L", "Line In",
67			"LINE1R", "Line In";
68		status = "disabled";
69
70		simple-audio-card,cpu {
71			sound-dai = <&sai2>;
72		};
73
74		dailink_master: simple-audio-card,codec {
75			sound-dai = <&tlv320>;
76			clocks = <&clks IMX6UL_CLK_SAI2>;
77		};
78	};
79
80};
81
82&adc1 {
83	pinctrl-names = "default";
84	pinctrl-0 = <&pinctrl_adc1>;
85	vref-supply = <&reg_adc1_vref_3v3>;
86	/*
87	 * driver can not separate a specific channel so we request 4 channels
88	 * here - we need only the fourth channel
89	 */
90	num-channels = <4>;
91	status = "disabled";
92};
93
94&can1 {
95	pinctrl-names = "default";
96	pinctrl-0 = <&pinctrl_flexcan1>;
97	xceiver-supply = <&reg_can1_en>;
98	status = "disabled";
99};
100
101&clks {
102	assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
103	assigned-clock-rates = <786432000>;
104};
105
106&ecspi3 {
107	pinctrl-names = "default";
108	pinctrl-0 = <&pinctrl_ecspi3>;
109	cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
110	status = "disabled";
111};
112
113&fec2 {
114	pinctrl-names = "default";
115	pinctrl-0 = <&pinctrl_enet2>;
116	phy-mode = "rmii";
117	phy-handle = <&ethphy2>;
118	status = "disabled";
119};
120
121&i2c1 {
122	tlv320: codec@18 {
123		compatible = "ti,tlv320aic3007";
124		#sound-dai-cells = <0>;
125		reg = <0x18>;
126		AVDD-supply = <&reg_sound_3v3>;
127		IOVDD-supply = <&reg_sound_3v3>;
128		DRVDD-supply = <&reg_sound_3v3>;
129		DVDD-supply = <&reg_sound_1v8>;
130		status = "disabled";
131	};
132
133	stmpe: touchscreen@44 {
134		compatible = "st,stmpe811";
135		reg = <0x44>;
136		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
137		interrupt-parent = <&gpio5>;
138		pinctrl-names = "default";
139		pinctrl-0 = <&pinctrl_stmpe>;
140		status = "disabled";
141
142		touchscreen {
143			compatible = "st,stmpe-ts";
144			st,sample-time = <4>;
145			st,mod-12b = <1>;
146			st,ref-sel = <0>;
147			st,adc-freq = <1>;
148			st,ave-ctrl = <1>;
149			st,touch-det-delay = <2>;
150			st,settling = <2>;
151			st,fraction-z = <7>;
152			st,i-drive = <1>;
153			touchscreen-inverted-x = <1>;
154			touchscreen-inverted-y = <1>;
155		};
156	};
157
158	i2c_rtc: rtc@68 {
159		pinctrl-names = "default";
160		pinctrl-0 = <&pinctrl_rtc_int>;
161		compatible = "microcrystal,rv4162";
162		reg = <0x68>;
163		interrupt-parent = <&gpio5>;
164		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
165		status = "disabled";
166	};
167};
168
169&mdio {
170	ethphy2: ethernet-phy@2 {
171		reg = <2>;
172		micrel,led-mode = <1>;
173		clocks = <&clks IMX6UL_CLK_ENET2_REF>;
174		clock-names = "rmii-ref";
175		status = "disabled";
176	};
177};
178
179&pwm3 {
180	pinctrl-names = "default";
181	pinctrl-0 = <&pinctrl_pwm3>;
182	status = "disabled";
183};
184
185&sai2 {
186	pinctrl-names = "default";
187	pinctrl-0 = <&pinctrl_sai2>;
188	assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
189			<&clks IMX6UL_CLK_SAI2>;
190	assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
191	assigned-clock-rates = <0>, <19200000>;
192	fsl,sai-mclk-direction-output;
193	status = "disabled";
194};
195
196&uart5 {
197	pinctrl-names = "default";
198	pinctrl-0 = <&pinctrl_uart5>;
199	uart-has-rtscts;
200	status = "disabled";
201};
202
203&usbotg1 {
204	pinctrl-names = "default";
205	pinctrl-0 = <&pinctrl_usb_otg1_id>;
206	dr_mode = "otg";
207	status = "disabled";
208};
209
210&usbotg2 {
211	dr_mode = "host";
212	disable-over-current;
213	status = "disabled";
214};
215
216&usdhc1 {
217	pinctrl-names = "default", "state_100mhz", "state_200mhz";
218	pinctrl-0 = <&pinctrl_usdhc1>;
219	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
220	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
221	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
222	no-1-8-v;
223	keep-power-in-suspend;
224	wakeup-source;
225	status = "disabled";
226};
227
228&iomuxc {
229	pinctrl_adc1: adc1grp {
230		fsl,pins = <
231			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0xb0
232		>;
233	};
234
235	pinctrl_ecspi3: ecspi3grp {
236		fsl,pins = <
237			MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO	0x10b0
238			MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI	0x10b0
239			MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK	0x10b0
240			MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20	0x10b0
241		>;
242	};
243
244	pinctrl_enet2: enet2grp {
245		fsl,pins = <
246			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
247			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
248			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
249			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
250			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b010
251			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b010
252			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b010
253			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b010
254		>;
255	};
256
257	pinctrl_flexcan1: flexcan1 {
258		fsl,pins = <
259			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x0b0b0
260			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x0b0b0
261		>;
262	};
263
264	princtrl_flexcan1_en: flexcan1engrp {
265		fsl,pins = <
266			MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x17059
267		>;
268	};
269
270	pinctrl_pwm3: pwm3grp {
271		fsl,pins = <
272			MX6UL_PAD_GPIO1_IO04__PWM3_OUT	0x0b0b0
273		>;
274	};
275
276	pinctrl_rtc_int: rtcintgrp {
277		fsl,pins = <
278			MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x17059
279		>;
280	};
281
282	pinctrl_sai2: sai2grp {
283		fsl,pins = <
284			MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK	0x17088
285			MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC	0x17088
286			MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA	0x11088
287			MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA	0x11088
288			MX6UL_PAD_JTAG_TMS__SAI2_MCLK		0x17088
289		>;
290	};
291
292	pinctrl_stmpe: stmpegrp {
293		fsl,pins = <
294			MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03	0x17059
295		>;
296	};
297
298	pinctrl_uart5: uart5grp {
299		fsl,pins = <
300			MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX	0x1b0b1
301			MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX	0x1b0b1
302			MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS	0x1b0b1
303			MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS	0x1b0b1
304		>;
305	};
306
307	pinctrl_usb_otg1_id: usbotg1idgrp {
308		fsl,pins = <
309			MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID	0x17059
310		>;
311	};
312
313	pinctrl_usdhc1: usdhc1grp {
314		fsl,pins = <
315			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
316			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10059
317			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
318			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
319			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
320			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
321			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x17059
322		>;
323	};
324
325	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
326		fsl,pins = <
327			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170b9
328			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100b9
329			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170b9
330			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170b9
331			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170b9
332			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170b9
333		>;
334	};
335
336	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
337		fsl,pins = <
338			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170f9
339			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100f9
340			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170f9
341			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170f9
342			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170f9
343			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170f9
344		>;
345	};
346};
347