1/* 2 * Copyright 2015-2016 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9#include <dt-bindings/clock/imx7ulp-clock.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/gpio/gpio.h> 12#include "skeleton.dtsi" 13#include "imx7ulp-pinfunc.h" 14 15/ { 16 interrupt-parent = <&intc>; 17 18 aliases { 19 gpio0 = &gpio4; 20 gpio1 = &gpio5; 21 gpio2 = &gpio0; 22 gpio3 = &gpio1; 23 gpio4 = &gpio2; 24 gpio5 = &gpio3; 25 mmc0 = &usdhc0; 26 mmc1 = &usdhc1; 27 serial0 = &lpuart4; 28 serial1 = &lpuart5; 29 serial2 = &lpuart6; 30 serial3 = &lpuart7; 31 usbphy0 = &usbphy1; 32 usb0 = &usbotg1; 33 i2c4 = &lpi2c4; 34 i2c5 = &lpi2c5; 35 i2c6 = &lpi2c6; 36 i2c7 = &lpi2c7; 37 spi0 = &qspi1; 38 }; 39 40 cpus { 41 #address-cells = <1>; 42 #size-cells = <0>; 43 44 cpu0: cpu@0 { 45 compatible = "arm,cortex-a7"; 46 device_type = "cpu"; 47 reg = <0>; 48 }; 49 }; 50 51 reserved-memory { 52 #address-cells = <1>; 53 #size-cells = <1>; 54 ranges; 55 56 /* global autoconfigured region for contiguous allocations */ 57 linux,cma { 58 compatible = "shared-dma-pool"; 59 reusable; 60 size = <0xC000000>; 61 alignment = <0x2000>; 62 linux,cma-default; 63 }; 64 65 rpmsg_reserved: rpmsg@9FFF0000 { 66 no-map; 67 reg = <0x9FF00000 0x100000>; 68 }; 69 70 }; 71 72 intc: interrupt-controller@40021000 { 73 compatible = "arm,cortex-a7-gic"; 74 #interrupt-cells = <3>; 75 interrupt-controller; 76 reg = <0x40021000 0x1000>, 77 <0x40022000 0x100>; 78 }; 79 80 clocks { 81 #address-cells = <1>; 82 #size-cells = <0>; 83 84 ckil: clock@0 { 85 compatible = "fixed-clock"; 86 #clock-cells = <0>; 87 clock-frequency = <32768>; 88 clock-output-names = "ckil"; 89 }; 90 91 osc: clock@1 { 92 compatible = "fixed-clock"; 93 #clock-cells = <0>; 94 clock-frequency = <24000000>; 95 clock-output-names = "osc"; 96 }; 97 98 sirc: clock@2 { 99 compatible = "fixed-clock"; 100 #clock-cells = <0>; 101 clock-frequency = <16000000>; 102 clock-output-names = "sirc"; 103 }; 104 105 firc: clock@3 { 106 compatible = "fixed-clock"; 107 #clock-cells = <0>; 108 clock-frequency = <48000000>; 109 clock-output-names = "firc"; 110 }; 111 112 upll: clock@4 { 113 compatible = "fixed-clock"; 114 #clock-cells = <0>; 115 clock-frequency = <480000000>; 116 clock-output-names = "upll"; 117 }; 118 119 mpll: clock@5 { 120 compatible = "fixed-clock"; 121 #clock-cells = <0>; 122 clock-frequency = <480000000>; 123 clock-output-names = "mpll"; 124 }; 125 }; 126 127 sram: sram@20000000 { 128 compatible = "fsl,lpm-sram"; 129 reg = <0x1fffc000 0x4000>; 130 }; 131 132 ahbbridge0: ahb-bridge0@40000000 { 133 compatible = "fsl,aips-bus", "simple-bus"; 134 #address-cells = <1>; 135 #size-cells = <1>; 136 reg = <0x40000000 0x800000>; 137 ranges; 138 139 edma0: dma-controller@40080000 { 140 #dma-cells = <2>; 141 compatible = "nxp,imx7ulp-edma"; 142 reg = <0x40080000 0x2000>, 143 <0x40210000 0x1000>; 144 dma-channels = <32>; 145 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 162 clock-names = "dma", "dmamux0"; 163 clocks = <&clks IMX7ULP_CLK_DMA1>, <&clks IMX7ULP_CLK_DMA_MUX1>; 164 }; 165 166 mu: mu@40220000 { 167 compatible = "fsl,imx7ulp-mu", "fsl,imx6sx-mu"; 168 reg = <0x40220000 0x1000>; 169 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 171 status = "okay"; 172 }; 173 174 nmi: nmi@40220000 { 175 compatible = "fsl,imx7ulp-nmi"; 176 reg = <0x40220000 0x1000>; 177 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 178 status = "okay"; 179 }; 180 181 rpmsg: rpmsg{ 182 compatible = "fsl,imx7ulp-rpmsg"; 183 memory-region = <&rpmsg_reserved>; 184 status = "disabled"; 185 }; 186 187 snvs: snvs@40230000 { 188 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 189 reg = <0x40230000 0x10000>; 190 191 snvs_rtc: snvs-rtc-lp{ 192 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 193 regmap =<&snvs>; 194 offset = <0x34>; 195 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 196 clock-names = "snvs-rtc"; 197 clocks = <&clks IMX7ULP_CLK_SNVS>; 198 }; 199 }; 200 201 tpm5: tpm@40260000 { 202 compatible = "fsl,imx7ulp-tpm"; 203 reg = <0x40260000 0x1000>; 204 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&clks IMX7ULP_CLK_LPTPM5>; 206 }; 207 208 lpit: 1@40270000 { 209 compatible = "fsl,imx-lpit"; 210 reg = <0x40270000 0x1000>; 211 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 212 /* clocks = <&lpclk>;*/ 213 clocks = <&clks IMX7ULP_CLK_LPIT1>; 214 assigned-clock-rates = <48000000>; 215 assigned-clocks = <&clks IMX7ULP_CLK_LPIT1>; 216 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; 217 }; 218 219 lpi2c4: lpi2c4@402B0000 { 220 compatible = "fsl,imx7ulp-lpi2c"; 221 reg = <0x402B0000 0x10000>; 222 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 223 clocks = <&clks IMX7ULP_CLK_LPI2C4>; 224 clock-names = "ipg"; 225 assigned-clocks = <&clks IMX7ULP_CLK_LPI2C4>; 226 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; 227 assigned-clock-rates = <48000000>; 228 status = "disabled"; 229 }; 230 231 lpi2c5: lpi2c4@402C0000 { 232 compatible = "fsl,imx7ulp-lpi2c"; 233 reg = <0x402C0000 0x10000>; 234 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 235 clocks = <&clks IMX7ULP_CLK_LPI2C5>; 236 clock-names = "ipg"; 237 assigned-clocks = <&clks IMX7ULP_CLK_LPI2C5>; 238 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; 239 assigned-clock-rates = <48000000>; 240 status = "disabled"; 241 }; 242 243 lpspi2: lpspi@40290000 { 244 compatible = "fsl,imx7ulp-spi"; 245 reg = <0x40290000 0x10000>; 246 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 247 clocks = <&clks IMX7ULP_CLK_LPSPI2>; 248 clock-names = "ipg"; 249 assigned-clocks = <&clks IMX7ULP_CLK_LPSPI2>; 250 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; 251 assigned-clock-rates = <48000000>; 252 status = "disabled"; 253 }; 254 255 lpspi3: lpspi@402A0000 { 256 compatible = "fsl,imx7ulp-spi"; 257 reg = <0x402A0000 0x10000>; 258 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 259 clocks = <&clks IMX7ULP_CLK_LPSPI3>; 260 clock-names = "ipg"; 261 assigned-clocks = <&clks IMX7ULP_CLK_LPSPI3>; 262 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; 263 assigned-clock-rates = <48000000>; 264 status = "disabled"; 265 }; 266 267 lpuart4: serial@402D0000 { 268 compatible = "fsl,imx7ulp-lpuart"; 269 reg = <0x402D0000 0x1000>; 270 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 271 clocks = <&clks IMX7ULP_CLK_LPUART4>; 272 clock-names = "ipg"; 273 assigned-clocks = <&clks IMX7ULP_CLK_LPUART4>; 274 assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>; 275 assigned-clock-rates = <24000000>; 276 status = "disabled"; 277 }; 278 279 lpuart5: serial@402E0000 { 280 compatible = "fsl,imx7ulp-lpuart"; 281 reg = <0x402E0000 0x1000>; 282 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 283 clocks = <&clks IMX7ULP_CLK_LPUART5>; 284 clock-names = "ipg"; 285 assigned-clocks = <&clks IMX7ULP_CLK_LPUART5>; 286 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; 287 assigned-clock-rates = <48000000>; 288 dmas = <&edma0 0 20>, <&edma0 0 19>; 289 dma-names = "tx","rx"; 290 status = "disabled"; 291 }; 292 293 usbotg1: usb@40330000 { 294 compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb", 295 "fsl,imx27-usb"; 296 reg = <0x40330000 0x200>; 297 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 298 clocks = <&clks IMX7ULP_CLK_USB0>; 299 fsl,usbphy = <&usbphy1>; 300 fsl,usbmisc = <&usbmisc1 0>; 301 ahb-burst-config = <0x0>; 302 tx-burst-size-dword = <0x8>; 303 rx-burst-size-dword = <0x8>; 304 status = "disabled"; 305 }; 306 307 usbmisc1: usbmisc@40330200 { 308 #index-cells = <1>; 309 compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc", 310 "fsl,imx6q-usbmisc"; 311 reg = <0x40330200 0x200>; 312 }; 313 314 usbphy1: usbphy@0x40350000 { 315 compatible = "fsl,imx7ulp-usbphy", 316 "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; 317 reg = <0x40350000 0x1000>; 318 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&clks IMX7ULP_CLK_USB_PHY>; 320 nxp,sim = <&sim>; 321 }; 322 323 usdhc0: usdhc@40370000 { 324 compatible = "fsl,imx7ulp-usdhc"; 325 reg = <0x40370000 0x10000>; 326 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>, 328 <&clks IMX7ULP_CLK_NIC1_DIV>, 329 <&clks IMX7ULP_CLK_USDHC0>; 330 clock-names ="ipg", "ahb", "per"; 331 bus-width = <4>; 332 fsl,tuning-start-tap = <20>; 333 fsl,tuning-step= <2>; 334 status = "disabled"; 335 }; 336 337 usdhc1: usdhc@40380000 { 338 compatible = "fsl,imx7ulp-usdhc"; 339 reg = <0x40380000 0x10000>; 340 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 341 clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>, 342 <&clks IMX7ULP_CLK_NIC1_DIV>, 343 <&clks IMX7ULP_CLK_USDHC1>; 344 clock-names ="ipg", "ahb", "per"; 345 bus-width = <4>; 346 fsl,tuning-start-tap = <20>; 347 fsl,tuning-step= <2>; 348 status = "disabled"; 349 }; 350 351 wdog1: wdog@403D0000 { 352 compatible = "fsl,imx7ulp-wdt"; 353 reg = <0x403D0000 0x10000>; 354 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 355 clocks = <&clks IMX7ULP_CLK_WDG1>; 356 assigned-clocks = <&clks IMX7ULP_CLK_WDG1>; 357 assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>; 358 /* 359 * As the 1KHz LPO clock rate is not trimed,the actually clock 360 * is about 667Hz, so the init timeout 60s should set 40*1000 361 * in the TOVAL register. 362 */ 363 timeout-sec = <40>; 364 }; 365 366 wdog2: wdog@40430000 { 367 compatible = "fsl,imx7ulp-wdt"; 368 reg = <0x40430000 0x10000>; 369 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 370 clocks = <&clks IMX7ULP_CLK_WDG2>; 371 assigned-clocks = <&clks IMX7ULP_CLK_WDG2>; 372 assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>; 373 timeout-sec = <40>; 374 }; 375 376 clks: scg1@403E0000 { 377 compatible = "fsl,imx7ulp-scg1"; 378 reg = <0x403E0000 0x10000>; 379 clocks = <&ckil>, <&osc>, <&sirc>, 380 <&firc>, <&upll>, <&mpll>; 381 clock-names = "ckil", "osc", "sirc", 382 "firc", "upll", "mpll"; 383 #clock-cells = <1>; 384 assigned-clocks = <&clks IMX7ULP_CLK_LPTPM5>, 385 <&clks IMX7ULP_CLK_USDHC1>; 386 assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>, 387 <&clks IMX7ULP_CLK_NIC1_DIV>; 388 }; 389 390 pcc2: pcc2@403F0000 { 391 compatible = "fsl,imx7ulp-pcc2"; 392 reg = <0x403F0000 0x10000>; 393 }; 394 395 pmc1: pmc1@40400000 { 396 compatible = "fsl,imx7ulp-pmc1"; 397 reg = <0x40400000 0x1000>; 398 }; 399 400 smc1: smc1@40410000 { 401 compatible = "fsl,imx7ulp-smc1"; 402 reg = <0x40410000 0x1000>; 403 }; 404 405 }; 406 407 ahbbridge1: ahb-bridge1@40800000 { 408 compatible = "fsl,aips-bus", "simple-bus"; 409 #address-cells = <1>; 410 #size-cells = <1>; 411 reg = <0x40800000 0x800000>; 412 ranges; 413 414 lpi2c6: lpi2c6@40A40000 { 415 compatible = "fsl,imx7ulp-lpi2c"; 416 reg = <0x40A40000 0x10000>; 417 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&clks IMX7ULP_CLK_LPI2C6>; 419 clock-names = "ipg"; 420 assigned-clocks = <&clks IMX7ULP_CLK_LPI2C6>; 421 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; 422 assigned-clock-rates = <48000000>; 423 status = "disabled"; 424 }; 425 426 lpi2c7: lpi2c7@40A50000 { 427 compatible = "fsl,imx7ulp-lpi2c"; 428 reg = <0x40A50000 0x10000>; 429 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&clks IMX7ULP_CLK_LPI2C7>; 431 clock-names = "ipg"; 432 assigned-clocks = <&clks IMX7ULP_CLK_LPI2C7>; 433 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; 434 assigned-clock-rates = <48000000>; 435 status = "disabled"; 436 }; 437 438 lpuart6: serial@40A60000 { 439 compatible = "fsl,imx7ulp-lpuart"; 440 reg = <0x40A60000 0x1000>; 441 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 442 clocks = <&clks IMX7ULP_CLK_LPUART6>; 443 clock-names = "ipg"; 444 assigned-clocks = <&clks IMX7ULP_CLK_LPUART6>; 445 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; 446 assigned-clock-rates = <48000000>; 447 dmas = <&edma0 0 22>, <&edma0 0 21>; 448 dma-names = "tx","rx"; 449 status = "disabled"; 450 }; 451 452 lpuart7: serial@40A70000 { 453 compatible = "fsl,imx7ulp-lpuart"; 454 reg = <0x40A70000 0x1000>; 455 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&clks IMX7ULP_CLK_LPUART7>; 457 clock-names = "ipg"; 458 assigned-clocks = <&clks IMX7ULP_CLK_LPUART7>; 459 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; 460 assigned-clock-rates = <50000000>; 461 dmas = <&edma0 0 24>, <&edma0 0 23>; 462 dma-names = "tx","rx"; 463 status = "disabled"; 464 }; 465 466 lcdif: lcdif@40AA0000 { 467 compatible = "fsl,imx7ulp-lcdif"; 468 reg = <0x40aa0000 0x10000>; 469 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&clks IMX7ULP_CLK_DUMMY>, 471 <&clks IMX7ULP_CLK_LCDIF>, 472 <&clks IMX7ULP_CLK_DUMMY>; 473 clock-names = "axi", "pix", "disp_axi"; 474 status = "disabled"; 475 }; 476 477 mipi_dsi: mipi_dsi@40A90000 { 478 compatible = "fsl,imx7ulp-mipi-dsi"; 479 reg = <0x40A90000 0x10000>; 480 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&clks IMX7ULP_CLK_DSI>; 482 clock-names = "mipi_dsi_clk"; 483 sim = <&sim>; 484 status = "disabled"; 485 }; 486 487 mmdc: mmdc@40ab0000 { 488 compatible = "fsl,imx7ulp-mmdc"; 489 reg = <0x40ab0000 0x4000>; 490 }; 491 492 pcc3: pcc3@40B30000 { 493 compatible = "fsl,imx7ulp-pcc3"; 494 reg = <0x40B30000 0x10000>; 495 }; 496 497 iomuxc: iomuxc@4103D000 { 498 compatible = "fsl,imx7ulp-iomuxc-0"; 499 reg = <0x4103D000 0x1000>; 500 fsl,mux_mask = <0xf00>; 501 status = "disabled"; 502 }; 503 504 iomuxc1: iomuxc1@40ac0000 { 505 compatible = "fsl,imx7ulp-iomuxc-1"; 506 reg = <0x40ac0000 0x1000>; 507 fsl,mux_mask = <0xf00>; 508 }; 509 510 gpio4: gpio@4103f000 { 511 compatible = "fsl,imx7ulp-gpio"; 512 reg = <0x4103f000 0x1000 0x4100F000 0x40>; 513 gpio-controller; 514 #gpio-cells = <2>; 515 gpio-ranges = <&iomuxc 0 0 32>; 516 }; 517 518 gpio5: gpio@41040000 { 519 compatible = "fsl,imx7ulp-gpio"; 520 reg = <0x41040000 0x1000 0x4100F040 0x40>; 521 gpio-controller; 522 #gpio-cells = <2>; 523 gpio-ranges = <&iomuxc 0 32 32>; 524 }; 525 526 gpio0: gpio@40ae0000 { 527 compatible = "fsl,imx7ulp-gpio"; 528 reg = <0x40ae0000 0x1000 0x400F0000 0x40>; 529 gpio-controller; 530 #gpio-cells = <2>; 531 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 532 interrupt-controller; 533 #interrupt-cells = <2>; 534 gpio-ranges = <&iomuxc1 0 0 32>; 535 }; 536 537 gpio1: gpio@40af0000 { 538 compatible = "fsl,imx7ulp-gpio"; 539 reg = <0x40af0000 0x1000 0x400F0040 0x40>; 540 gpio-controller; 541 #gpio-cells = <2>; 542 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 543 interrupt-controller; 544 #interrupt-cells = <2>; 545 gpio-ranges = <&iomuxc1 0 32 32>; 546 }; 547 548 gpio2: gpio@40b00000 { 549 compatible = "fsl,imx7ulp-gpio"; 550 reg = <0x40b00000 0x1000 0x400F0080 0x40>; 551 gpio-controller; 552 #gpio-cells = <2>; 553 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 554 interrupt-controller; 555 #interrupt-cells = <2>; 556 gpio-ranges = <&iomuxc1 0 64 32>; 557 }; 558 559 gpio3: gpio@40b10000 { 560 compatible = "fsl,imx7ulp-gpio"; 561 reg = <0x40b10000 0x1000 0x400F00c0 0x40>; 562 gpio-controller; 563 #gpio-cells = <2>; 564 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 565 interrupt-controller; 566 #interrupt-cells = <2>; 567 gpio-ranges = <&iomuxc1 0 96 32>; 568 }; 569 570 pmc0: pmc0@410a1000 { 571 compatible = "fsl,imx7ulp-pmc0"; 572 reg = <0x410a1000 0x1000>; 573 }; 574 575 sim: sim@410a3000 { 576 compatible = "fsl,imx7ulp-sim", "syscon"; 577 reg = <0x410a3000 0x1000>; 578 }; 579 580 qspi1: qspi@410A5000 { 581 #address-cells = <1>; 582 #size-cells = <0>; 583 compatible = "fsl,imx7ulp-qspi"; 584 reg = <0x410A5000 0x10000>, <0xC0000000 0x10000000>; 585 reg-names = "QuadSPI", "QuadSPI-memory"; 586 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 587 clocks = <&clks IMX7ULP_CLK_DUMMY>, 588 <&clks IMX7ULP_CLK_DUMMY>; 589 clock-names = "qspi_en", "qspi"; 590 status = "disabled"; 591 }; 592 593 gpu: gpu@41800000 { 594 compatible = "fsl,imx6q-gpu"; 595 reg = <0x41800000 0x80000>, <0x41880000 0x80000>, 596 <0x60000000 0x40000000>, <0x0 0x4000000>; 597 reg-names = "iobase_3d", "iobase_2d", 598 "phys_baseaddr", "contiguous_mem"; 599 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 601 interrupt-names = "irq_3d", "irq_2d"; 602 clocks = <&clks IMX7ULP_CLK_GPU3D>, 603 <&clks IMX7ULP_CLK_NIC1_DIV>, 604 <&clks IMX7ULP_CLK_GPU_DIV>, 605 <&clks IMX7ULP_CLK_GPU2D>, 606 <&clks IMX7ULP_CLK_NIC1_DIV>, 607 <&clks IMX7ULP_CLK_NIC1_DIV>; 608 clock-names = "gpu3d_clk", "gpu3d_shader_clk", 609 "gpu3d_axi_clk", "gpu2d_clk", 610 "gpu2d_shader_clk", "gpu2d_axi_clk"; 611 }; 612 }; 613 614 imx_ion { 615 compatible = "fsl,mxc-ion"; 616 fsl,heap-id = <0>; 617 }; 618}; 619