1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) 2020
4 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
5 */
6
7#include "armv7-m.dtsi"
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/imxrt1020-clock.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/memory/imxrt-sdram.h>
12
13/ {
14	#address-cells = <1>;
15	#size-cells = <1>;
16
17	aliases {
18		gpio0 = &gpio1;
19		gpio1 = &gpio2;
20		gpio2 = &gpio3;
21		mmc0 = &usdhc1;
22		serial0 = &lpuart1;
23	};
24
25	clocks {
26		ckil {
27			compatible = "fsl,imx-ckil", "fixed-clock";
28			#clock-cells = <0>;
29			clock-frequency = <32768>;
30		};
31
32		ckih1 {
33			compatible = "fsl,imx-ckih1", "fixed-clock";
34			#clock-cells = <0>;
35			clock-frequency = <0>;
36		};
37
38		osc: osc {
39			compatible = "fsl,imx-osc", "fixed-clock";
40			#clock-cells = <0>;
41			clock-frequency = <24000000>;
42		};
43	};
44
45	soc {
46		semc: semc@402f0000 {
47			compatible = "fsl,imxrt-semc";
48			reg = <0x402f0000 0x4000>;
49			clocks = <&clks IMXRT1020_CLK_SEMC>;
50			pinctrl-0 = <&pinctrl_semc>;
51			pinctrl-names = "default";
52			status = "okay";
53		};
54
55		lpuart1: serial@40184000 {
56			compatible = "fsl,imxrt-lpuart";
57			reg = <0x40184000 0x4000>;
58			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
59			clocks = <&clks IMXRT1020_CLK_LPUART1>;
60			clock-names = "per";
61			status = "disabled";
62		};
63
64		iomuxc: iomuxc@401f8000 {
65			compatible = "fsl,imxrt-iomuxc";
66			reg = <0x401f8000 0x4000>;
67			fsl,mux_mask = <0x7>;
68		};
69
70		clks: ccm@400fc000 {
71			compatible = "fsl,imxrt1020-ccm";
72			reg = <0x400fc000 0x4000>;
73			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
74				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
75			#clock-cells = <1>;
76		};
77
78		usdhc1: usdhc@402c0000 {
79			compatible = "fsl,imxrt-usdhc";
80			reg = <0x402c0000 0x10000>;
81			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
82			clocks = <&clks IMXRT1020_CLK_USDHC1>;
83			clock-names = "per";
84			bus-width = <4>;
85			fsl,tuning-start-tap = <20>;
86			fsl,tuning-step= <2>;
87			status = "disabled";
88		};
89
90		gpio1: gpio@401b8000 {
91			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
92			reg = <0x401b8000 0x4000>;
93			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
94				     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
95			gpio-controller;
96			#gpio-cells = <2>;
97			interrupt-controller;
98			#interrupt-cells = <2>;
99		};
100
101		gpio2: gpio@401bc000 {
102			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
103			reg = <0x401bc000 0x4000>;
104			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
105				<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
106			gpio-controller;
107			#gpio-cells = <2>;
108			interrupt-controller;
109			#interrupt-cells = <2>;
110		};
111
112		gpio3: gpio@401c0000 {
113			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
114			reg = <0x401c0000 0x4000>;
115			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
116				<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
117			gpio-controller;
118			#gpio-cells = <2>;
119			interrupt-controller;
120			#interrupt-cells = <2>;
121		};
122
123		gpio5: gpio@400c0000 {
124			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
125			reg = <0x400c0000 0x4000>;
126			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
127				<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
128			gpio-controller;
129			#gpio-cells = <2>;
130			interrupt-controller;
131			#interrupt-cells = <2>;
132		};
133
134		gpt1: gpt1@401ec000 {
135			compatible = "fsl,imxrt-gpt";
136			reg = <0x401ec000 0x4000>;
137			interrupts = <100>;
138			clocks = <&osc>;
139			status = "disabled";
140		};
141	};
142};
143