1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Copyright (C) 2021 BayLibre, SAS
5 * Author: Ben Ho <ben.ho@mediatek.com>
6 *         Erin Lo <erin.lo@mediatek.com>
7 *         Fabien Parent <fparent@baylibre.com>
8 */
9
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/clock/mt8183-clk.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/phy/phy.h>
15
16/ {
17	compatible = "mediatek,mt8183";
18	interrupt-parent = <&sysirq>;
19	#address-cells = <2>;
20	#size-cells = <2>;
21
22	cpus {
23		#address-cells = <1>;
24		#size-cells = <0>;
25
26		cpu-map {
27			cluster0 {
28				core0 {
29					cpu = <&cpu0>;
30				};
31				core1 {
32					cpu = <&cpu1>;
33				};
34				core2 {
35					cpu = <&cpu2>;
36				};
37				core3 {
38					cpu = <&cpu3>;
39				};
40			};
41
42			cluster1 {
43				core0 {
44					cpu = <&cpu4>;
45				};
46				core1 {
47					cpu = <&cpu5>;
48				};
49				core2 {
50					cpu = <&cpu6>;
51				};
52				core3 {
53					cpu = <&cpu7>;
54				};
55			};
56		};
57
58		cpu0: cpu@0 {
59			device_type = "cpu";
60			compatible = "arm,cortex-a53";
61			reg = <0x000>;
62			enable-method = "psci";
63			capacity-dmips-mhz = <741>;
64		};
65
66		cpu1: cpu@1 {
67			device_type = "cpu";
68			compatible = "arm,cortex-a53";
69			reg = <0x001>;
70			enable-method = "psci";
71			capacity-dmips-mhz = <741>;
72		};
73
74		cpu2: cpu@2 {
75			device_type = "cpu";
76			compatible = "arm,cortex-a53";
77			reg = <0x002>;
78			enable-method = "psci";
79			capacity-dmips-mhz = <741>;
80		};
81
82		cpu3: cpu@3 {
83			device_type = "cpu";
84			compatible = "arm,cortex-a53";
85			reg = <0x003>;
86			enable-method = "psci";
87			capacity-dmips-mhz = <741>;
88		};
89
90		cpu4: cpu@100 {
91			device_type = "cpu";
92			compatible = "arm,cortex-a73";
93			reg = <0x100>;
94			enable-method = "psci";
95			capacity-dmips-mhz = <1024>;
96		};
97
98		cpu5: cpu@101 {
99			device_type = "cpu";
100			compatible = "arm,cortex-a73";
101			reg = <0x101>;
102			enable-method = "psci";
103			capacity-dmips-mhz = <1024>;
104		};
105
106		cpu6: cpu@102 {
107			device_type = "cpu";
108			compatible = "arm,cortex-a73";
109			reg = <0x102>;
110			enable-method = "psci";
111			capacity-dmips-mhz = <1024>;
112		};
113
114		cpu7: cpu@103 {
115			device_type = "cpu";
116			compatible = "arm,cortex-a73";
117			reg = <0x103>;
118			enable-method = "psci";
119			capacity-dmips-mhz = <1024>;
120		};
121	};
122
123	clk26m: oscillator {
124		compatible = "fixed-clock";
125		#clock-cells = <0>;
126		clock-frequency = <26000000>;
127		clock-output-names = "clk26m";
128	};
129
130	soc {
131		#address-cells = <2>;
132		#size-cells = <2>;
133		compatible = "simple-bus";
134		ranges;
135
136		watchdog: watchdog@10007000 {
137			compatible = "mediatek,mt8183-wdt",
138				      "mediatek,wdt";
139			reg = <0 0x10007000 0 0x100>;
140			status = "disabled";
141		};
142
143		gic: interrupt-controller@c000000 {
144			compatible = "arm,gic-v3";
145			#interrupt-cells = <4>;
146			interrupt-parent = <&gic>;
147			interrupt-controller;
148			reg = <0 0x0c000000 0 0x40000>,  /* GICD */
149			      <0 0x0c100000 0 0x200000>, /* GICR */
150			      <0 0x0c400000 0 0x2000>,   /* GICC */
151			      <0 0x0c410000 0 0x1000>,   /* GICH */
152			      <0 0x0c420000 0 0x2000>;   /* GICV */
153
154			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
155			ppi-partitions {
156				ppi_cluster0: interrupt-partition-0 {
157					affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
158				};
159				ppi_cluster1: interrupt-partition-1 {
160					affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
161				};
162			};
163		};
164
165		sysirq: interrupt-controller@c530a80 {
166			compatible = "mediatek,mt8183-sysirq",
167				     "mediatek,mt6577-sysirq";
168			interrupt-controller;
169			#interrupt-cells = <3>;
170			interrupt-parent = <&gic>;
171			reg = <0 0x0c530a80 0 0x50>;
172		};
173
174		topckgen: syscon@10000000 {
175			compatible = "mediatek,mt8183-topckgen", "syscon";
176			reg = <0 0x10000000 0 0x1000>;
177			#clock-cells = <1>;
178		};
179
180		infracfg: syscon@10001000 {
181			compatible = "mediatek,mt8183-infracfg", "syscon";
182			reg = <0 0x10001000 0 0x1000>;
183			#clock-cells = <1>;
184		};
185
186		apmixedsys: syscon@1000c000 {
187			compatible = "mediatek,mt8183-apmixedsys", "syscon";
188			reg = <0 0x1000c000 0 0x1000>;
189			#clock-cells = <1>;
190		};
191
192		uart0: serial@11002000 {
193			compatible = "mediatek,mt8183-uart",
194				     "mediatek,hsuart";
195			reg = <0 0x11002000 0 0x1000>;
196			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
197			clock-frequency = <26000000>;
198			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
199			clock-names = "baud", "bus";
200			status = "disabled";
201		};
202
203		mmc0: mmc@11230000 {
204			compatible = "mediatek,mt8183-mmc";
205			reg = <0 0x11230000 0 0x1000>,
206			      <0 0x11f50000 0 0x1000>;
207			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
208			clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>,
209				 <&infracfg CLK_INFRA_MSDC0>,
210				 <&infracfg CLK_INFRA_MSDC0_SCK>;
211			clock-names = "source", "hclk", "source_cg";
212			status = "disabled";
213		};
214
215		u3phy: usb-phy@11f40000 {
216			compatible = "mediatek,generic-tphy-v2";
217			#address-cells = <2>;
218			#size-cells = <2>;
219			ranges;
220			status = "okay";
221
222			u2port0: usb-phy2@11f40000 {
223				reg = <0 0x11f40000 0 0x700>;
224				clocks = <&clk26m>;
225				clock-names = "ref";
226				#phy-cells = <1>;
227				status = "okay";
228			};
229
230			u3port0: usb-phy3@11f40700 {
231				reg = <0 0x11f40700 0 0x900>;
232				clocks = <&clk26m>;
233				clock-names = "ref";
234				#phy-cells = <1>;
235				status = "okay";
236			};
237		};
238
239		usb: usb@11200000 {
240			compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3";
241			reg = <0 0x11200000 0 0x3e00>,
242			      <0 0x11203e00 0 0x0100>;
243			reg-names = "mac", "ippc";
244			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
245			phys = <&u2port0 PHY_TYPE_USB2>;
246			clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
247				 <&infracfg CLK_INFRA_USB>;
248			clock-names = "sys_ck", "ref_ck";
249			#address-cells = <2>;
250			#size-cells = <2>;
251			ranges;
252			status = "disabled";
253
254			ssusb: ssusb@11200000 {
255				compatible = "mediatek,ssusb";
256				reg = <0 0x11200000 0 0x3e00>;
257				reg-names = "mac";
258				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
259				status = "disabled";
260			};
261
262			usb_host: xhci@11200000 {
263				compatible = "mediatek,mtk-xhci";
264				reg = <0 0x11200000 0 0x1000>;
265				reg-names = "mac";
266				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
267				clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
268					 <&infracfg CLK_INFRA_USB>;
269				clock-names = "sys_ck", "ref_ck";
270				status = "disabled";
271			};
272		};
273	};
274};
275