1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
4 */
5
6/ {
7	cluster0_opp: opp-table0 {
8		compatible = "operating-points-v2";
9		opp-shared;
10
11		opp00 {
12			opp-hz = /bits/ 64 <408000000>;
13			opp-microvolt = <800000>;
14			clock-latency-ns = <40000>;
15		};
16		opp01 {
17			opp-hz = /bits/ 64 <600000000>;
18			opp-microvolt = <825000>;
19		};
20		opp02 {
21			opp-hz = /bits/ 64 <816000000>;
22			opp-microvolt = <850000>;
23		};
24		opp03 {
25			opp-hz = /bits/ 64 <1008000000>;
26			opp-microvolt = <900000>;
27		};
28		opp04 {
29			opp-hz = /bits/ 64 <1200000000>;
30			opp-microvolt = <975000>;
31		};
32		opp05 {
33			opp-hz = /bits/ 64 <1416000000>;
34			opp-microvolt = <1100000>;
35		};
36		opp06 {
37			opp-hz = /bits/ 64 <1512000000>;
38			opp-microvolt = <1150000>;
39		};
40	};
41
42	cluster1_opp: opp-table1 {
43		compatible = "operating-points-v2";
44		opp-shared;
45
46		opp00 {
47			opp-hz = /bits/ 64 <408000000>;
48			opp-microvolt = <800000>;
49			clock-latency-ns = <40000>;
50		};
51		opp01 {
52			opp-hz = /bits/ 64 <600000000>;
53			opp-microvolt = <800000>;
54		};
55		opp02 {
56			opp-hz = /bits/ 64 <816000000>;
57			opp-microvolt = <825000>;
58		};
59		opp03 {
60			opp-hz = /bits/ 64 <1008000000>;
61			opp-microvolt = <850000>;
62		};
63		opp04 {
64			opp-hz = /bits/ 64 <1200000000>;
65			opp-microvolt = <900000>;
66		};
67		opp05 {
68			opp-hz = /bits/ 64 <1416000000>;
69			opp-microvolt = <975000>;
70		};
71		opp06 {
72			opp-hz = /bits/ 64 <1608000000>;
73			opp-microvolt = <1050000>;
74		};
75		opp07 {
76			opp-hz = /bits/ 64 <1800000000>;
77			opp-microvolt = <1150000>;
78		};
79		opp08 {
80			opp-hz = /bits/ 64 <2016000000>;
81			opp-microvolt = <1250000>;
82		};
83	};
84
85	gpu_opp_table: opp-table2 {
86		compatible = "operating-points-v2";
87
88		opp00 {
89			opp-hz = /bits/ 64 <200000000>;
90			opp-microvolt = <800000>;
91		};
92		opp01 {
93			opp-hz = /bits/ 64 <297000000>;
94			opp-microvolt = <800000>;
95		};
96		opp02 {
97			opp-hz = /bits/ 64 <400000000>;
98			opp-microvolt = <825000>;
99		};
100		opp03 {
101			opp-hz = /bits/ 64 <500000000>;
102			opp-microvolt = <850000>;
103		};
104		opp04 {
105			opp-hz = /bits/ 64 <600000000>;
106			opp-microvolt = <925000>;
107		};
108		opp05 {
109			opp-hz = /bits/ 64 <800000000>;
110			opp-microvolt = <1075000>;
111		};
112	};
113};
114
115&cpu_l0 {
116	operating-points-v2 = <&cluster0_opp>;
117};
118
119&cpu_l1 {
120	operating-points-v2 = <&cluster0_opp>;
121};
122
123&cpu_l2 {
124	operating-points-v2 = <&cluster0_opp>;
125};
126
127&cpu_l3 {
128	operating-points-v2 = <&cluster0_opp>;
129};
130
131&cpu_b0 {
132	operating-points-v2 = <&cluster1_opp>;
133};
134
135&cpu_b1 {
136	operating-points-v2 = <&cluster1_opp>;
137};
138
139&gpu {
140	operating-points-v2 = <&gpu_opp_table>;
141};
142