1/*
2 * Copyright 2014 Chen-Yu Tsai
3 *
4 * Chen-Yu Tsai <wens@csie.org>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 *  a) This file is free software; you can redistribute it and/or
12 *     modify it under the terms of the GNU General Public License as
13 *     published by the Free Software Foundation; either version 2 of the
14 *     License, or (at your option) any later version.
15 *
16 *     This file is distributed in the hope that it will be useful,
17 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
18 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19 *     GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 *  b) Permission is hereby granted, free of charge, to any person
24 *     obtaining a copy of this software and associated documentation
25 *     files (the "Software"), to deal in the Software without
26 *     restriction, including without limitation the rights to use,
27 *     copy, modify, merge, publish, distribute, sublicense, and/or
28 *     sell copies of the Software, and to permit persons to whom the
29 *     Software is furnished to do so, subject to the following
30 *     conditions:
31 *
32 *     The above copyright notice and this permission notice shall be
33 *     included in all copies or substantial portions of the Software.
34 *
35 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 *     OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45#include "sun8i-a23-a33.dtsi"
46#include <dt-bindings/thermal/thermal.h>
47
48/ {
49	cpu0_opp_table: opp_table0 {
50		compatible = "operating-points-v2";
51		opp-shared;
52
53		opp-120000000 {
54			opp-hz = /bits/ 64 <120000000>;
55			opp-microvolt = <1040000>;
56			clock-latency-ns = <244144>; /* 8 32k periods */
57		};
58
59		opp-240000000 {
60			opp-hz = /bits/ 64 <240000000>;
61			opp-microvolt = <1040000>;
62			clock-latency-ns = <244144>; /* 8 32k periods */
63		};
64
65		opp-312000000 {
66			opp-hz = /bits/ 64 <312000000>;
67			opp-microvolt = <1040000>;
68			clock-latency-ns = <244144>; /* 8 32k periods */
69		};
70
71		opp-408000000 {
72			opp-hz = /bits/ 64 <408000000>;
73			opp-microvolt = <1040000>;
74			clock-latency-ns = <244144>; /* 8 32k periods */
75		};
76
77		opp-480000000 {
78			opp-hz = /bits/ 64 <480000000>;
79			opp-microvolt = <1040000>;
80			clock-latency-ns = <244144>; /* 8 32k periods */
81		};
82
83		opp-504000000 {
84			opp-hz = /bits/ 64 <504000000>;
85			opp-microvolt = <1040000>;
86			clock-latency-ns = <244144>; /* 8 32k periods */
87		};
88
89		opp-600000000 {
90			opp-hz = /bits/ 64 <600000000>;
91			opp-microvolt = <1040000>;
92			clock-latency-ns = <244144>; /* 8 32k periods */
93		};
94
95		opp-648000000 {
96			opp-hz = /bits/ 64 <648000000>;
97			opp-microvolt = <1040000>;
98			clock-latency-ns = <244144>; /* 8 32k periods */
99		};
100
101		opp-720000000 {
102			opp-hz = /bits/ 64 <720000000>;
103			opp-microvolt = <1100000>;
104			clock-latency-ns = <244144>; /* 8 32k periods */
105		};
106
107		opp-816000000 {
108			opp-hz = /bits/ 64 <816000000>;
109			opp-microvolt = <1100000>;
110			clock-latency-ns = <244144>; /* 8 32k periods */
111		};
112
113		opp-912000000 {
114			opp-hz = /bits/ 64 <912000000>;
115			opp-microvolt = <1200000>;
116			clock-latency-ns = <244144>; /* 8 32k periods */
117		};
118
119		opp-1008000000 {
120			opp-hz = /bits/ 64 <1008000000>;
121			opp-microvolt = <1200000>;
122			clock-latency-ns = <244144>; /* 8 32k periods */
123		};
124	};
125
126	cpus {
127		cpu@0 {
128			clocks = <&ccu CLK_CPUX>;
129			clock-names = "cpu";
130			operating-points-v2 = <&cpu0_opp_table>;
131			#cooling-cells = <2>;
132		};
133
134		cpu@1 {
135			operating-points-v2 = <&cpu0_opp_table>;
136		};
137
138		cpu@2 {
139			compatible = "arm,cortex-a7";
140			device_type = "cpu";
141			reg = <2>;
142			operating-points-v2 = <&cpu0_opp_table>;
143		};
144
145		cpu@3 {
146			compatible = "arm,cortex-a7";
147			device_type = "cpu";
148			reg = <3>;
149			operating-points-v2 = <&cpu0_opp_table>;
150		};
151	};
152
153	de: display-engine {
154		compatible = "allwinner,sun8i-a33-display-engine";
155		allwinner,pipelines = <&fe0>;
156		status = "disabled";
157	};
158
159	iio-hwmon {
160		compatible = "iio-hwmon";
161		io-channels = <&ths>;
162	};
163
164	mali_opp_table: gpu-opp-table {
165		compatible = "operating-points-v2";
166
167		opp-144000000 {
168			opp-hz = /bits/ 64 <144000000>;
169		};
170
171		opp-240000000 {
172			opp-hz = /bits/ 64 <240000000>;
173		};
174
175		opp-384000000 {
176			opp-hz = /bits/ 64 <384000000>;
177		};
178	};
179
180	memory {
181		reg = <0x40000000 0x80000000>;
182	};
183
184	sound: sound {
185		compatible = "simple-audio-card";
186		simple-audio-card,name = "sun8i-a33-audio";
187		simple-audio-card,format = "i2s";
188		simple-audio-card,frame-master = <&link_codec>;
189		simple-audio-card,bitclock-master = <&link_codec>;
190		simple-audio-card,mclk-fs = <512>;
191		simple-audio-card,aux-devs = <&codec_analog>;
192		simple-audio-card,routing =
193			"Left DAC", "AIF1 Slot 0 Left",
194			"Right DAC", "AIF1 Slot 0 Right";
195		status = "disabled";
196
197		simple-audio-card,cpu {
198			sound-dai = <&dai>;
199		};
200
201		link_codec: simple-audio-card,codec {
202			sound-dai = <&codec>;
203		};
204	};
205
206	soc@1c00000 {
207		tcon0: lcd-controller@1c0c000 {
208			compatible = "allwinner,sun8i-a33-tcon";
209			reg = <0x01c0c000 0x1000>;
210			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
211			clocks = <&ccu CLK_BUS_LCD>,
212				 <&ccu CLK_LCD_CH0>;
213			clock-names = "ahb",
214				      "tcon-ch0";
215			clock-output-names = "tcon-pixel-clock";
216			resets = <&ccu RST_BUS_LCD>;
217			reset-names = "lcd";
218			status = "disabled";
219
220			ports {
221				#address-cells = <1>;
222				#size-cells = <0>;
223
224				tcon0_in: port@0 {
225					#address-cells = <1>;
226					#size-cells = <0>;
227					reg = <0>;
228
229					tcon0_in_drc0: endpoint@0 {
230						reg = <0>;
231						remote-endpoint = <&drc0_out_tcon0>;
232					};
233				};
234
235				tcon0_out: port@1 {
236					#address-cells = <1>;
237					#size-cells = <0>;
238					reg = <1>;
239
240					tcon0_out_dsi: endpoint@1 {
241						reg = <1>;
242						remote-endpoint = <&dsi_in_tcon0>;
243					};
244				};
245			};
246		};
247
248		crypto: crypto-engine@1c15000 {
249			compatible = "allwinner,sun4i-a10-crypto";
250			reg = <0x01c15000 0x1000>;
251			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
252			clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
253			clock-names = "ahb", "mod";
254			resets = <&ccu RST_BUS_SS>;
255			reset-names = "ahb";
256		};
257
258		dai: dai@1c22c00 {
259			#sound-dai-cells = <0>;
260			compatible = "allwinner,sun6i-a31-i2s";
261			reg = <0x01c22c00 0x200>;
262			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
263			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
264			clock-names = "apb", "mod";
265			resets = <&ccu RST_BUS_CODEC>;
266			dmas = <&dma 15>, <&dma 15>;
267			dma-names = "rx", "tx";
268			status = "disabled";
269		};
270
271		codec: codec@1c22e00 {
272			#sound-dai-cells = <0>;
273			compatible = "allwinner,sun8i-a33-codec";
274			reg = <0x01c22e00 0x400>;
275			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
276			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
277			clock-names = "bus", "mod";
278			status = "disabled";
279		};
280
281		ths: ths@1c25000 {
282			compatible = "allwinner,sun8i-a33-ths";
283			reg = <0x01c25000 0x100>;
284			#thermal-sensor-cells = <0>;
285			#io-channel-cells = <0>;
286		};
287
288		dsi: dsi@1ca0000 {
289			compatible = "allwinner,sun6i-a31-mipi-dsi";
290			reg = <0x01ca0000 0x1000>;
291			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
292			clocks = <&ccu CLK_BUS_MIPI_DSI>,
293				 <&ccu CLK_DSI_SCLK>;
294			clock-names = "bus", "mod";
295			resets = <&ccu RST_BUS_MIPI_DSI>;
296			phys = <&dphy>;
297			phy-names = "dphy";
298			status = "disabled";
299
300			ports {
301				#address-cells = <1>;
302				#size-cells = <0>;
303
304				port@0 {
305					#address-cells = <1>;
306					#size-cells = <0>;
307					reg = <0>;
308
309					dsi_in_tcon0: endpoint {
310						remote-endpoint = <&tcon0_out_dsi>;
311					};
312				};
313			};
314		};
315
316		dphy: d-phy@1ca1000 {
317			compatible = "allwinner,sun6i-a31-mipi-dphy";
318			reg = <0x01ca1000 0x1000>;
319			clocks = <&ccu CLK_BUS_MIPI_DSI>,
320				 <&ccu CLK_DSI_DPHY>;
321			clock-names = "bus", "mod";
322			resets = <&ccu RST_BUS_MIPI_DSI>;
323			status = "disabled";
324			#phy-cells = <0>;
325		};
326
327		fe0: display-frontend@1e00000 {
328			compatible = "allwinner,sun8i-a33-display-frontend";
329			reg = <0x01e00000 0x20000>;
330			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
331			clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
332				 <&ccu CLK_DRAM_DE_FE>;
333			clock-names = "ahb", "mod",
334				      "ram";
335			resets = <&ccu RST_BUS_DE_FE>;
336
337			ports {
338				#address-cells = <1>;
339				#size-cells = <0>;
340
341				fe0_out: port@1 {
342					#address-cells = <1>;
343					#size-cells = <0>;
344					reg = <1>;
345
346					fe0_out_be0: endpoint@0 {
347						reg = <0>;
348						remote-endpoint = <&be0_in_fe0>;
349					};
350				};
351			};
352		};
353
354		be0: display-backend@1e60000 {
355			compatible = "allwinner,sun8i-a33-display-backend";
356			reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
357			reg-names = "be", "sat";
358			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
359			clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
360				 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
361			clock-names = "ahb", "mod",
362				      "ram", "sat";
363			resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
364			reset-names = "be", "sat";
365			assigned-clocks = <&ccu CLK_DE_BE>;
366			assigned-clock-rates = <300000000>;
367
368			ports {
369				#address-cells = <1>;
370				#size-cells = <0>;
371
372				be0_in: port@0 {
373					#address-cells = <1>;
374					#size-cells = <0>;
375					reg = <0>;
376
377					be0_in_fe0: endpoint@0 {
378						reg = <0>;
379						remote-endpoint = <&fe0_out_be0>;
380					};
381				};
382
383				be0_out: port@1 {
384					#address-cells = <1>;
385					#size-cells = <0>;
386					reg = <1>;
387
388					be0_out_drc0: endpoint@0 {
389						reg = <0>;
390						remote-endpoint = <&drc0_in_be0>;
391					};
392				};
393			};
394		};
395
396		drc0: drc@1e70000 {
397			compatible = "allwinner,sun8i-a33-drc";
398			reg = <0x01e70000 0x10000>;
399			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
400			clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
401				 <&ccu CLK_DRAM_DRC>;
402			clock-names = "ahb", "mod", "ram";
403			resets = <&ccu RST_BUS_DRC>;
404
405			assigned-clocks = <&ccu CLK_DRC>;
406			assigned-clock-rates = <300000000>;
407
408			ports {
409				#address-cells = <1>;
410				#size-cells = <0>;
411
412				drc0_in: port@0 {
413					#address-cells = <1>;
414					#size-cells = <0>;
415					reg = <0>;
416
417					drc0_in_be0: endpoint@0 {
418						reg = <0>;
419						remote-endpoint = <&be0_out_drc0>;
420					};
421				};
422
423				drc0_out: port@1 {
424					#address-cells = <1>;
425					#size-cells = <0>;
426					reg = <1>;
427
428					drc0_out_tcon0: endpoint@0 {
429						reg = <0>;
430						remote-endpoint = <&tcon0_in_drc0>;
431					};
432				};
433			};
434		};
435	};
436
437	thermal-zones {
438		cpu_thermal {
439			/* milliseconds */
440			polling-delay-passive = <250>;
441			polling-delay = <1000>;
442			thermal-sensors = <&ths>;
443
444			cooling-maps {
445				map0 {
446					trip = <&cpu_alert0>;
447					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
448				};
449				map1 {
450					trip = <&cpu_alert1>;
451					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
452				};
453
454				map2 {
455					trip = <&gpu_alert0>;
456					cooling-device = <&mali 1 THERMAL_NO_LIMIT>;
457				};
458
459				map3 {
460					trip = <&gpu_alert1>;
461					cooling-device = <&mali 2 THERMAL_NO_LIMIT>;
462				};
463			};
464
465			trips {
466				cpu_alert0: cpu_alert0 {
467					/* milliCelsius */
468					temperature = <75000>;
469					hysteresis = <2000>;
470					type = "passive";
471				};
472
473				gpu_alert0: gpu_alert0 {
474					/* milliCelsius */
475					temperature = <85000>;
476					hysteresis = <2000>;
477					type = "passive";
478				};
479
480				cpu_alert1: cpu_alert1 {
481					/* milliCelsius */
482					temperature = <90000>;
483					hysteresis = <2000>;
484					type = "hot";
485				};
486
487				gpu_alert1: gpu_alert1 {
488					/* milliCelsius */
489					temperature = <95000>;
490					hysteresis = <2000>;
491					type = "hot";
492				};
493
494				cpu_crit: cpu_crit {
495					/* milliCelsius */
496					temperature = <110000>;
497					hysteresis = <2000>;
498					type = "critical";
499				};
500			};
501		};
502	};
503};
504
505&ccu {
506	compatible = "allwinner,sun8i-a33-ccu";
507};
508
509&mali {
510	operating-points-v2 = <&mali_opp_table>;
511};
512
513&pio {
514	compatible = "allwinner,sun8i-a33-pinctrl";
515	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
516		     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
517
518	uart0_pins_b: uart0@1 {
519		pins = "PB0", "PB1";
520		function = "uart0";
521	};
522
523};
524
525&usb_otg {
526	compatible = "allwinner,sun8i-a33-musb";
527};
528
529&usbphy {
530	compatible = "allwinner,sun8i-a33-usb-phy";
531	reg = <0x01c19400 0x14>, <0x01c1a800 0x4>;
532	reg-names = "phy_ctrl", "pmu1";
533};
534