1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <dm/device-internal.h>
9 #include <env.h>
10 #include <env_internal.h>
11 #include <i2c.h>
12 #include <init.h>
13 #include <mmc.h>
14 #include <phy.h>
15 #include <asm/global_data.h>
16 #include <asm/io.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/soc.h>
19 #include <linux/delay.h>
20
21 DECLARE_GLOBAL_DATA_PTR;
22
23 /* IO expander I2C device */
24 #define I2C_IO_EXP_ADDR 0x22
25 #define I2C_IO_CFG_REG_0 0x6
26 #define I2C_IO_DATA_OUT_REG_0 0x2
27 #define I2C_IO_REG_0_SATA_OFF 2
28 #define I2C_IO_REG_0_USB_H_OFF 1
29
30 /* The pin control values are the same for DB and Espressobin */
31 #define PINCTRL_NB_REG_VALUE 0x000173fa
32 #define PINCTRL_SB_REG_VALUE 0x00007a23
33
34 /* Ethernet switch registers */
35 /* SMI addresses for multi-chip mode */
36 #define MVEBU_PORT_CTRL_SMI_ADDR(p) (16 + (p))
37 #define MVEBU_SW_G2_SMI_ADDR (28)
38
39 /* Multi-chip mode */
40 #define MVEBU_SW_SMI_DATA_REG (1)
41 #define MVEBU_SW_SMI_CMD_REG (0)
42 #define SW_SMI_CMD_REG_ADDR_OFF 0
43 #define SW_SMI_CMD_DEV_ADDR_OFF 5
44 #define SW_SMI_CMD_SMI_OP_OFF 10
45 #define SW_SMI_CMD_SMI_MODE_OFF 12
46 #define SW_SMI_CMD_SMI_BUSY_OFF 15
47
48 /* Single-chip mode */
49 /* Switch Port Registers */
50 #define MVEBU_SW_LINK_CTRL_REG (1)
51 #define MVEBU_SW_PORT_CTRL_REG (4)
52 #define MVEBU_SW_PORT_BASE_VLAN (6)
53
54 /* Global 2 Registers */
55 #define MVEBU_G2_SMI_PHY_CMD_REG (24)
56 #define MVEBU_G2_SMI_PHY_DATA_REG (25)
57
58 /*
59 * Memory Controller Registers
60 *
61 * Assembled based on public information:
62 * https://gitlab.nic.cz/turris/mox-boot-builder/-/blob/master/wtmi/main.c#L332-336
63 * https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/blob/mv_ddr-armada-18.12/drivers/mv_ddr_mc6.h#L309-L332
64 *
65 * And checked against the written register values for the various topologies:
66 * https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/blob/mv_ddr-armada-atf-mainline/a3700/mv_ddr_tim.h
67 */
68 #define A3700_CH0_MC_CTRL2_REG MVEBU_REGISTER(0x002c4)
69 #define A3700_MC_CTRL2_SDRAM_TYPE_MASK 0xf
70 #define A3700_MC_CTRL2_SDRAM_TYPE_OFFS 4
71 #define A3700_MC_CTRL2_SDRAM_TYPE_DDR3 2
72 #define A3700_MC_CTRL2_SDRAM_TYPE_DDR4 3
73
board_early_init_f(void)74 int board_early_init_f(void)
75 {
76 return 0;
77 }
78
board_init(void)79 int board_init(void)
80 {
81 /* adress of boot parameters */
82 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
83
84 return 0;
85 }
86
87 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)88 int board_late_init(void)
89 {
90 char *ptr = (char *)&default_environment[0];
91 struct udevice *dev;
92 struct mmc *mmc_dev;
93 bool ddr4, emmc;
94 const char *mac;
95 char eth[10];
96 int i;
97
98 if (!of_machine_is_compatible("globalscale,espressobin"))
99 return 0;
100
101 /* Find free buffer in default_environment[] for new variables */
102 while (*ptr != '\0' && *(ptr+1) != '\0') ptr++;
103 ptr += 2;
104
105 /*
106 * Ensure that 'env default -a' does not erase permanent MAC addresses
107 * stored in env variables: $ethaddr, $eth1addr, $eth2addr and $eth3addr
108 */
109
110 mac = env_get("ethaddr");
111 if (mac && strlen(mac) <= 17)
112 ptr += sprintf(ptr, "ethaddr=%s", mac) + 1;
113
114 for (i = 1; i <= 3; i++) {
115 sprintf(eth, "eth%daddr", i);
116 mac = env_get(eth);
117 if (mac && strlen(mac) <= 17)
118 ptr += sprintf(ptr, "%s=%s", eth, mac) + 1;
119 }
120
121 /* If the memory controller has been configured for DDR4, we're running on v7 */
122 ddr4 = ((readl(A3700_CH0_MC_CTRL2_REG) >> A3700_MC_CTRL2_SDRAM_TYPE_OFFS)
123 & A3700_MC_CTRL2_SDRAM_TYPE_MASK) == A3700_MC_CTRL2_SDRAM_TYPE_DDR4;
124
125 /* eMMC is mmc dev num 1 */
126 mmc_dev = find_mmc_device(1);
127 emmc = (mmc_dev && mmc_init(mmc_dev) == 0);
128
129 /* if eMMC is not present then remove it from DM */
130 if (!emmc && mmc_dev) {
131 dev = mmc_dev->dev;
132 device_remove(dev, DM_REMOVE_NORMAL);
133 device_unbind(dev);
134 }
135
136 if (env_get("fdtfile"))
137 return 0;
138
139 /* Ensure that 'env default -a' set correct value to $fdtfile */
140 if (ddr4 && emmc)
141 strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin-v7-emmc.dtb");
142 else if (ddr4)
143 strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin-v7.dtb");
144 else if (emmc)
145 strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin-emmc.dtb");
146 else
147 strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin.dtb");
148
149 /* If $fdtfile was not set explicitly by user then set default value */
150 if (!env_get("fdtfile"))
151 env_set("fdtfile", ptr + sizeof("fdtfile="));
152
153 return 0;
154 }
155 #endif
156
157 /* Board specific AHCI / SATA enable code */
board_ahci_enable(void)158 int board_ahci_enable(void)
159 {
160 struct udevice *dev;
161 int ret;
162 u8 buf[8];
163
164 /* Only DB requres this configuration */
165 if (!of_machine_is_compatible("marvell,armada-3720-db"))
166 return 0;
167
168 /* Configure IO exander PCA9555: 7bit address 0x22 */
169 ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
170 if (ret) {
171 printf("Cannot find PCA9555: %d\n", ret);
172 return 0;
173 }
174
175 ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
176 if (ret) {
177 printf("Failed to read IO expander value via I2C\n");
178 return -EIO;
179 }
180
181 /*
182 * Enable SATA power via IO expander connected via I2C by setting
183 * the corresponding bit to output mode to enable power for SATA
184 */
185 buf[0] &= ~(1 << I2C_IO_REG_0_SATA_OFF);
186 ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
187 if (ret) {
188 printf("Failed to set IO expander via I2C\n");
189 return -EIO;
190 }
191
192 return 0;
193 }
194
195 /* Board specific xHCI enable code */
board_xhci_enable(fdt_addr_t base)196 int board_xhci_enable(fdt_addr_t base)
197 {
198 struct udevice *dev;
199 int ret;
200 u8 buf[8];
201
202 /* Only DB requres this configuration */
203 if (!of_machine_is_compatible("marvell,armada-3720-db"))
204 return 0;
205
206 /* Configure IO exander PCA9555: 7bit address 0x22 */
207 ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
208 if (ret) {
209 printf("Cannot find PCA9555: %d\n", ret);
210 return 0;
211 }
212
213 printf("Enable USB VBUS\n");
214
215 /*
216 * Read configuration (direction) and set VBUS pin as output
217 * (reset pin = output)
218 */
219 ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
220 if (ret) {
221 printf("Failed to read IO expander value via I2C\n");
222 return -EIO;
223 }
224 buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
225 ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
226 if (ret) {
227 printf("Failed to set IO expander via I2C\n");
228 return -EIO;
229 }
230
231 /* Read VBUS output value and disable it */
232 ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
233 if (ret) {
234 printf("Failed to read IO expander value via I2C\n");
235 return -EIO;
236 }
237 buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
238 ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
239 if (ret) {
240 printf("Failed to set IO expander via I2C\n");
241 return -EIO;
242 }
243
244 /*
245 * Required delay for configuration to settle - must wait for
246 * power on port is disabled in case VBUS signal was high,
247 * required 3 seconds delay to let VBUS signal fully settle down
248 */
249 mdelay(3000);
250
251 /* Enable VBUS power: Set output value of VBUS pin as enabled */
252 buf[0] |= (1 << I2C_IO_REG_0_USB_H_OFF);
253 ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
254 if (ret) {
255 printf("Failed to set IO expander via I2C\n");
256 return -EIO;
257 }
258
259 mdelay(500); /* required delay to let output value settle */
260
261 return 0;
262 }
263
264 /* Helper function for accessing switch devices in multi-chip connection mode */
mii_multi_chip_mode_write(struct mii_dev * bus,int dev_smi_addr,int smi_addr,int reg,u16 value)265 static int mii_multi_chip_mode_write(struct mii_dev *bus, int dev_smi_addr,
266 int smi_addr, int reg, u16 value)
267 {
268 u16 smi_cmd = 0;
269
270 if (bus->write(bus, dev_smi_addr, 0,
271 MVEBU_SW_SMI_DATA_REG, value) != 0) {
272 printf("Error writing to the PHY addr=%02x reg=%02x\n",
273 smi_addr, reg);
274 return -EFAULT;
275 }
276
277 smi_cmd = (1 << SW_SMI_CMD_SMI_BUSY_OFF) |
278 (1 << SW_SMI_CMD_SMI_MODE_OFF) |
279 (1 << SW_SMI_CMD_SMI_OP_OFF) |
280 (smi_addr << SW_SMI_CMD_DEV_ADDR_OFF) |
281 (reg << SW_SMI_CMD_REG_ADDR_OFF);
282 if (bus->write(bus, dev_smi_addr, 0,
283 MVEBU_SW_SMI_CMD_REG, smi_cmd) != 0) {
284 printf("Error writing to the PHY addr=%02x reg=%02x\n",
285 smi_addr, reg);
286 return -EFAULT;
287 }
288
289 return 0;
290 }
291
292 /* Bring-up board-specific network stuff */
board_network_enable(struct mii_dev * bus)293 int board_network_enable(struct mii_dev *bus)
294 {
295 if (!of_machine_is_compatible("globalscale,espressobin"))
296 return 0;
297
298 /*
299 * FIXME: remove this code once Topaz driver gets available
300 * A3720 Community Board Only
301 * Configure Topaz switch (88E6341)
302 * Restrict output to ports 1,2,3 only from port 0 (CPU)
303 * Set port 0,1,2,3 to forwarding Mode (through Switch Port registers)
304 */
305 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1),
306 MVEBU_SW_PORT_BASE_VLAN, BIT(0));
307 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2),
308 MVEBU_SW_PORT_BASE_VLAN, BIT(0));
309 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3),
310 MVEBU_SW_PORT_BASE_VLAN, BIT(0));
311
312 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
313 MVEBU_SW_PORT_CTRL_REG, 0x7f);
314 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1),
315 MVEBU_SW_PORT_CTRL_REG, 0x7f);
316 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2),
317 MVEBU_SW_PORT_CTRL_REG, 0x7f);
318 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3),
319 MVEBU_SW_PORT_CTRL_REG, 0x7f);
320
321 /* RGMII Delay on Port 0 (CPU port), force link to 1000Mbps */
322 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
323 MVEBU_SW_LINK_CTRL_REG, 0xe002);
324
325 /* Power up PHY 1, 2, 3 (through Global 2 registers) */
326 mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
327 MVEBU_G2_SMI_PHY_DATA_REG, 0x1140);
328 mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
329 MVEBU_G2_SMI_PHY_CMD_REG, 0x9620);
330 mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
331 MVEBU_G2_SMI_PHY_CMD_REG, 0x9640);
332 mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
333 MVEBU_G2_SMI_PHY_CMD_REG, 0x9660);
334
335 return 0;
336 }
337
338 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
ft_board_setup(void * blob,struct bd_info * bd)339 int ft_board_setup(void *blob, struct bd_info *bd)
340 {
341 int ret;
342 int spi_off;
343 int parts_off;
344 int part_off;
345
346 /* Fill SPI MTD partitions for Linux kernel on Espressobin */
347 if (!of_machine_is_compatible("globalscale,espressobin"))
348 return 0;
349
350 spi_off = fdt_node_offset_by_compatible(blob, -1, "jedec,spi-nor");
351 if (spi_off < 0)
352 return 0;
353
354 /* Do not touch partitions if they are already defined */
355 if (fdt_subnode_offset(blob, spi_off, "partitions") >= 0)
356 return 0;
357
358 parts_off = fdt_add_subnode(blob, spi_off, "partitions");
359 if (parts_off < 0) {
360 printf("Can't add partitions node: %s\n", fdt_strerror(parts_off));
361 return 0;
362 }
363
364 ret = fdt_setprop_string(blob, parts_off, "compatible", "fixed-partitions");
365 if (ret < 0) {
366 printf("Can't set compatible property: %s\n", fdt_strerror(ret));
367 return 0;
368 }
369
370 ret = fdt_setprop_u32(blob, parts_off, "#address-cells", 1);
371 if (ret < 0) {
372 printf("Can't set #address-cells property: %s\n", fdt_strerror(ret));
373 return 0;
374 }
375
376 ret = fdt_setprop_u32(blob, parts_off, "#size-cells", 1);
377 if (ret < 0) {
378 printf("Can't set #size-cells property: %s\n", fdt_strerror(ret));
379 return 0;
380 }
381
382 /* Add u-boot-env partition */
383
384 part_off = fdt_add_subnode(blob, parts_off, "partition@u-boot-env");
385 if (part_off < 0) {
386 printf("Can't add partition@u-boot-env node: %s\n", fdt_strerror(part_off));
387 return 0;
388 }
389
390 ret = fdt_setprop_u32(blob, part_off, "reg", CONFIG_ENV_OFFSET);
391 if (ret < 0) {
392 printf("Can't set partition@u-boot-env reg property: %s\n", fdt_strerror(ret));
393 return 0;
394 }
395
396 ret = fdt_appendprop_u32(blob, part_off, "reg", CONFIG_ENV_SIZE);
397 if (ret < 0) {
398 printf("Can't set partition@u-boot-env reg property: %s\n", fdt_strerror(ret));
399 return 0;
400 }
401
402 ret = fdt_setprop_string(blob, part_off, "label", "u-boot-env");
403 if (ret < 0) {
404 printf("Can't set partition@u-boot-env label property: %s\n", fdt_strerror(ret));
405 return 0;
406 }
407
408 /* Add firmware partition */
409
410 part_off = fdt_add_subnode(blob, parts_off, "partition@firmware");
411 if (part_off < 0) {
412 printf("Can't add partition@firmware node: %s\n", fdt_strerror(part_off));
413 return 0;
414 }
415
416 ret = fdt_setprop_u32(blob, part_off, "reg", 0);
417 if (ret < 0) {
418 printf("Can't set partition@firmware reg property: %s\n", fdt_strerror(ret));
419 return 0;
420 }
421
422 ret = fdt_appendprop_u32(blob, part_off, "reg", CONFIG_ENV_OFFSET);
423 if (ret < 0) {
424 printf("Can't set partition@firmware reg property: %s\n", fdt_strerror(ret));
425 return 0;
426 }
427
428 ret = fdt_setprop_string(blob, part_off, "label", "firmware");
429 if (ret < 0) {
430 printf("Can't set partition@firmware label property: %s\n", fdt_strerror(ret));
431 return 0;
432 }
433
434 return 0;
435 }
436 #endif
437