1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007
4 * Sascha Hauer, Pengutronix
5 *
6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 */
8
9 #include <common.h>
10 #include <init.h>
11 #include <time.h>
12 #include <asm/io.h>
13 #include <div64.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/sys_proto.h>
17
18 /* General purpose timers registers */
19 struct mxc_gpt {
20 unsigned int control;
21 unsigned int prescaler;
22 unsigned int status;
23 unsigned int nouse[6];
24 unsigned int counter;
25 };
26
27 static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
28
29 /* General purpose timers bitfields */
30 #define GPTCR_SWR (1 << 15) /* Software reset */
31 #define GPTCR_24MEN (1 << 10) /* Enable 24MHz clock input */
32 #define GPTCR_FRR (1 << 9) /* Freerun / restart */
33 #define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source 32khz */
34 #define GPTCR_CLKSOURCE_OSC (5 << 6) /* Clock source OSC */
35 #define GPTCR_CLKSOURCE_PRE (1 << 6) /* Clock source PRECLK */
36 #define GPTCR_CLKSOURCE_MASK (0x7 << 6)
37 #define GPTCR_TEN 1 /* Timer enable */
38
39 #define GPTPR_PRESCALER24M_SHIFT 12
40 #define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT)
41
gpt_has_clk_source_osc(void)42 static inline int gpt_has_clk_source_osc(void)
43 {
44 #if defined(CONFIG_MX6)
45 if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
46 is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() ||
47 is_mx6ull() || is_mx6sll())
48 return 1;
49
50 return 0;
51 #else
52 return 0;
53 #endif
54 }
55
gpt_get_clk(void)56 static inline ulong gpt_get_clk(void)
57 {
58 #ifdef CONFIG_MXC_GPT_HCLK
59 if (gpt_has_clk_source_osc())
60 return MXC_HCLK >> 3;
61 else
62 return mxc_get_clock(MXC_IPG_PERCLK);
63 #else
64 return MXC_CLK32;
65 #endif
66 }
67
timer_init(void)68 int timer_init(void)
69 {
70 int i;
71
72 /* setup GP Timer 1 */
73 __raw_writel(GPTCR_SWR, &cur_gpt->control);
74
75 /* We have no udelay by now */
76 __raw_writel(0, &cur_gpt->control);
77
78 i = __raw_readl(&cur_gpt->control);
79 i &= ~GPTCR_CLKSOURCE_MASK;
80
81 #ifdef CONFIG_MXC_GPT_HCLK
82 if (gpt_has_clk_source_osc()) {
83 i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
84
85 /*
86 * For DL/S, SX, UL, ULL, SLL set 24Mhz OSC
87 * Enable bit and prescaler
88 */
89 if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull() ||
90 is_mx6sll()) {
91 i |= GPTCR_24MEN;
92
93 /* Produce 3Mhz clock */
94 __raw_writel((7 << GPTPR_PRESCALER24M_SHIFT),
95 &cur_gpt->prescaler);
96 }
97 } else {
98 i |= GPTCR_CLKSOURCE_PRE | GPTCR_TEN;
99 }
100 #else
101 __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
102 i |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
103 #endif
104 __raw_writel(i, &cur_gpt->control);
105
106 return 0;
107 }
108
timer_read_counter(void)109 unsigned long timer_read_counter(void)
110 {
111 return __raw_readl(&cur_gpt->counter); /* current tick value */
112 }
113
114 /*
115 * This function is derived from PowerPC code (timebase clock frequency).
116 * On ARM it returns the number of timer ticks per second.
117 */
get_tbclk(void)118 ulong get_tbclk(void)
119 {
120 return gpt_get_clk();
121 }
122
123 /*
124 * This function is intended for SHORT delays only.
125 * It will overflow at around 10 seconds @ 400MHz,
126 * or 20 seconds @ 200MHz.
127 */
usec2ticks(unsigned long _usec)128 unsigned long usec2ticks(unsigned long _usec)
129 {
130 unsigned long long usec = _usec;
131
132 usec *= get_tbclk();
133 usec += 999999;
134 do_div(usec, 1000000);
135
136 return usec;
137 }
138