1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2009
4 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
5 */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <dm.h>
10 #include <i2c.h>
11 #include <log.h>
12 #include <malloc.h>
13 #include <pci.h>
14 #include <reset.h>
15 #include <asm/io.h>
16 #include <linux/delay.h>
17 #include "designware_i2c.h"
18 #include <dm/device_compat.h>
19 #include <linux/err.h>
20
21 /*
22 * This assigned unique hex value is constant and is derived from the two ASCII
23 * letters 'DW' followed by a 16-bit unsigned number
24 */
25 #define DW_I2C_COMP_TYPE 0x44570140
26
27 #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
dw_i2c_enable(struct i2c_regs * i2c_base,bool enable)28 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
29 {
30 u32 ena = enable ? IC_ENABLE_0B : 0;
31
32 writel(ena, &i2c_base->ic_enable);
33
34 return 0;
35 }
36 #else
dw_i2c_enable(struct i2c_regs * i2c_base,bool enable)37 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
38 {
39 u32 ena = enable ? IC_ENABLE_0B : 0;
40 int timeout = 100;
41
42 do {
43 writel(ena, &i2c_base->ic_enable);
44 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
45 return 0;
46
47 /*
48 * Wait 10 times the signaling period of the highest I2C
49 * transfer supported by the driver (for 400KHz this is
50 * 25us) as described in the DesignWare I2C databook.
51 */
52 udelay(25);
53 } while (timeout--);
54 printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
55
56 return -ETIMEDOUT;
57 }
58 #endif
59
60 /* High and low times in different speed modes (in ns) */
61 enum {
62 /* SDA Hold Time */
63 DEFAULT_SDA_HOLD_TIME = 300,
64 };
65
66 /**
67 * calc_counts() - Convert a period to a number of IC clk cycles
68 *
69 * @ic_clk: Input clock in Hz
70 * @period_ns: Period to represent, in ns
71 * @return calculated count
72 */
calc_counts(uint ic_clk,uint period_ns)73 static uint calc_counts(uint ic_clk, uint period_ns)
74 {
75 return DIV_ROUND_UP(ic_clk / 1000 * period_ns, NANO_TO_KILO);
76 }
77
78 /**
79 * struct i2c_mode_info - Information about an I2C speed mode
80 *
81 * Each speed mode has its own characteristics. This struct holds these to aid
82 * calculations in dw_i2c_calc_timing().
83 *
84 * @speed: Speed in Hz
85 * @min_scl_lowtime_ns: Minimum value for SCL low period in ns
86 * @min_scl_hightime_ns: Minimum value for SCL high period in ns
87 * @def_rise_time_ns: Default rise time in ns
88 * @def_fall_time_ns: Default fall time in ns
89 */
90 struct i2c_mode_info {
91 int speed;
92 int min_scl_hightime_ns;
93 int min_scl_lowtime_ns;
94 int def_rise_time_ns;
95 int def_fall_time_ns;
96 };
97
98 static const struct i2c_mode_info info_for_mode[] = {
99 [IC_SPEED_MODE_STANDARD] = {
100 I2C_SPEED_STANDARD_RATE,
101 MIN_SS_SCL_HIGHTIME,
102 MIN_SS_SCL_LOWTIME,
103 1000,
104 300,
105 },
106 [IC_SPEED_MODE_FAST] = {
107 I2C_SPEED_FAST_RATE,
108 MIN_FS_SCL_HIGHTIME,
109 MIN_FS_SCL_LOWTIME,
110 300,
111 300,
112 },
113 [IC_SPEED_MODE_FAST_PLUS] = {
114 I2C_SPEED_FAST_PLUS_RATE,
115 MIN_FP_SCL_HIGHTIME,
116 MIN_FP_SCL_LOWTIME,
117 260,
118 500,
119 },
120 [IC_SPEED_MODE_HIGH] = {
121 I2C_SPEED_HIGH_RATE,
122 MIN_HS_SCL_HIGHTIME,
123 MIN_HS_SCL_LOWTIME,
124 120,
125 120,
126 },
127 };
128
129 /**
130 * dw_i2c_calc_timing() - Calculate the timings to use for a bus
131 *
132 * @priv: Bus private information (NULL if not using driver model)
133 * @mode: Speed mode to use
134 * @ic_clk: IC clock speed in Hz
135 * @spk_cnt: Spike-suppression count
136 * @config: Returns value to use
137 * @return 0 if OK, -EINVAL if the calculation failed due to invalid data
138 */
dw_i2c_calc_timing(struct dw_i2c * priv,enum i2c_speed_mode mode,int ic_clk,int spk_cnt,struct dw_i2c_speed_config * config)139 static int dw_i2c_calc_timing(struct dw_i2c *priv, enum i2c_speed_mode mode,
140 int ic_clk, int spk_cnt,
141 struct dw_i2c_speed_config *config)
142 {
143 int fall_cnt, rise_cnt, min_tlow_cnt, min_thigh_cnt;
144 int hcnt, lcnt, period_cnt, diff, tot;
145 int sda_hold_time_ns, scl_rise_time_ns, scl_fall_time_ns;
146 const struct i2c_mode_info *info;
147
148 /*
149 * Find the period, rise, fall, min tlow, and min thigh in terms of
150 * counts of the IC clock
151 */
152 info = &info_for_mode[mode];
153 period_cnt = ic_clk / info->speed;
154 scl_rise_time_ns = priv && priv->scl_rise_time_ns ?
155 priv->scl_rise_time_ns : info->def_rise_time_ns;
156 scl_fall_time_ns = priv && priv->scl_fall_time_ns ?
157 priv->scl_fall_time_ns : info->def_fall_time_ns;
158 rise_cnt = calc_counts(ic_clk, scl_rise_time_ns);
159 fall_cnt = calc_counts(ic_clk, scl_fall_time_ns);
160 min_tlow_cnt = calc_counts(ic_clk, info->min_scl_lowtime_ns);
161 min_thigh_cnt = calc_counts(ic_clk, info->min_scl_hightime_ns);
162
163 debug("dw_i2c: period %d rise %d fall %d tlow %d thigh %d spk %d\n",
164 period_cnt, rise_cnt, fall_cnt, min_tlow_cnt, min_thigh_cnt,
165 spk_cnt);
166
167 /*
168 * Back-solve for hcnt and lcnt according to the following equations:
169 * SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_Fall_time
170 * SCL_Low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time
171 */
172 hcnt = min_thigh_cnt - fall_cnt - 7 - spk_cnt;
173 lcnt = min_tlow_cnt - rise_cnt + fall_cnt - 1;
174
175 if (hcnt < 0 || lcnt < 0) {
176 debug("dw_i2c: bad counts. hcnt = %d lcnt = %d\n", hcnt, lcnt);
177 return -EINVAL;
178 }
179
180 /*
181 * Now add things back up to ensure the period is hit. If it is off,
182 * split the difference and bias to lcnt for remainder
183 */
184 tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
185
186 if (tot < period_cnt) {
187 diff = (period_cnt - tot) / 2;
188 hcnt += diff;
189 lcnt += diff;
190 tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
191 lcnt += period_cnt - tot;
192 }
193
194 config->scl_lcnt = lcnt;
195 config->scl_hcnt = hcnt;
196
197 /* Use internal default unless other value is specified */
198 sda_hold_time_ns = priv && priv->sda_hold_time_ns ?
199 priv->sda_hold_time_ns : DEFAULT_SDA_HOLD_TIME;
200 config->sda_hold = calc_counts(ic_clk, sda_hold_time_ns);
201
202 debug("dw_i2c: hcnt = %d lcnt = %d sda hold = %d\n", hcnt, lcnt,
203 config->sda_hold);
204
205 return 0;
206 }
207
208 /**
209 * calc_bus_speed() - Calculate the config to use for a particular i2c speed
210 *
211 * @priv: Private information for the driver (NULL if not using driver model)
212 * @i2c_base: Registers for the I2C controller
213 * @speed: Required i2c speed in Hz
214 * @bus_clk: Input clock to the I2C controller in Hz (e.g. IC_CLK)
215 * @config: Returns the config to use for this speed
216 * @return 0 if OK, -ve on error
217 */
calc_bus_speed(struct dw_i2c * priv,struct i2c_regs * regs,int speed,ulong bus_clk,struct dw_i2c_speed_config * config)218 static int calc_bus_speed(struct dw_i2c *priv, struct i2c_regs *regs, int speed,
219 ulong bus_clk, struct dw_i2c_speed_config *config)
220 {
221 const struct dw_scl_sda_cfg *scl_sda_cfg = NULL;
222 enum i2c_speed_mode i2c_spd;
223 int spk_cnt;
224 int ret;
225
226 if (priv)
227 scl_sda_cfg = priv->scl_sda_cfg;
228 /* Allow high speed if there is no config, or the config allows it */
229 if (speed >= I2C_SPEED_HIGH_RATE)
230 i2c_spd = IC_SPEED_MODE_HIGH;
231 else if (speed >= I2C_SPEED_FAST_PLUS_RATE)
232 i2c_spd = IC_SPEED_MODE_FAST_PLUS;
233 else if (speed >= I2C_SPEED_FAST_RATE)
234 i2c_spd = IC_SPEED_MODE_FAST;
235 else
236 i2c_spd = IC_SPEED_MODE_STANDARD;
237
238 /* Check is high speed possible and fall back to fast mode if not */
239 if (i2c_spd == IC_SPEED_MODE_HIGH) {
240 u32 comp_param1;
241
242 comp_param1 = readl(®s->comp_param1);
243 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
244 != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH)
245 i2c_spd = IC_SPEED_MODE_FAST;
246 }
247
248 /* Get the proper spike-suppression count based on target speed */
249 if (!priv || !priv->has_spk_cnt)
250 spk_cnt = 0;
251 else if (i2c_spd >= IC_SPEED_MODE_HIGH)
252 spk_cnt = readl(®s->hs_spklen);
253 else
254 spk_cnt = readl(®s->fs_spklen);
255 if (scl_sda_cfg) {
256 config->sda_hold = scl_sda_cfg->sda_hold;
257 if (i2c_spd == IC_SPEED_MODE_STANDARD) {
258 config->scl_hcnt = scl_sda_cfg->ss_hcnt;
259 config->scl_lcnt = scl_sda_cfg->ss_lcnt;
260 } else if (i2c_spd == IC_SPEED_MODE_HIGH) {
261 config->scl_hcnt = scl_sda_cfg->hs_hcnt;
262 config->scl_lcnt = scl_sda_cfg->hs_lcnt;
263 } else {
264 config->scl_hcnt = scl_sda_cfg->fs_hcnt;
265 config->scl_lcnt = scl_sda_cfg->fs_lcnt;
266 }
267 } else {
268 ret = dw_i2c_calc_timing(priv, i2c_spd, bus_clk, spk_cnt,
269 config);
270 if (ret)
271 return log_msg_ret("gen_confg", ret);
272 }
273 config->speed_mode = i2c_spd;
274
275 return 0;
276 }
277
278 /**
279 * _dw_i2c_set_bus_speed() - Set the i2c speed
280 *
281 * @priv: Private information for the driver (NULL if not using driver model)
282 * @i2c_base: Registers for the I2C controller
283 * @speed: Required i2c speed in Hz
284 * @bus_clk: Input clock to the I2C controller in Hz (e.g. IC_CLK)
285 * @return 0 if OK, -ve on error
286 */
_dw_i2c_set_bus_speed(struct dw_i2c * priv,struct i2c_regs * i2c_base,unsigned int speed,unsigned int bus_clk)287 static int _dw_i2c_set_bus_speed(struct dw_i2c *priv, struct i2c_regs *i2c_base,
288 unsigned int speed, unsigned int bus_clk)
289 {
290 struct dw_i2c_speed_config config;
291 unsigned int cntl;
292 unsigned int ena;
293 int ret;
294
295 ret = calc_bus_speed(priv, i2c_base, speed, bus_clk, &config);
296 if (ret)
297 return ret;
298
299 /* Get enable setting for restore later */
300 ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;
301
302 /* to set speed cltr must be disabled */
303 dw_i2c_enable(i2c_base, false);
304
305 cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
306
307 switch (config.speed_mode) {
308 case IC_SPEED_MODE_HIGH:
309 cntl |= IC_CON_SPD_HS;
310 writel(config.scl_hcnt, &i2c_base->ic_hs_scl_hcnt);
311 writel(config.scl_lcnt, &i2c_base->ic_hs_scl_lcnt);
312 break;
313 case IC_SPEED_MODE_STANDARD:
314 cntl |= IC_CON_SPD_SS;
315 writel(config.scl_hcnt, &i2c_base->ic_ss_scl_hcnt);
316 writel(config.scl_lcnt, &i2c_base->ic_ss_scl_lcnt);
317 break;
318 case IC_SPEED_MODE_FAST_PLUS:
319 case IC_SPEED_MODE_FAST:
320 default:
321 cntl |= IC_CON_SPD_FS;
322 writel(config.scl_hcnt, &i2c_base->ic_fs_scl_hcnt);
323 writel(config.scl_lcnt, &i2c_base->ic_fs_scl_lcnt);
324 break;
325 }
326
327 writel(cntl, &i2c_base->ic_con);
328
329 /* Configure SDA Hold Time if required */
330 if (config.sda_hold)
331 writel(config.sda_hold, &i2c_base->ic_sda_hold);
332
333 /* Restore back i2c now speed set */
334 if (ena == IC_ENABLE_0B)
335 dw_i2c_enable(i2c_base, true);
336
337 return 0;
338 }
339
340 /*
341 * i2c_setaddress - Sets the target slave address
342 * @i2c_addr: target i2c address
343 *
344 * Sets the target slave address.
345 */
i2c_setaddress(struct i2c_regs * i2c_base,unsigned int i2c_addr)346 static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
347 {
348 /* Disable i2c */
349 dw_i2c_enable(i2c_base, false);
350
351 writel(i2c_addr, &i2c_base->ic_tar);
352
353 /* Enable i2c */
354 dw_i2c_enable(i2c_base, true);
355 }
356
357 /*
358 * i2c_flush_rxfifo - Flushes the i2c RX FIFO
359 *
360 * Flushes the i2c RX FIFO
361 */
i2c_flush_rxfifo(struct i2c_regs * i2c_base)362 static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
363 {
364 while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
365 readl(&i2c_base->ic_cmd_data);
366 }
367
368 /*
369 * i2c_wait_for_bb - Waits for bus busy
370 *
371 * Waits for bus busy
372 */
i2c_wait_for_bb(struct i2c_regs * i2c_base)373 static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
374 {
375 unsigned long start_time_bb = get_timer(0);
376
377 while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
378 !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
379
380 /* Evaluate timeout */
381 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
382 return 1;
383 }
384
385 return 0;
386 }
387
i2c_xfer_init(struct i2c_regs * i2c_base,uchar chip,uint addr,int alen)388 static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
389 int alen)
390 {
391 if (i2c_wait_for_bb(i2c_base))
392 return 1;
393
394 i2c_setaddress(i2c_base, chip);
395 while (alen) {
396 alen--;
397 /* high byte address going out first */
398 writel((addr >> (alen * 8)) & 0xff,
399 &i2c_base->ic_cmd_data);
400 }
401 return 0;
402 }
403
i2c_xfer_finish(struct i2c_regs * i2c_base)404 static int i2c_xfer_finish(struct i2c_regs *i2c_base)
405 {
406 ulong start_stop_det = get_timer(0);
407
408 while (1) {
409 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
410 readl(&i2c_base->ic_clr_stop_det);
411 break;
412 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
413 break;
414 }
415 }
416
417 if (i2c_wait_for_bb(i2c_base)) {
418 printf("Timed out waiting for bus\n");
419 return 1;
420 }
421
422 i2c_flush_rxfifo(i2c_base);
423
424 return 0;
425 }
426
427 /*
428 * i2c_read - Read from i2c memory
429 * @chip: target i2c address
430 * @addr: address to read from
431 * @alen:
432 * @buffer: buffer for read data
433 * @len: no of bytes to be read
434 *
435 * Read from i2c memory.
436 */
__dw_i2c_read(struct i2c_regs * i2c_base,u8 dev,uint addr,int alen,u8 * buffer,int len)437 static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
438 int alen, u8 *buffer, int len)
439 {
440 unsigned long start_time_rx;
441 unsigned int active = 0;
442
443 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
444 /*
445 * EEPROM chips that implement "address overflow" are ones
446 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
447 * address and the extra bits end up in the "chip address"
448 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
449 * four 256 byte chips.
450 *
451 * Note that we consider the length of the address field to
452 * still be one byte because the extra address bits are
453 * hidden in the chip address.
454 */
455 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
456 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
457
458 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
459 addr);
460 #endif
461
462 if (i2c_xfer_init(i2c_base, dev, addr, alen))
463 return 1;
464
465 start_time_rx = get_timer(0);
466 while (len) {
467 if (!active) {
468 /*
469 * Avoid writing to ic_cmd_data multiple times
470 * in case this loop spins too quickly and the
471 * ic_status RFNE bit isn't set after the first
472 * write. Subsequent writes to ic_cmd_data can
473 * trigger spurious i2c transfer.
474 */
475 if (len == 1)
476 writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
477 else
478 writel(IC_CMD, &i2c_base->ic_cmd_data);
479 active = 1;
480 }
481
482 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
483 *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
484 len--;
485 start_time_rx = get_timer(0);
486 active = 0;
487 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
488 return 1;
489 }
490 }
491
492 return i2c_xfer_finish(i2c_base);
493 }
494
495 /*
496 * i2c_write - Write to i2c memory
497 * @chip: target i2c address
498 * @addr: address to read from
499 * @alen:
500 * @buffer: buffer for read data
501 * @len: no of bytes to be read
502 *
503 * Write to i2c memory.
504 */
__dw_i2c_write(struct i2c_regs * i2c_base,u8 dev,uint addr,int alen,u8 * buffer,int len)505 static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
506 int alen, u8 *buffer, int len)
507 {
508 int nb = len;
509 unsigned long start_time_tx;
510
511 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
512 /*
513 * EEPROM chips that implement "address overflow" are ones
514 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
515 * address and the extra bits end up in the "chip address"
516 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
517 * four 256 byte chips.
518 *
519 * Note that we consider the length of the address field to
520 * still be one byte because the extra address bits are
521 * hidden in the chip address.
522 */
523 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
524 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
525
526 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
527 addr);
528 #endif
529
530 if (i2c_xfer_init(i2c_base, dev, addr, alen))
531 return 1;
532
533 start_time_tx = get_timer(0);
534 while (len) {
535 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
536 if (--len == 0) {
537 writel(*buffer | IC_STOP,
538 &i2c_base->ic_cmd_data);
539 } else {
540 writel(*buffer, &i2c_base->ic_cmd_data);
541 }
542 buffer++;
543 start_time_tx = get_timer(0);
544
545 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
546 printf("Timed out. i2c write Failed\n");
547 return 1;
548 }
549 }
550
551 return i2c_xfer_finish(i2c_base);
552 }
553
554 /*
555 * __dw_i2c_init - Init function
556 * @speed: required i2c speed
557 * @slaveaddr: slave address for the device
558 *
559 * Initialization function.
560 */
__dw_i2c_init(struct i2c_regs * i2c_base,int speed,int slaveaddr)561 static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
562 {
563 int ret;
564
565 /* Disable i2c */
566 ret = dw_i2c_enable(i2c_base, false);
567 if (ret)
568 return ret;
569
570 writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
571 &i2c_base->ic_con);
572 writel(IC_RX_TL, &i2c_base->ic_rx_tl);
573 writel(IC_TX_TL, &i2c_base->ic_tx_tl);
574 writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
575 #ifndef CONFIG_DM_I2C
576 _dw_i2c_set_bus_speed(NULL, i2c_base, speed, IC_CLK);
577 writel(slaveaddr, &i2c_base->ic_sar);
578 #endif
579
580 /* Enable i2c */
581 ret = dw_i2c_enable(i2c_base, true);
582 if (ret)
583 return ret;
584
585 return 0;
586 }
587
588 #ifndef CONFIG_DM_I2C
589 /*
590 * The legacy I2C functions. These need to get removed once
591 * all users of this driver are converted to DM.
592 */
i2c_get_base(struct i2c_adapter * adap)593 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
594 {
595 switch (adap->hwadapnr) {
596 #if CONFIG_SYS_I2C_BUS_MAX >= 4
597 case 3:
598 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
599 #endif
600 #if CONFIG_SYS_I2C_BUS_MAX >= 3
601 case 2:
602 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
603 #endif
604 #if CONFIG_SYS_I2C_BUS_MAX >= 2
605 case 1:
606 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
607 #endif
608 case 0:
609 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
610 default:
611 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
612 }
613
614 return NULL;
615 }
616
dw_i2c_set_bus_speed(struct i2c_adapter * adap,unsigned int speed)617 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
618 unsigned int speed)
619 {
620 adap->speed = speed;
621 return _dw_i2c_set_bus_speed(NULL, i2c_get_base(adap), speed, IC_CLK);
622 }
623
dw_i2c_init(struct i2c_adapter * adap,int speed,int slaveaddr)624 static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
625 {
626 __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
627 }
628
dw_i2c_read(struct i2c_adapter * adap,u8 dev,uint addr,int alen,u8 * buffer,int len)629 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
630 int alen, u8 *buffer, int len)
631 {
632 return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
633 }
634
dw_i2c_write(struct i2c_adapter * adap,u8 dev,uint addr,int alen,u8 * buffer,int len)635 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
636 int alen, u8 *buffer, int len)
637 {
638 return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
639 }
640
641 /* dw_i2c_probe - Probe the i2c chip */
dw_i2c_probe(struct i2c_adapter * adap,u8 dev)642 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
643 {
644 struct i2c_regs *i2c_base = i2c_get_base(adap);
645 u32 tmp;
646 int ret;
647
648 /*
649 * Try to read the first location of the chip.
650 */
651 ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
652 if (ret)
653 dw_i2c_init(adap, adap->speed, adap->slaveaddr);
654
655 return ret;
656 }
657
658 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
659 dw_i2c_write, dw_i2c_set_bus_speed,
660 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
661
662 #if CONFIG_SYS_I2C_BUS_MAX >= 2
663 U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
664 dw_i2c_write, dw_i2c_set_bus_speed,
665 CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
666 #endif
667
668 #if CONFIG_SYS_I2C_BUS_MAX >= 3
669 U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
670 dw_i2c_write, dw_i2c_set_bus_speed,
671 CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
672 #endif
673
674 #if CONFIG_SYS_I2C_BUS_MAX >= 4
675 U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
676 dw_i2c_write, dw_i2c_set_bus_speed,
677 CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
678 #endif
679
680 #else /* CONFIG_DM_I2C */
681 /* The DM I2C functions */
682
683 static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
684 int nmsgs)
685 {
686 struct dw_i2c *i2c = dev_get_priv(bus);
687 int ret;
688
689 debug("i2c_xfer: %d messages\n", nmsgs);
690 for (; nmsgs > 0; nmsgs--, msg++) {
691 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
692 if (msg->flags & I2C_M_RD) {
693 ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
694 msg->buf, msg->len);
695 } else {
696 ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
697 msg->buf, msg->len);
698 }
699 if (ret) {
700 debug("i2c_write: error sending\n");
701 return -EREMOTEIO;
702 }
703 }
704
705 return 0;
706 }
707
708 static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
709 {
710 struct dw_i2c *i2c = dev_get_priv(bus);
711 ulong rate;
712
713 #if CONFIG_IS_ENABLED(CLK)
714 rate = clk_get_rate(&i2c->clk);
715 if (IS_ERR_VALUE(rate))
716 return -EINVAL;
717 #else
718 rate = IC_CLK;
719 #endif
720 return _dw_i2c_set_bus_speed(i2c, i2c->regs, speed, rate);
721 }
722
723 static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
724 uint chip_flags)
725 {
726 struct dw_i2c *i2c = dev_get_priv(bus);
727 struct i2c_regs *i2c_base = i2c->regs;
728 u32 tmp;
729 int ret;
730
731 /* Try to read the first location of the chip */
732 ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
733 if (ret)
734 __dw_i2c_init(i2c_base, 0, 0);
735
736 return ret;
737 }
738
739 int designware_i2c_ofdata_to_platdata(struct udevice *bus)
740 {
741 struct dw_i2c *priv = dev_get_priv(bus);
742 int ret;
743
744 if (!priv->regs)
745 priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
746 dev_read_u32(bus, "i2c-scl-rising-time-ns", &priv->scl_rise_time_ns);
747 dev_read_u32(bus, "i2c-scl-falling-time-ns", &priv->scl_fall_time_ns);
748 dev_read_u32(bus, "i2c-sda-hold-time-ns", &priv->sda_hold_time_ns);
749
750 ret = reset_get_bulk(bus, &priv->resets);
751 if (ret)
752 dev_warn(bus, "Can't get reset: %d\n", ret);
753 else
754 reset_deassert_bulk(&priv->resets);
755
756 #if CONFIG_IS_ENABLED(CLK)
757 ret = clk_get_by_index(bus, 0, &priv->clk);
758 if (ret)
759 return ret;
760
761 ret = clk_enable(&priv->clk);
762 if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
763 clk_free(&priv->clk);
764 dev_err(bus, "failed to enable clock\n");
765 return ret;
766 }
767 #endif
768
769 return 0;
770 }
771
772 int designware_i2c_probe(struct udevice *bus)
773 {
774 struct dw_i2c *priv = dev_get_priv(bus);
775 uint comp_type;
776
777 comp_type = readl(&priv->regs->comp_type);
778 if (comp_type != DW_I2C_COMP_TYPE) {
779 log_err("I2C bus %s has unknown type %#x\n", bus->name,
780 comp_type);
781 return -ENXIO;
782 }
783
784 log_info("I2C bus %s version %#x\n", bus->name,
785 readl(&priv->regs->comp_version));
786
787 return __dw_i2c_init(priv->regs, 0, 0);
788 }
789
790 int designware_i2c_remove(struct udevice *dev)
791 {
792 struct dw_i2c *priv = dev_get_priv(dev);
793
794 #if CONFIG_IS_ENABLED(CLK)
795 clk_disable(&priv->clk);
796 clk_free(&priv->clk);
797 #endif
798
799 return reset_release_bulk(&priv->resets);
800 }
801
802 const struct dm_i2c_ops designware_i2c_ops = {
803 .xfer = designware_i2c_xfer,
804 .probe_chip = designware_i2c_probe_chip,
805 .set_bus_speed = designware_i2c_set_bus_speed,
806 };
807
808 static const struct udevice_id designware_i2c_ids[] = {
809 { .compatible = "snps,designware-i2c" },
810 { }
811 };
812
813 U_BOOT_DRIVER(i2c_designware) = {
814 .name = "i2c_designware",
815 .id = UCLASS_I2C,
816 .of_match = designware_i2c_ids,
817 .ofdata_to_platdata = designware_i2c_ofdata_to_platdata,
818 .probe = designware_i2c_probe,
819 .priv_auto_alloc_size = sizeof(struct dw_i2c),
820 .remove = designware_i2c_remove,
821 .flags = DM_FLAG_OS_PREPARE,
822 .ops = &designware_i2c_ops,
823 };
824
825 #endif /* CONFIG_DM_I2C */
826