1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015-2016 Marvell International Ltd.
4 */
5
6 #include <common.h>
7 #include <fdtdec.h>
8 #include <log.h>
9 #include <asm/io.h>
10 #include <asm/arch/cpu.h>
11 #include <asm/arch/soc.h>
12 #include <linux/delay.h>
13
14 #include "comphy_a3700.h"
15
16 DECLARE_GLOBAL_DATA_PTR;
17
18 struct comphy_mux_data a3700_comphy_mux_data[] = {
19 /* Lane 0 */
20 {
21 4,
22 {
23 { PHY_TYPE_UNCONNECTED, 0x0 },
24 { PHY_TYPE_SGMII1, 0x0 },
25 { PHY_TYPE_USB3_HOST0, 0x1 },
26 { PHY_TYPE_USB3_DEVICE, 0x1 }
27 }
28 },
29 /* Lane 1 */
30 {
31 3,
32 {
33 { PHY_TYPE_UNCONNECTED, 0x0},
34 { PHY_TYPE_SGMII0, 0x0},
35 { PHY_TYPE_PEX0, 0x1}
36 }
37 },
38 /* Lane 2 */
39 {
40 4,
41 {
42 { PHY_TYPE_UNCONNECTED, 0x0},
43 { PHY_TYPE_SATA0, 0x0},
44 { PHY_TYPE_USB3_HOST0, 0x1},
45 { PHY_TYPE_USB3_DEVICE, 0x1}
46 }
47 },
48 };
49
50 struct sgmii_phy_init_data_fix {
51 u16 addr;
52 u16 value;
53 };
54
55 /* Changes to 40M1G25 mode data required for running 40M3G125 init mode */
56 static struct sgmii_phy_init_data_fix sgmii_phy_init_fix[] = {
57 {0x005, 0x07CC}, {0x015, 0x0000}, {0x01B, 0x0000}, {0x01D, 0x0000},
58 {0x01E, 0x0000}, {0x01F, 0x0000}, {0x020, 0x0000}, {0x021, 0x0030},
59 {0x026, 0x0888}, {0x04D, 0x0152}, {0x04F, 0xA020}, {0x050, 0x07CC},
60 {0x053, 0xE9CA}, {0x055, 0xBD97}, {0x071, 0x3015}, {0x076, 0x03AA},
61 {0x07C, 0x0FDF}, {0x0C2, 0x3030}, {0x0C3, 0x8000}, {0x0E2, 0x5550},
62 {0x0E3, 0x12A4}, {0x0E4, 0x7D00}, {0x0E6, 0x0C83}, {0x101, 0xFCC0},
63 {0x104, 0x0C10}
64 };
65
66 /* 40M1G25 mode init data */
67 static u16 sgmii_phy_init[512] = {
68 /* 0 1 2 3 4 5 6 7 */
69 /*-----------------------------------------------------------*/
70 /* 8 9 A B C D E F */
71 0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26, /* 00 */
72 0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52, /* 08 */
73 0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000, /* 10 */
74 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF, /* 18 */
75 0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000, /* 20 */
76 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, /* 28 */
77 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */
78 0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100, /* 38 */
79 0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00, /* 40 */
80 0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A, /* 48 */
81 0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001, /* 50 */
82 0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF, /* 58 */
83 0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000, /* 60 */
84 0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002, /* 68 */
85 0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780, /* 70 */
86 0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000, /* 78 */
87 0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000, /* 80 */
88 0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210, /* 88 */
89 0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F, /* 90 */
90 0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651, /* 98 */
91 0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000, /* A0 */
92 0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* A8 */
93 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* B0 */
94 0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, /* B8 */
95 0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003, /* C0 */
96 0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000, /* C8 */
97 0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00, /* D0 */
98 0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000, /* D8 */
99 0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541, /* E0 */
100 0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200, /* E8 */
101 0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000, /* F0 */
102 0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000, /* F8 */
103 0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000, /*100 */
104 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*108 */
105 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000, /*110 */
106 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*118 */
107 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*120 */
108 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*128 */
109 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*130 */
110 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*138 */
111 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*140 */
112 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*148 */
113 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*150 */
114 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*158 */
115 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*160 */
116 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*168 */
117 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*170 */
118 0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000, /*178 */
119 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*180 */
120 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*188 */
121 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*190 */
122 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*198 */
123 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */
124 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */
125 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */
126 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */
127 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */
128 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */
129 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */
130 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */
131 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */
132 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */
133 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */
134 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */
135 };
136
137 /*
138 * comphy_poll_reg
139 *
140 * return: 1 on success, 0 on timeout
141 */
comphy_poll_reg(void * addr,u32 val,u32 mask,u8 op_type)142 static u32 comphy_poll_reg(void *addr, u32 val, u32 mask, u8 op_type)
143 {
144 u32 rval = 0xDEAD, timeout;
145
146 for (timeout = PLL_LOCK_TIMEOUT; timeout > 0; timeout--) {
147 if (op_type == POLL_16B_REG)
148 rval = readw(addr); /* 16 bit */
149 else
150 rval = readl(addr) ; /* 32 bit */
151
152 if ((rval & mask) == val)
153 return 1;
154
155 udelay(10000);
156 }
157
158 debug("Time out waiting (%p = %#010x)\n", addr, rval);
159 return 0;
160 }
161
162 /*
163 * comphy_pcie_power_up
164 *
165 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
166 */
comphy_pcie_power_up(u32 speed,u32 invert)167 static int comphy_pcie_power_up(u32 speed, u32 invert)
168 {
169 int ret;
170
171 debug_enter();
172
173 /*
174 * 1. Enable max PLL.
175 */
176 reg_set16(phy_addr(PCIE, LANE_CFG1), bf_use_max_pll_rate, 0);
177
178 /*
179 * 2. Select 20 bit SERDES interface.
180 */
181 reg_set16(phy_addr(PCIE, GLOB_CLK_SRC_LO), bf_cfg_sel_20b, 0);
182
183 /*
184 * 3. Force to use reg setting for PCIe mode
185 */
186 reg_set16(phy_addr(PCIE, MISC_REG1), bf_sel_bits_pcie_force, 0);
187
188 /*
189 * 4. Change RX wait
190 */
191 reg_set16(phy_addr(PCIE, PWR_MGM_TIM1), 0x10C, 0xFFFF);
192
193 /*
194 * 5. Enable idle sync
195 */
196 reg_set16(phy_addr(PCIE, UNIT_CTRL), 0x60 | rb_idle_sync_en, 0xFFFF);
197
198 /*
199 * 6. Enable the output of 100M/125M/500M clock
200 */
201 reg_set16(phy_addr(PCIE, MISC_REG0),
202 0xA00D | rb_clk500m_en | rb_clk100m_125m_en, 0xFFFF);
203
204 /*
205 * 7. Enable TX
206 */
207 reg_set(PCIE_REF_CLK_ADDR, 0x1342, 0xFFFFFFFF);
208
209 /*
210 * 8. Check crystal jumper setting and program the Power and PLL
211 * Control accordingly
212 */
213 if (get_ref_clk() == 40) {
214 /* 40 MHz */
215 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC63, 0xFFFF);
216 } else {
217 /* 25 MHz */
218 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC62, 0xFFFF);
219 }
220
221 /*
222 * 9. Override Speed_PLL value and use MAC PLL
223 */
224 reg_set16(phy_addr(PCIE, KVCO_CAL_CTRL), 0x0040 | rb_use_max_pll_rate,
225 0xFFFF);
226
227 /*
228 * 10. Check the Polarity invert bit
229 */
230 if (invert & PHY_POLARITY_TXD_INVERT)
231 reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0);
232
233 if (invert & PHY_POLARITY_RXD_INVERT)
234 reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_rxd_inv, 0);
235
236 /*
237 * 11. Release SW reset
238 */
239 reg_set16(phy_addr(PCIE, GLOB_PHY_CTRL0),
240 rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32,
241 bf_soft_rst | bf_mode_refdiv);
242
243 /* Wait for > 55 us to allow PCLK be enabled */
244 udelay(PLL_SET_DELAY_US);
245
246 /* Assert PCLK enabled */
247 ret = comphy_poll_reg(phy_addr(PCIE, LANE_STAT1), /* address */
248 rb_txdclk_pclk_en, /* value */
249 rb_txdclk_pclk_en, /* mask */
250 POLL_16B_REG); /* 16bit */
251 if (!ret)
252 printf("Failed to lock PCIe PLL\n");
253
254 debug_exit();
255
256 /* Return the status of the PLL */
257 return ret;
258 }
259
260 /*
261 * reg_set_indirect
262 *
263 * return: void
264 */
reg_set_indirect(u32 reg,u16 data,u16 mask)265 static void reg_set_indirect(u32 reg, u16 data, u16 mask)
266 {
267 reg_set(rh_vsreg_addr, reg, 0xFFFFFFFF);
268 reg_set(rh_vsreg_data, data, mask);
269 }
270
271 /*
272 * comphy_sata_power_up
273 *
274 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
275 */
comphy_sata_power_up(void)276 static int comphy_sata_power_up(void)
277 {
278 int ret;
279
280 debug_enter();
281
282 /*
283 * 0. Swap SATA TX lines
284 */
285 reg_set_indirect(vphy_sync_pattern_reg, bs_txd_inv, bs_txd_inv);
286
287 /*
288 * 1. Select 40-bit data width width
289 */
290 reg_set_indirect(vphy_loopback_reg0, 0x800, bs_phyintf_40bit);
291
292 /*
293 * 2. Select reference clock and PHY mode (SATA)
294 */
295 if (get_ref_clk() == 40) {
296 /* 40 MHz */
297 reg_set_indirect(vphy_power_reg0, 0x3, 0x00FF);
298 } else {
299 /* 20 MHz */
300 reg_set_indirect(vphy_power_reg0, 0x1, 0x00FF);
301 }
302
303 /*
304 * 3. Use maximum PLL rate (no power save)
305 */
306 reg_set_indirect(vphy_calctl_reg, bs_max_pll_rate, bs_max_pll_rate);
307
308 /*
309 * 4. Reset reserved bit (??)
310 */
311 reg_set_indirect(vphy_reserve_reg, 0, bs_phyctrl_frm_pin);
312
313 /*
314 * 5. Set vendor-specific configuration (??)
315 */
316 reg_set(rh_vs0_a, vsata_ctrl_reg, 0xFFFFFFFF);
317 reg_set(rh_vs0_d, bs_phy_pu_pll, bs_phy_pu_pll);
318
319 /* Wait for > 55 us to allow PLL be enabled */
320 udelay(PLL_SET_DELAY_US);
321
322 /* Assert SATA PLL enabled */
323 reg_set(rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF);
324 ret = comphy_poll_reg(rh_vsreg_data, /* address */
325 bs_pll_ready_tx, /* value */
326 bs_pll_ready_tx, /* mask */
327 POLL_32B_REG); /* 32bit */
328 if (!ret)
329 printf("Failed to lock SATA PLL\n");
330
331 debug_exit();
332
333 return ret;
334 }
335
336 /*
337 * usb3_reg_set16
338 *
339 * return: void
340 */
usb3_reg_set16(u32 reg,u16 data,u16 mask,u32 lane)341 static void usb3_reg_set16(u32 reg, u16 data, u16 mask, u32 lane)
342 {
343 /*
344 * When Lane 2 PHY is for USB3, access the PHY registers
345 * through indirect Address and Data registers INDIR_ACC_PHY_ADDR
346 * (RD00E0178h [31:0]) and INDIR_ACC_PHY_DATA (RD00E017Ch [31:0])
347 * within the SATA Host Controller registers, Lane 2 base register
348 * offset is 0x200
349 */
350
351 if (lane == 2)
352 reg_set_indirect(USB3PHY_LANE2_REG_BASE_OFFSET + reg, data,
353 mask);
354 else
355 reg_set16(phy_addr(USB3, reg), data, mask);
356 }
357
358 /*
359 * comphy_usb3_power_up
360 *
361 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
362 */
comphy_usb3_power_up(u32 lane,u32 type,u32 speed,u32 invert)363 static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert)
364 {
365 int ret;
366
367 debug_enter();
368
369 /*
370 * 1. Power up OTG module
371 */
372 reg_set(USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0);
373
374 /*
375 * 2. Set counter for 100us pulse in USB3 Host and Device
376 * restore default burst size limit (Reference Clock 31:24)
377 */
378 reg_set(USB3_CTRPUL_VAL_REG, 0x8 << 24, rb_usb3_ctr_100ns);
379
380
381 /* 0xd005c300 = 0x1001 */
382 /* set PRD_TXDEEMPH (3.5db de-emph) */
383 usb3_reg_set16(LANE_CFG0, 0x1, 0xFF, lane);
384
385 /*
386 * Set BIT0: enable transmitter in high impedance mode
387 * Set BIT[3:4]: delay 2 clock cycles for HiZ off latency
388 * Set BIT6: Tx detect Rx at HiZ mode
389 * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db
390 * together with bit 0 of COMPHY_REG_LANE_CFG0_ADDR
391 * register
392 */
393 usb3_reg_set16(LANE_CFG1,
394 tx_det_rx_mode | gen2_tx_data_dly_deft
395 | tx_elec_idle_mode_en,
396 prd_txdeemph1_mask | tx_det_rx_mode
397 | gen2_tx_data_dly_mask | tx_elec_idle_mode_en, lane);
398
399 /* 0xd005c310 = 0x93: set Spread Spectrum Clock Enabled */
400 usb3_reg_set16(LANE_CFG4, bf_spread_spectrum_clock_en, 0x80, lane);
401
402 /*
403 * set Override Margining Controls From the MAC: Use margining signals
404 * from lane configuration
405 */
406 usb3_reg_set16(TEST_MODE_CTRL, rb_mode_margin_override, 0xFFFF, lane);
407
408 /* set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles */
409 /* set Mode Clock Source = PCLK is generated from REFCLK */
410 usb3_reg_set16(GLOB_CLK_SRC_LO, 0x0, 0xFF, lane);
411
412 /* set G2 Spread Spectrum Clock Amplitude at 4K */
413 usb3_reg_set16(GEN2_SETTINGS_2, g2_tx_ssc_amp, 0xF000, lane);
414
415 /*
416 * unset G3 Spread Spectrum Clock Amplitude & set G3 TX and RX Register
417 * Master Current Select
418 */
419 usb3_reg_set16(GEN2_SETTINGS_3, 0x0, 0xFFFF, lane);
420
421 /*
422 * 3. Check crystal jumper setting and program the Power and PLL
423 * Control accordingly
424 * 4. Change RX wait
425 */
426 if (get_ref_clk() == 40) {
427 /* 40 MHz */
428 usb3_reg_set16(PWR_PLL_CTRL, 0xFCA3, 0xFFFF, lane);
429 usb3_reg_set16(PWR_MGM_TIM1, 0x10C, 0xFFFF, lane);
430 } else {
431 /* 25 MHz */
432 usb3_reg_set16(PWR_PLL_CTRL, 0xFCA2, 0xFFFF, lane);
433 usb3_reg_set16(PWR_MGM_TIM1, 0x107, 0xFFFF, lane);
434 }
435
436 /*
437 * 5. Enable idle sync
438 */
439 usb3_reg_set16(UNIT_CTRL, 0x60 | rb_idle_sync_en, 0xFFFF, lane);
440
441 /*
442 * 6. Enable the output of 500M clock
443 */
444 usb3_reg_set16(MISC_REG0, 0xA00D | rb_clk500m_en, 0xFFFF, lane);
445
446 /*
447 * 7. Set 20-bit data width
448 */
449 usb3_reg_set16(DIG_LB_EN, 0x0400, 0xFFFF, lane);
450
451 /*
452 * 8. Override Speed_PLL value and use MAC PLL
453 */
454 usb3_reg_set16(KVCO_CAL_CTRL, 0x0040 | rb_use_max_pll_rate, 0xFFFF,
455 lane);
456
457 /*
458 * 9. Check the Polarity invert bit
459 */
460 if (invert & PHY_POLARITY_TXD_INVERT)
461 usb3_reg_set16(SYNC_PATTERN, phy_txd_inv, 0, lane);
462
463 if (invert & PHY_POLARITY_RXD_INVERT)
464 usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0, lane);
465
466 /*
467 * 10. Set max speed generation to USB3.0 5Gbps
468 */
469 usb3_reg_set16(SYNC_MASK_GEN, 0x0400, 0x0C00, lane);
470
471 /*
472 * 11. Set capacitor value for FFE gain peaking to 0xF
473 */
474 usb3_reg_set16(GEN3_SETTINGS_3, 0xF, 0xF, lane);
475
476 /*
477 * 12. Release SW reset
478 */
479 usb3_reg_set16(GLOB_PHY_CTRL0,
480 rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32
481 | 0x20, 0xFFFF, lane);
482
483 /* Wait for > 55 us to allow PCLK be enabled */
484 udelay(PLL_SET_DELAY_US);
485
486 /* Assert PCLK enabled */
487 if (lane == 2) {
488 reg_set(rh_vsreg_addr,
489 LANE_STAT1 + USB3PHY_LANE2_REG_BASE_OFFSET,
490 0xFFFFFFFF);
491 ret = comphy_poll_reg(rh_vsreg_data, /* address */
492 rb_txdclk_pclk_en, /* value */
493 rb_txdclk_pclk_en, /* mask */
494 POLL_32B_REG); /* 32bit */
495 } else {
496 ret = comphy_poll_reg(phy_addr(USB3, LANE_STAT1), /* address */
497 rb_txdclk_pclk_en, /* value */
498 rb_txdclk_pclk_en, /* mask */
499 POLL_16B_REG); /* 16bit */
500 }
501 if (!ret)
502 printf("Failed to lock USB3 PLL\n");
503
504 /*
505 * Set Soft ID for Host mode (Device mode works with Hard ID
506 * detection)
507 */
508 if (type == PHY_TYPE_USB3_HOST0) {
509 /*
510 * set BIT0: set ID_MODE of Host/Device = "Soft ID" (BIT1)
511 * clear BIT1: set SOFT_ID = Host
512 * set BIT4: set INT_MODE = ID. Interrupt Mode: enable
513 * interrupt by ID instead of using both interrupts
514 * of HOST and Device ORed simultaneously
515 * INT_MODE=ID in order to avoid unexpected
516 * behaviour or both interrupts together
517 */
518 reg_set(USB32_CTRL_BASE,
519 usb32_ctrl_id_mode | usb32_ctrl_int_mode,
520 usb32_ctrl_id_mode | usb32_ctrl_soft_id |
521 usb32_ctrl_int_mode);
522 }
523
524 debug_exit();
525
526 return ret;
527 }
528
529 /*
530 * comphy_usb2_power_up
531 *
532 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
533 */
comphy_usb2_power_up(u8 usb32)534 static int comphy_usb2_power_up(u8 usb32)
535 {
536 int ret;
537
538 debug_enter();
539
540 if (usb32 != 0 && usb32 != 1) {
541 printf("invalid usb32 value: (%d), should be either 0 or 1\n",
542 usb32);
543 debug_exit();
544 return 0;
545 }
546
547 /*
548 * 0. Setup PLL. 40MHz clock uses defaults.
549 * See "PLL Settings for Typical REFCLK" table
550 */
551 if (get_ref_clk() == 25) {
552 reg_set(USB2_PHY_BASE(usb32), 5 | (96 << 16),
553 0x3F | (0xFF << 16) | (0x3 << 28));
554 }
555
556 /*
557 * 1. PHY pull up and disable USB2 suspend
558 */
559 reg_set(USB2_PHY_CTRL_ADDR(usb32),
560 RB_USB2PHY_SUSPM(usb32) | RB_USB2PHY_PU(usb32), 0);
561
562 if (usb32 != 0) {
563 /*
564 * 2. Power up OTG module
565 */
566 reg_set(USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0);
567
568 /*
569 * 3. Configure PHY charger detection
570 */
571 reg_set(USB2_PHY_CHRGR_DET_ADDR, 0,
572 rb_cdp_en | rb_dcp_en | rb_pd_en | rb_cdp_dm_auto |
573 rb_enswitch_dp | rb_enswitch_dm | rb_pu_chrg_dtc);
574 }
575
576 /* Assert PLL calibration done */
577 ret = comphy_poll_reg(USB2_PHY_CAL_CTRL_ADDR(usb32),
578 rb_usb2phy_pllcal_done, /* value */
579 rb_usb2phy_pllcal_done, /* mask */
580 POLL_32B_REG); /* 32bit */
581 if (!ret)
582 printf("Failed to end USB2 PLL calibration\n");
583
584 /* Assert impedance calibration done */
585 ret = comphy_poll_reg(USB2_PHY_CAL_CTRL_ADDR(usb32),
586 rb_usb2phy_impcal_done, /* value */
587 rb_usb2phy_impcal_done, /* mask */
588 POLL_32B_REG); /* 32bit */
589 if (!ret)
590 printf("Failed to end USB2 impedance calibration\n");
591
592 /* Assert squetch calibration done */
593 ret = comphy_poll_reg(USB2_PHY_RX_CHAN_CTRL1_ADDR(usb32),
594 rb_usb2phy_sqcal_done, /* value */
595 rb_usb2phy_sqcal_done, /* mask */
596 POLL_32B_REG); /* 32bit */
597 if (!ret)
598 printf("Failed to end USB2 unknown calibration\n");
599
600 /* Assert PLL is ready */
601 ret = comphy_poll_reg(USB2_PHY_PLL_CTRL0_ADDR(usb32),
602 rb_usb2phy_pll_ready, /* value */
603 rb_usb2phy_pll_ready, /* mask */
604 POLL_32B_REG); /* 32bit */
605
606 if (!ret)
607 printf("Failed to lock USB2 PLL\n");
608
609 debug_exit();
610
611 return ret;
612 }
613
614 /*
615 * comphy_emmc_power_up
616 *
617 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
618 */
comphy_emmc_power_up(void)619 static int comphy_emmc_power_up(void)
620 {
621 debug_enter();
622
623 /*
624 * 1. Bus power ON, Bus voltage 1.8V
625 */
626 reg_set(SDIO_HOST_CTRL1_ADDR, 0xB00, 0xF00);
627
628 /*
629 * 2. Set FIFO parameters
630 */
631 reg_set(SDIO_SDHC_FIFO_ADDR, 0x315, 0xFFFFFFFF);
632
633 /*
634 * 3. Set Capabilities 1_2
635 */
636 reg_set(SDIO_CAP_12_ADDR, 0x25FAC8B2, 0xFFFFFFFF);
637
638 /*
639 * 4. Set Endian
640 */
641 reg_set(SDIO_ENDIAN_ADDR, 0x00c00000, 0);
642
643 /*
644 * 4. Init PHY
645 */
646 reg_set(SDIO_PHY_TIMING_ADDR, 0x80000000, 0x80000000);
647 reg_set(SDIO_PHY_PAD_CTRL0_ADDR, 0x50000000, 0xF0000000);
648
649 /*
650 * 5. DLL reset
651 */
652 reg_set(SDIO_DLL_RST_ADDR, 0xFFFEFFFF, 0);
653 reg_set(SDIO_DLL_RST_ADDR, 0x00010000, 0);
654
655 debug_exit();
656
657 return 1;
658 }
659
660 /*
661 * comphy_sgmii_power_up
662 *
663 * return:
664 */
comphy_sgmii_phy_init(u32 lane,u32 speed)665 static void comphy_sgmii_phy_init(u32 lane, u32 speed)
666 {
667 const int fix_arr_sz = ARRAY_SIZE(sgmii_phy_init_fix);
668 int addr, fix_idx;
669 u16 val;
670
671 fix_idx = 0;
672 for (addr = 0; addr < 512; addr++) {
673 /*
674 * All PHY register values are defined in full for 3.125Gbps
675 * SERDES speed. The values required for 1.25 Gbps are almost
676 * the same and only few registers should be "fixed" in
677 * comparison to 3.125 Gbps values. These register values are
678 * stored in "sgmii_phy_init_fix" array.
679 */
680 if ((speed != PHY_SPEED_1_25G) &&
681 (sgmii_phy_init_fix[fix_idx].addr == addr)) {
682 /* Use new value */
683 val = sgmii_phy_init_fix[fix_idx].value;
684 if (fix_idx < fix_arr_sz)
685 fix_idx++;
686 } else {
687 val = sgmii_phy_init[addr];
688 }
689
690 reg_set16(sgmiiphy_addr(lane, addr), val, 0xFFFF);
691 }
692 }
693
694 /*
695 * comphy_sgmii_power_up
696 *
697 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
698 */
comphy_sgmii_power_up(u32 lane,u32 speed,u32 invert)699 static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
700 {
701 int ret;
702 u32 saved_selector;
703
704 debug_enter();
705
706 /*
707 * 1. Configure PHY to SATA/SAS mode by setting pin PIN_PIPE_SEL=0
708 */
709 saved_selector = readl(COMPHY_SEL_ADDR);
710 reg_set(COMPHY_SEL_ADDR, 0, 0xFFFFFFFF);
711
712 /*
713 * 2. Reset PHY by setting PHY input port PIN_RESET=1.
714 * 3. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep
715 * PHY TXP/TXN output to idle state during PHY initialization
716 * 4. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0.
717 */
718 reg_set(COMPHY_PHY_CFG1_ADDR(lane),
719 rb_pin_reset_comphy | rb_pin_tx_idle | rb_pin_pu_iveref,
720 rb_pin_reset_core | rb_pin_pu_pll |
721 rb_pin_pu_rx | rb_pin_pu_tx);
722
723 /*
724 * 5. Release reset to the PHY by setting PIN_RESET=0.
725 */
726 reg_set(COMPHY_PHY_CFG1_ADDR(lane), 0, rb_pin_reset_comphy);
727
728 /*
729 * 7. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide
730 * COMPHY bit rate
731 */
732 if (speed == PHY_SPEED_3_125G) { /* 3.125 GHz */
733 reg_set(COMPHY_PHY_CFG1_ADDR(lane),
734 (0x8 << rf_gen_rx_sel_shift) |
735 (0x8 << rf_gen_tx_sel_shift),
736 rf_gen_rx_select | rf_gen_tx_select);
737
738 } else if (speed == PHY_SPEED_1_25G) { /* 1.25 GHz */
739 reg_set(COMPHY_PHY_CFG1_ADDR(lane),
740 (0x6 << rf_gen_rx_sel_shift) |
741 (0x6 << rf_gen_tx_sel_shift),
742 rf_gen_rx_select | rf_gen_tx_select);
743 } else {
744 printf("Unsupported COMPHY speed!\n");
745 return 0;
746 }
747
748 /*
749 * 8. Wait 1mS for bandgap and reference clocks to stabilize;
750 * then start SW programming.
751 */
752 mdelay(10);
753
754 /* 9. Program COMPHY register PHY_MODE */
755 reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL),
756 PHY_MODE_SGMII << rf_phy_mode_shift, rf_phy_mode_mask);
757
758 /*
759 * 10. Set COMPHY register REFCLK_SEL to select the correct REFCLK
760 * source
761 */
762 reg_set16(sgmiiphy_addr(lane, MISC_REG0), 0, rb_ref_clk_sel);
763
764 /*
765 * 11. Set correct reference clock frequency in COMPHY register
766 * REF_FREF_SEL.
767 */
768 if (get_ref_clk() == 40) {
769 reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL),
770 0x4 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask);
771 } else {
772 /* 25MHz */
773 reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL),
774 0x1 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask);
775 }
776
777 /* 12. Program COMPHY register PHY_GEN_MAX[1:0] */
778 /*
779 * This step is mentioned in the flow received from verification team.
780 * However the PHY_GEN_MAX value is only meaningful for other
781 * interfaces (not SGMII). For instance, it selects SATA speed
782 * 1.5/3/6 Gbps or PCIe speed 2.5/5 Gbps
783 */
784
785 /*
786 * 13. Program COMPHY register SEL_BITS to set correct parallel data
787 * bus width
788 */
789 /* 10bit */
790 reg_set16(sgmiiphy_addr(lane, DIG_LB_EN), 0, rf_data_width_mask);
791
792 /*
793 * 14. As long as DFE function needs to be enabled in any mode,
794 * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F
795 * for real chip during COMPHY power on.
796 */
797 /*
798 * The step 14 exists (and empty) in the original initialization flow
799 * obtained from the verification team. According to the functional
800 * specification DFE_UPDATE_EN already has the default value 0x3F
801 */
802
803 /*
804 * 15. Program COMPHY GEN registers.
805 * These registers should be programmed based on the lab testing
806 * result to achieve optimal performance. Please contact the CEA
807 * group to get the related GEN table during real chip bring-up.
808 * We only requred to run though the entire registers programming
809 * flow defined by "comphy_sgmii_phy_init" when the REF clock is
810 * 40 MHz. For REF clock 25 MHz the default values stored in PHY
811 * registers are OK.
812 */
813 debug("Running C-DPI phy init %s mode\n",
814 speed == PHY_SPEED_3_125G ? "2G5" : "1G");
815 if (get_ref_clk() == 40)
816 comphy_sgmii_phy_init(lane, speed);
817
818 /*
819 * 16. [Simulation Only] should not be used for real chip.
820 * By pass power up calibration by programming EXT_FORCE_CAL_DONE
821 * (R02h[9]) to 1 to shorten COMPHY simulation time.
822 */
823 /*
824 * 17. [Simulation Only: should not be used for real chip]
825 * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX
826 * training simulation time.
827 */
828
829 /*
830 * 18. Check the PHY Polarity invert bit
831 */
832 if (invert & PHY_POLARITY_TXD_INVERT)
833 reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_txd_inv, 0);
834
835 if (invert & PHY_POLARITY_RXD_INVERT)
836 reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_rxd_inv, 0);
837
838 /*
839 * 19. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1
840 * to start PHY power up sequence. All the PHY register
841 * programming should be done before PIN_PU_PLL=1. There should be
842 * no register programming for normal PHY operation from this point.
843 */
844 reg_set(COMPHY_PHY_CFG1_ADDR(lane),
845 rb_pin_pu_pll | rb_pin_pu_rx | rb_pin_pu_tx,
846 rb_pin_pu_pll | rb_pin_pu_rx | rb_pin_pu_tx);
847
848 /*
849 * 20. Wait for PHY power up sequence to finish by checking output ports
850 * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1.
851 */
852 ret = comphy_poll_reg(COMPHY_PHY_STAT1_ADDR(lane), /* address */
853 rb_pll_ready_tx | rb_pll_ready_rx, /* value */
854 rb_pll_ready_tx | rb_pll_ready_rx, /* mask */
855 POLL_32B_REG); /* 32bit */
856 if (!ret)
857 printf("Failed to lock PLL for SGMII PHY %d\n", lane);
858
859 /*
860 * 21. Set COMPHY input port PIN_TX_IDLE=0
861 */
862 reg_set(COMPHY_PHY_CFG1_ADDR(lane), 0x0, rb_pin_tx_idle);
863
864 /*
865 * 22. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1.
866 * to start RX initialization. PIN_RX_INIT_DONE will be cleared to
867 * 0 by the PHY. After RX initialization is done, PIN_RX_INIT_DONE
868 * will be set to 1 by COMPHY. Set PIN_RX_INIT=0 after
869 * PIN_RX_INIT_DONE= 1.
870 * Please refer to RX initialization part for details.
871 */
872 reg_set(COMPHY_PHY_CFG1_ADDR(lane), rb_phy_rx_init, 0x0);
873
874 ret = comphy_poll_reg(COMPHY_PHY_STAT1_ADDR(lane), /* address */
875 rb_rx_init_done, /* value */
876 rb_rx_init_done, /* mask */
877 POLL_32B_REG); /* 32bit */
878 if (!ret)
879 printf("Failed to init RX of SGMII PHY %d\n", lane);
880
881 /*
882 * Restore saved selector.
883 */
884 reg_set(COMPHY_SEL_ADDR, saved_selector, 0xFFFFFFFF);
885
886 debug_exit();
887
888 return ret;
889 }
890
comphy_dedicated_phys_init(void)891 void comphy_dedicated_phys_init(void)
892 {
893 int node, usb32, ret = 1;
894 const void *blob = gd->fdt_blob;
895
896 debug_enter();
897
898 for (usb32 = 0; usb32 <= 1; usb32++) {
899 /*
900 * There are 2 UTMI PHYs in this SOC.
901 * One is independendent and one is paired with USB3 port (OTG)
902 */
903 if (usb32 == 0) {
904 node = fdt_node_offset_by_compatible(
905 blob, -1, "marvell,armada3700-ehci");
906 } else {
907 node = fdt_node_offset_by_compatible(
908 blob, -1, "marvell,armada3700-xhci");
909 }
910
911 if (node > 0) {
912 if (fdtdec_get_is_enabled(blob, node)) {
913 ret = comphy_usb2_power_up(usb32);
914 if (!ret)
915 printf("Failed to initialize UTMI PHY\n");
916 else
917 debug("UTMI PHY init succeed\n");
918 } else {
919 debug("USB%d node is disabled\n",
920 usb32 == 0 ? 2 : 3);
921 }
922 } else {
923 debug("No USB%d node in DT\n", usb32 == 0 ? 2 : 3);
924 }
925 }
926
927 node = fdt_node_offset_by_compatible(blob, -1,
928 "marvell,armada-3700-ahci");
929 if (node > 0) {
930 if (fdtdec_get_is_enabled(blob, node)) {
931 ret = comphy_sata_power_up();
932 if (!ret)
933 printf("Failed to initialize SATA PHY\n");
934 else
935 debug("SATA PHY init succeed\n");
936 } else {
937 debug("SATA node is disabled\n");
938 }
939 } else {
940 debug("No SATA node in DT\n");
941 }
942
943 node = fdt_node_offset_by_compatible(blob, -1,
944 "marvell,armada-8k-sdhci");
945 if (node <= 0) {
946 node = fdt_node_offset_by_compatible(
947 blob, -1, "marvell,armada-3700-sdhci");
948 }
949
950 if (node > 0) {
951 if (fdtdec_get_is_enabled(blob, node)) {
952 ret = comphy_emmc_power_up();
953 if (!ret)
954 printf("Failed to initialize SDIO/eMMC PHY\n");
955 else
956 debug("SDIO/eMMC PHY init succeed\n");
957 } else {
958 debug("SDIO/eMMC node is disabled\n");
959 }
960 } else {
961 debug("No SDIO/eMMC node in DT\n");
962 }
963
964 debug_exit();
965 }
966
comphy_a3700_init(struct chip_serdes_phy_config * chip_cfg,struct comphy_map * serdes_map)967 int comphy_a3700_init(struct chip_serdes_phy_config *chip_cfg,
968 struct comphy_map *serdes_map)
969 {
970 struct comphy_map *comphy_map;
971 u32 comphy_max_count = chip_cfg->comphy_lanes_count;
972 u32 lane, ret = 0;
973
974 debug_enter();
975
976 /* Initialize PHY mux */
977 chip_cfg->mux_data = a3700_comphy_mux_data;
978 comphy_mux_init(chip_cfg, serdes_map, COMPHY_SEL_ADDR);
979
980 for (lane = 0, comphy_map = serdes_map; lane < comphy_max_count;
981 lane++, comphy_map++) {
982 debug("Initialize serdes number %d\n", lane);
983 debug("Serdes type = 0x%x invert=%d\n",
984 comphy_map->type, comphy_map->invert);
985
986 switch (comphy_map->type) {
987 case PHY_TYPE_UNCONNECTED:
988 continue;
989 break;
990
991 case PHY_TYPE_PEX0:
992 ret = comphy_pcie_power_up(comphy_map->speed,
993 comphy_map->invert);
994 break;
995
996 case PHY_TYPE_USB3_HOST0:
997 case PHY_TYPE_USB3_DEVICE:
998 ret = comphy_usb3_power_up(lane,
999 comphy_map->type,
1000 comphy_map->speed,
1001 comphy_map->invert);
1002 break;
1003
1004 case PHY_TYPE_SGMII0:
1005 case PHY_TYPE_SGMII1:
1006 ret = comphy_sgmii_power_up(lane, comphy_map->speed,
1007 comphy_map->invert);
1008 break;
1009
1010 default:
1011 debug("Unknown SerDes type, skip initialize SerDes %d\n",
1012 lane);
1013 ret = 1;
1014 break;
1015 }
1016 if (!ret)
1017 printf("PLL is not locked - Failed to initialize lane %d\n",
1018 lane);
1019 }
1020
1021 debug_exit();
1022 return ret;
1023 }
1024